Re: [EXT] Re: [Patch v9] driver/clk/clk-si5338: Add common clock framework driver for si5338

On 5/31/19 7:06 AM, Radu Nicolae Pirea wrote: > Caution: EXT Email > > Hi, > > @York I want to continue the work on this driver and I want to upstream > it. Are you OK with this? > > I saw later improvement suggestions related to the bindings and I will > make the changes. Radu, You are

Re: Layerscape behavior when a UE is detected

On 12/5/18 2:54 PM, Tracy Smith wrote: >>> Question 4) If so, will a panic ever be called if there is a hardware >>> uncorrectable memory failure? > >> No. It is up to upper layer of EDAC driver. Layerscape driver only reports >> CEs and UEs. > > Just to be clear, the upper layer of the EDAC

Re: Layerscape behavior when a UE is detected

On 12/5/18 2:54 PM, Tracy Smith wrote: >>> Question 4) If so, will a panic ever be called if there is a hardware >>> uncorrectable memory failure? > >> No. It is up to upper layer of EDAC driver. Layerscape driver only reports >> CEs and UEs. > > Just to be clear, the upper layer of the EDAC

Re: Patrol scrub questions

On 12/5/18 2:00 PM, Tracy Smith wrote: >> Single-bit errors are corrected by memory controller without involving >> software. > > Sorry for being verbose, but I need to explain the reason for the > questions below since I need to determine if a memory scrub is > required on layerscape and why.

Re: Patrol scrub questions

On 12/5/18 2:00 PM, Tracy Smith wrote: >> Single-bit errors are corrected by memory controller without involving >> software. > > Sorry for being verbose, but I need to explain the reason for the > questions below since I need to determine if a memory scrub is > required on layerscape and why.

Re: edac driver injection of uncorrected errors & utils

On 12/5/18 8:38 AM, Tracy Smith wrote: > This is more directed toward York for layerscape. I see some edac code > that seem to do periodic scrubs based on intervals or scrub rate, but > that is not needed for the layerscape driver to correct errors because > errors are scrubbed when found by the

Re: edac driver injection of uncorrected errors & utils

On 12/5/18 8:38 AM, Tracy Smith wrote: > This is more directed toward York for layerscape. I see some edac code > that seem to do periodic scrubs based on intervals or scrub rate, but > that is not needed for the layerscape driver to correct errors because > errors are scrubbed when found by the

Re: [PATCH RFC 1/2] drivers/edac: Add L1 and L2 error detection for A53 and A57

c6fa92cd99c5c301635%7C0%7C0%7C636567177956904165=xWmuUtS9dk7PSq1R11L%2F4vpoztnXATAPgtmiqytpnAs%3D=0 > ) > > Some comments below, I haven't looked in to edac or the manuals for A53/A57. > > On 15/03/18 00:17, York Sun wrote: >> Add error detection for A53 and A57 cores. Hardware

Re: [PATCH RFC 1/2] drivers/edac: Add L1 and L2 error detection for A53 and A57

c6fa92cd99c5c301635%7C0%7C0%7C636567177956904165=xWmuUtS9dk7PSq1R11L%2F4vpoztnXATAPgtmiqytpnAs%3D=0 > ) > > Some comments below, I haven't looked in to edac or the manuals for A53/A57. > > On 15/03/18 00:17, York Sun wrote: >> Add error detection for A53 and A57 cores. Hardware

Re: [PATCH RFC 1/2] drivers/edac: Add L1 and L2 error detection for A53 and A57

On 03/15/2018 08:07 AM, Mark Rutland wrote: > Hi York, > > On Wed, Mar 14, 2018 at 05:17:46PM -0700, York Sun wrote: >> Add error detection for A53 and A57 cores. Hardware error injection >> is supported on A53. Software error injection is supported on both. >> For hard

Re: [PATCH RFC 1/2] drivers/edac: Add L1 and L2 error detection for A53 and A57

On 03/15/2018 08:07 AM, Mark Rutland wrote: > Hi York, > > On Wed, Mar 14, 2018 at 05:17:46PM -0700, York Sun wrote: >> Add error detection for A53 and A57 cores. Hardware error injection >> is supported on A53. Software error injection is supported on both. >> For hard

Re: [PATCH RFC 1/2] drivers/edac: Add L1 and L2 error detection for A53 and A57

On 03/15/2018 03:18 AM, Borislav Petkov wrote: > On Thu, Mar 15, 2018 at 01:20:18AM +0000, York Sun wrote: >> The discussion led to using device tree to specify which cores have this >> feature. Since this feature is "implementation dependent", I can only >> conf

Re: [PATCH RFC 1/2] drivers/edac: Add L1 and L2 error detection for A53 and A57

On 03/15/2018 03:18 AM, Borislav Petkov wrote: > On Thu, Mar 15, 2018 at 01:20:18AM +0000, York Sun wrote: >> The discussion led to using device tree to specify which cores have this >> feature. Since this feature is "implementation dependent", I can only >> conf

Re: [PATCH RFC 1/2] drivers/edac: Add L1 and L2 error detection for A53 and A57

On 03/14/2018 06:08 PM, Borislav Petkov wrote: > On Wed, Mar 14, 2018 at 05:17:46PM -0700, York Sun wrote: >> Add error detection for A53 and A57 cores. Hardware error injection >> is supported on A53. Software error injection is supported on both. >> For hardware error inj

Re: [PATCH RFC 1/2] drivers/edac: Add L1 and L2 error detection for A53 and A57

On 03/14/2018 06:08 PM, Borislav Petkov wrote: > On Wed, Mar 14, 2018 at 05:17:46PM -0700, York Sun wrote: >> Add error detection for A53 and A57 cores. Hardware error injection >> is supported on A53. Software error injection is supported on both. >> For hardware error inj

[PATCH RFC 2/2] arm64: Update device tree for ls1043a and ls1046a to enable edac driver

Add edac node to enable error detection for L1 and L2 cache. Signed-off-by: York Sun <york@nxp.com> --- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 9 + arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 9 + 2 files changed, 18 insertions(+) diff --git a/arch/arm6

[PATCH RFC 2/2] arm64: Update device tree for ls1043a and ls1046a to enable edac driver

Add edac node to enable error detection for L1 and L2 cache. Signed-off-by: York Sun --- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 9 + arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 9 + 2 files changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl

[PATCH RFC 1/2] drivers/edac: Add L1 and L2 error detection for A53 and A57

in the driver. Failure to enable access disables hardware error injection. For error interrupt to work, another SMC call enables access to L2ECTLR_EL1. Failure to enable access disables interrupt for error reporting. Signed-off-by: York Sun <york@nxp.com> --- .../devicetree/bindings/edac/

[PATCH RFC 1/2] drivers/edac: Add L1 and L2 error detection for A53 and A57

in the driver. Failure to enable access disables hardware error injection. For error interrupt to work, another SMC call enables access to L2ECTLR_EL1. Failure to enable access disables interrupt for error reporting. Signed-off-by: York Sun --- .../devicetree/bindings/edac/cortex-arm64-edac.txt

Re: [PATCH] EDAC, layerscape: allow building for LS1021A

Then you are good to go. York Sent from my iPhone > On Feb 22, 2018, at 22:40, Rasmus Villemoes <rasmus.villem...@prevas.dk> > wrote: > >> On 2018-02-20 22:01, York Sun wrote: >> Sorry for top posting. I am on vacation and replying from my phone. >>

Re: [PATCH] EDAC, layerscape: allow building for LS1021A

Then you are good to go. York Sent from my iPhone > On Feb 22, 2018, at 22:40, Rasmus Villemoes > wrote: > >> On 2018-02-20 22:01, York Sun wrote: >> Sorry for top posting. I am on vacation and replying from my phone. >> >> The controller is compatible a

Re: [PATCH] EDAC, layerscape: allow building for LS1021A

Sorry for top posting. I am on vacation and replying from my phone. The controller is compatible and the driver should work. Please double check to make sure you can inject errors and receive interrupt. After that you are good to go. York Sent from my iPhone > On Feb 20, 2018, at 23:09,

Re: [PATCH] EDAC, layerscape: allow building for LS1021A

Sorry for top posting. I am on vacation and replying from my phone. The controller is compatible and the driver should work. Please double check to make sure you can inject errors and receive interrupt. After that you are good to go. York Sent from my iPhone > On Feb 20, 2018, at 23:09,

Re: [PATCH] config: ls1012aqds: Add USB EHCI support for ls1012aqds

On 09/14/2017 12:54 PM, York Sun wrote: > On 07/27/2017 03:05 AM, yinbo@nxp.com wrote: >> From: Rajesh Bhagat <rajesh.bha...@nxp.com> >> >> +#elif defined(CONFIG_LS102XA) || defined(CONFIG_ARCH_LS1012A) > > Please use CONFIG_ARCH_LS1021A, not CONFIG_LS102X

Re: [PATCH] config: ls1012aqds: Add USB EHCI support for ls1012aqds

On 09/14/2017 12:54 PM, York Sun wrote: > On 07/27/2017 03:05 AM, yinbo@nxp.com wrote: >> From: Rajesh Bhagat >> >> +#elif defined(CONFIG_LS102XA) || defined(CONFIG_ARCH_LS1012A) > > Please use CONFIG_ARCH_LS1021A, not CONFIG_LS102XA. > Never mind. This

Re: [PATCH] config: ls1012aqds: Add USB EHCI support for ls1012aqds

On 07/27/2017 03:05 AM, yinbo@nxp.com wrote: > From: Rajesh Bhagat > > Add USB EHCI support for ls1012aqds platform > > Signed-off-by: Rajat Srivastava > Signed-off-by: Rajesh Bhagat > Signed-off-by: yinbo.zhu

Re: [PATCH] config: ls1012aqds: Add USB EHCI support for ls1012aqds

On 07/27/2017 03:05 AM, yinbo@nxp.com wrote: > From: Rajesh Bhagat > > Add USB EHCI support for ls1012aqds platform > > Signed-off-by: Rajat Srivastava > Signed-off-by: Rajesh Bhagat > Signed-off-by: yinbo.zhu > --- > arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 + >

Re: [PATCH] edac: mpc85xx: implement "remove" for mpc85xx_pci_err_driver

On 11/15/2016 10:26 PM, yanjiang@windriver.com wrote: > From: Yanjiang Jin > > Tested on a T4240QDS board. > > If we execute the below steps without this patch: > > 1. modprobe mpc85xx_edac [The first insmod, everything is well.] > 2. modprobe -r mpc85xx_edac > 3.

Re: [PATCH] edac: mpc85xx: implement "remove" for mpc85xx_pci_err_driver

On 11/15/2016 10:26 PM, yanjiang@windriver.com wrote: > From: Yanjiang Jin > > Tested on a T4240QDS board. > > If we execute the below steps without this patch: > > 1. modprobe mpc85xx_edac [The first insmod, everything is well.] > 2. modprobe -r mpc85xx_edac > 3. modprobe mpc85xx_edac

Re: [Patch v9] driver/clk/clk-si5338: Add common clock framework driver for si5338

On 09/02/2016 07:04 AM, Rob Herring wrote: > On Fri, Aug 26, 2016 at 02:45:49PM -0700, York Sun wrote: >> From: York Sun <york...@freescale.com> >> >> SI5338 is a programmable clock generator. It has 4 sets of inputs, >> PLL, multisynth and dividers to make 4 ou

Re: [Patch v9] driver/clk/clk-si5338: Add common clock framework driver for si5338

On 09/02/2016 07:04 AM, Rob Herring wrote: > On Fri, Aug 26, 2016 at 02:45:49PM -0700, York Sun wrote: >> From: York Sun >> >> SI5338 is a programmable clock generator. It has 4 sets of inputs, >> PLL, multisynth and dividers to make 4 outputs. This driver splits &

Re: [Patch v4 9/9] arm64: Update device tree for Layerscape SoCs

On 08/30/2016 03:58 AM, Shawn Guo wrote: > On Tue, Aug 09, 2016 at 02:59:39PM -0700, York Sun wrote: >> Add DDR memory controller nodes to enable EDAC driver. >> >> Signed-off-by: York Sun <york@nxp.com> > > The patch subject is too general. I changed it

Re: [Patch v4 9/9] arm64: Update device tree for Layerscape SoCs

On 08/30/2016 03:58 AM, Shawn Guo wrote: > On Tue, Aug 09, 2016 at 02:59:39PM -0700, York Sun wrote: >> Add DDR memory controller nodes to enable EDAC driver. >> >> Signed-off-by: York Sun > > The patch subject is too general. I changed it to "arm64:

[Patch v9] driver/clk/clk-si5338: Add common clock framework driver for si5338

From: York Sun <york...@freescale.com> SI5338 is a programmable clock generator. It has 4 sets of inputs, PLL, multisynth and dividers to make 4 outputs. This driver splits them into multiple clocks to comply with common clock framework. See Documentation/devicetree/bindings/clock/silabs,

[Patch v9] driver/clk/clk-si5338: Add common clock framework driver for si5338

From: York Sun SI5338 is a programmable clock generator. It has 4 sets of inputs, PLL, multisynth and dividers to make 4 outputs. This driver splits them into multiple clocks to comply with common clock framework. See Documentation/devicetree/bindings/clock/silabs,si5338.txt for details

Re: [Patch v8] driver/clk/clk-si5338: Add common clock framework driver for si5338

On 08/23/2016 09:48 PM, Stephen Boyd wrote: > On 08/24, kbuild test robot wrote: >> >> 2827 if (drv_type < 0) >> 2828 return drv_type; >> 2829 >> 2830 drv_vdd = get_drv_vdd(drvdata, i); >> 2831 if (drv_vdd < 0) >>

Re: [Patch v8] driver/clk/clk-si5338: Add common clock framework driver for si5338

On 08/23/2016 09:48 PM, Stephen Boyd wrote: > On 08/24, kbuild test robot wrote: >> >> 2827 if (drv_type < 0) >> 2828 return drv_type; >> 2829 >> 2830 drv_vdd = get_drv_vdd(drvdata, i); >> 2831 if (drv_vdd < 0) >>

[Patch v5 8/9] driver/edac/layerscape_edac: Add Layerscape EDAC support

Add DDR EDAC for ARM-based compatible controllers. Both big-endian and little-endian are supported, as specified in device tree. Signed-off-by: York Sun <york@nxp.com> --- Change log v5: Update author and copyright for the new driver Drop initializing varaible with 0 Add

[Patch v5 8/9] driver/edac/layerscape_edac: Add Layerscape EDAC support

Add DDR EDAC for ARM-based compatible controllers. Both big-endian and little-endian are supported, as specified in device tree. Signed-off-by: York Sun --- Change log v5: Update author and copyright for the new driver Drop initializing varaible with 0 Add pr_fmt macro v4: Drop

Re: [Patch v4 9/9] arm64: Update device tree for Layerscape SoCs

+Shawn Guo On 08/09/2016 03:00 PM, York Sun wrote: > Add DDR memory controller nodes to enable EDAC driver. > > Signed-off-by: York Sun <york@nxp.com> > > --- > Change log > v4: no change > v3: no change > v2: no change > > arch/arm64/b

Re: [Patch v4 9/9] arm64: Update device tree for Layerscape SoCs

+Shawn Guo On 08/09/2016 03:00 PM, York Sun wrote: > Add DDR memory controller nodes to enable EDAC driver. > > Signed-off-by: York Sun > > --- > Change log > v4: no change > v3: no change > v2: no change > > arch/arm64/boot/dts/freescale/fsl-ls1043a.dts

[Patch v8] driver/clk/clk-si5338: Add common clock framework driver for si5338

From: York Sun <york...@freescale.com> SI5338 is a programmable clock generator. It has 4 sets of inputs, PLL, multisynth and dividers to make 4 outputs. This driver splits them into multiple clocks to comply with common clock framework. See Documentation/devicetree/bindings/clock/silabs,

[Patch v8] driver/clk/clk-si5338: Add common clock framework driver for si5338

From: York Sun SI5338 is a programmable clock generator. It has 4 sets of inputs, PLL, multisynth and dividers to make 4 outputs. This driver splits them into multiple clocks to comply with common clock framework. See Documentation/devicetree/bindings/clock/silabs,si5338.txt for details

[PATCH] drivers/edac/fsl_ddr: Replace simple_strtoul with kstrtoul

Replace obsolete simple_strtoul() with kstrtoul(). Signed-off-by: York Sun <york@nxp.com> --- drivers/edac/fsl_ddr_edac.c | 30 -- 1 file changed, 24 insertions(+), 6 deletions(-) diff --git a/drivers/edac/fsl_ddr_edac.c b/drivers/edac/fsl_ddr_edac.c

[PATCH] drivers/edac/fsl_ddr: Replace simple_strtoul with kstrtoul

Replace obsolete simple_strtoul() with kstrtoul(). Signed-off-by: York Sun --- drivers/edac/fsl_ddr_edac.c | 30 -- 1 file changed, 24 insertions(+), 6 deletions(-) diff --git a/drivers/edac/fsl_ddr_edac.c b/drivers/edac/fsl_ddr_edac.c index afade14..4ddf838 100644

Re: [Patch v4 8/9] driver/edac/layerscape_edac: Add Layerscape EDAC support

On 08/12/2016 02:13 AM, Borislav Petkov wrote: > On Tue, Aug 09, 2016 at 02:55:45PM -0700, York Sun wrote: >> Add DDR EDAC for ARM-based compatible controllers. Both big-endian >> and little-endian are supported, as specified in device tree. >> >> Signed-off-by:

Re: [Patch v4 8/9] driver/edac/layerscape_edac: Add Layerscape EDAC support

On 08/12/2016 02:13 AM, Borislav Petkov wrote: > On Tue, Aug 09, 2016 at 02:55:45PM -0700, York Sun wrote: >> Add DDR EDAC for ARM-based compatible controllers. Both big-endian >> and little-endian are supported, as specified in device tree. >> >> Signed-off-by: York S

Re: [Patch v4 3/9] driver/edac/fsl-ddr: Separate FSL DDR EDAC driver from MPC85xx

On 08/11/2016 06:36 AM, Borislav Petkov wrote: > On Tue, Aug 09, 2016 at 02:55:40PM -0700, York Sun wrote: >> The mpc85xx compatible DDR controllers are used on ARM-based SoCs. >> Separate the DDR part from mpc85xx EDAC driver and prepare to support >> both architecture. >

Re: [Patch v4 3/9] driver/edac/fsl-ddr: Separate FSL DDR EDAC driver from MPC85xx

On 08/11/2016 06:36 AM, Borislav Petkov wrote: > On Tue, Aug 09, 2016 at 02:55:40PM -0700, York Sun wrote: >> The mpc85xx compatible DDR controllers are used on ARM-based SoCs. >> Separate the DDR part from mpc85xx EDAC driver and prepare to support >> both architecture. >

[Patch v5 3/9] driver/edac/fsl-ddr: Separate FSL DDR EDAC driver from MPC85xx

The mpc85xx compatible DDR controllers are used on ARM-based SoCs. Separate the DDR part from mpc85xx EDAC driver and prepare to support both architecture. Signed-off-by: York Sun <york@nxp.com> --- Change log v5: Rebase onto git://git.kernel.org/pub/scm/linux/kernel/git/bp/

[Patch v5 3/9] driver/edac/fsl-ddr: Separate FSL DDR EDAC driver from MPC85xx

The mpc85xx compatible DDR controllers are used on ARM-based SoCs. Separate the DDR part from mpc85xx EDAC driver and prepare to support both architecture. Signed-off-by: York Sun --- Change log v5: Rebase onto git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp.git edac-for-4.9

Re: [Patch v4 3/9] driver/edac/fsl-ddr: Separate FSL DDR EDAC driver from MPC85xx

On 08/11/2016 06:36 AM, Borislav Petkov wrote: > > Please regenerate it against: > > http://git.kernel.org/cgit/linux/kernel/git/bp/bp.git#edac-for-4.9 > Will do. York

Re: [Patch v4 3/9] driver/edac/fsl-ddr: Separate FSL DDR EDAC driver from MPC85xx

On 08/11/2016 06:36 AM, Borislav Petkov wrote: > > Please regenerate it against: > > http://git.kernel.org/cgit/linux/kernel/git/bp/bp.git#edac-for-4.9 > Will do. York

[Patch v4 7/9] driver/edac/fsl_ddr: Fix kernel warning when module is removed

When compiled as a module, removing this module causes kernel warnings when irq_dispose_mapping() is called. Instead of calling irq_of_parse_and_map(), using platform_get_irq() to acquire the IRQ number. Signed-off-by: York Sun <york@nxp.com> --- Change log v4: Absorb name c

[Patch v4 7/9] driver/edac/fsl_ddr: Fix kernel warning when module is removed

When compiled as a module, removing this module causes kernel warnings when irq_dispose_mapping() is called. Instead of calling irq_of_parse_and_map(), using platform_get_irq() to acquire the IRQ number. Signed-off-by: York Sun --- Change log v4: Absorb name changes by "Rename m

[Patch v4 6/9] driver/edac/fsl_ddr: Add support of little endian

Get endianness from device tree. Both big endian and little endian are supported. Default to big endian for backward compatibility to MPC85xx. Signed-off-by: York Sun <york@nxp.com> --- Change log v4: Absorb name changes by "Rename macros and names" Drop testin

[Patch v4 6/9] driver/edac/fsl_ddr: Add support of little endian

Get endianness from device tree. Both big endian and little endian are supported. Default to big endian for backward compatibility to MPC85xx. Signed-off-by: York Sun --- Change log v4: Absorb name changes by "Rename macros and names" Drop testing for big-endian as suggested

[Patch v4 9/9] arm64: Update device tree for Layerscape SoCs

Add DDR memory controller nodes to enable EDAC driver. Signed-off-by: York Sun <york@nxp.com> --- Change log v4: no change v3: no change v2: no change arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 7 +++ arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 14 +++

[Patch v4 9/9] arm64: Update device tree for Layerscape SoCs

Add DDR memory controller nodes to enable EDAC driver. Signed-off-by: York Sun --- Change log v4: no change v3: no change v2: no change arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 7 +++ arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 14 ++ 2 files changed, 21

[Patch v4 8/9] driver/edac/layerscape_edac: Add Layerscape EDAC support

Add DDR EDAC for ARM-based compatible controllers. Both big-endian and little-endian are supported, as specified in device tree. Signed-off-by: York Sun <york@nxp.com> --- Change log v4: Drop adding atomic_scrub() for arm64 Drop NO_IRQ v3: no change v2: Create new driver

[Patch v4 8/9] driver/edac/layerscape_edac: Add Layerscape EDAC support

Add DDR EDAC for ARM-based compatible controllers. Both big-endian and little-endian are supported, as specified in device tree. Signed-off-by: York Sun --- Change log v4: Drop adding atomic_scrub() for arm64 Drop NO_IRQ v3: no change v2: Create new driver using shared DDR object

[Patch v4 3/9] driver/edac/fsl-ddr: Separate FSL DDR EDAC driver from MPC85xx

The mpc85xx compatible DDR controllers are used on ARM-based SoCs. Separate the DDR part from mpc85xx EDAC driver and prepare to support both architecture. Signed-off-by: York Sun <york@nxp.com> --- Change log v4: Change comment in file header Use lower case "f

[Patch v4 3/9] driver/edac/fsl-ddr: Separate FSL DDR EDAC driver from MPC85xx

The mpc85xx compatible DDR controllers are used on ARM-based SoCs. Separate the DDR part from mpc85xx EDAC driver and prepare to support both architecture. Signed-off-by: York Sun --- Change log v4: Change comment in file header Use lower case "fsl_ddr_edac" for EDAC_MOD_STR

[Patch v4 5/9] driver/edac/fsl_ddr: Add DDR types

The compatible DDR controllers may support DDR, DDR2, DDR3, DDR4. An individual controller doesn't support all of them. EDAC driver reads the controller to determine which mode is running. Signed-off-by: York Sun <york@nxp.com> --- Change log v4: Drop DSC_SDTYPE_DDR* macros, use

[Patch v4 1/9] driver/edac/mpc85xx_edac: Drop setting/clearing RFXE bit in HID1

support this bit. It is more reasonable to leave RFXE as is in EDAC driver, and leave the uncorrectable errors triggering machine check for e500v1. Signed-off-by: York Sun <york@nxp.com> Suggested-by: Scott Wood <o...@buserror.net> --- Change log v4: Fix typo in commit message

[Patch v4 4/9] driver/edac/fsl_ddr: Rename macros and names

Use generic names for macros, variables and functions. Signed-off-by: York Sun <york@nxp.com> --- Change log v4: Replace MPC85XX_MC_* with FSL_MC_* v3: Absort changes from reording patches v2: Separated from "House cleaning" patch of v1 drivers/edac/fsl_

[Patch v4 2/9] driver/edac/mpc85xx_edac: Replace printk with proper pr_* format

Replace printk with more preferred pr_err/pr_warn/pr_info format. Signed-off-by: York Sun <york@nxp.com> --- Change log v4: no change v3: no change v2: Reordered patch. Change more printk statement than v1 patch. drivers/edac/mpc85xx_edac.

[Patch v4 5/9] driver/edac/fsl_ddr: Add DDR types

The compatible DDR controllers may support DDR, DDR2, DDR3, DDR4. An individual controller doesn't support all of them. EDAC driver reads the controller to determine which mode is running. Signed-off-by: York Sun --- Change log v4: Drop DSC_SDTYPE_DDR* macros, use naked numbers as suggested

[Patch v4 1/9] driver/edac/mpc85xx_edac: Drop setting/clearing RFXE bit in HID1

support this bit. It is more reasonable to leave RFXE as is in EDAC driver, and leave the uncorrectable errors triggering machine check for e500v1. Signed-off-by: York Sun Suggested-by: Scott Wood --- Change log v4: Fix typo in commit message v3: Revise commit message v2: new patch

[Patch v4 4/9] driver/edac/fsl_ddr: Rename macros and names

Use generic names for macros, variables and functions. Signed-off-by: York Sun --- Change log v4: Replace MPC85XX_MC_* with FSL_MC_* v3: Absort changes from reording patches v2: Separated from "House cleaning" patch of v1 drivers/edac/fsl_ddr_ed

[Patch v4 2/9] driver/edac/mpc85xx_edac: Replace printk with proper pr_* format

Replace printk with more preferred pr_err/pr_warn/pr_info format. Signed-off-by: York Sun --- Change log v4: no change v3: no change v2: Reordered patch. Change more printk statement than v1 patch. drivers/edac/mpc85xx_edac.c | 72 ++--- 1 file

Re: [Patch v3 03/11] driver/edac/mpc85xx_edac: Drop setting/clearing RFXE bit in HID1

On 08/08/2016 11:56 PM, Borislav Petkov wrote: > On Tue, Aug 09, 2016 at 05:06:39AM +0000, york sun wrote: >> It is uncorrectable. DDR controller can only report the error. I don't >> believe EDAC driver can do more. For the same reason I said we can leave >> RXFE as is,

Re: [Patch v3 03/11] driver/edac/mpc85xx_edac: Drop setting/clearing RFXE bit in HID1

On 08/08/2016 11:56 PM, Borislav Petkov wrote: > On Tue, Aug 09, 2016 at 05:06:39AM +0000, york sun wrote: >> It is uncorrectable. DDR controller can only report the error. I don't >> believe EDAC driver can do more. For the same reason I said we can leave >> RXFE as is,

Re: [Patch v3 03/11] driver/edac/mpc85xx_edac: Drop setting/clearing RFXE bit in HID1

On 08/09/2016 08:57 AM, york@nxp.com wrote: > On 08/08/2016 11:56 PM, Borislav Petkov wrote: >> On Tue, Aug 09, 2016 at 05:06:39AM +0000, york sun wrote: >>> It is uncorrectable. DDR controller can only report the error. I don't >>> believe EDAC driver can do more.

Re: [Patch v3 03/11] driver/edac/mpc85xx_edac: Drop setting/clearing RFXE bit in HID1

On 08/09/2016 08:57 AM, york@nxp.com wrote: > On 08/08/2016 11:56 PM, Borislav Petkov wrote: >> On Tue, Aug 09, 2016 at 05:06:39AM +0000, york sun wrote: >>> It is uncorrectable. DDR controller can only report the error. I don't >>> believe EDAC driver can do more.

Re: [Patch v3 10/11] driver/edac/layerscape_edac: Add Layerscape EDAC support

On 08/09/2016 04:12 AM, Will Deacon wrote: > On Mon, Aug 08, 2016 at 07:56:04PM +0000, york sun wrote: >> On 08/08/2016 11:07 AM, Marc Zyngier wrote: >>> On Thu, 4 Aug 2016 15:58:35 -0700 >>> York Sun <york@nxp.com> wrote: >>> >>>> Add D

Re: [Patch v3 10/11] driver/edac/layerscape_edac: Add Layerscape EDAC support

On 08/09/2016 04:12 AM, Will Deacon wrote: > On Mon, Aug 08, 2016 at 07:56:04PM +0000, york sun wrote: >> On 08/08/2016 11:07 AM, Marc Zyngier wrote: >>> On Thu, 4 Aug 2016 15:58:35 -0700 >>> York Sun wrote: >>> >>>> Add DDR EDAC for A

Re: [Patch v3 03/11] driver/edac/mpc85xx_edac: Drop setting/clearing RFXE bit in HID1

On 08/08/2016 10:01 PM, Borislav Petkov wrote: > On Tue, Aug 09, 2016 at 04:31:19AM +0000, york sun wrote: >> Yes, for most SoCs RFXE remains cleared. Uncorrectable errors are >> handled by EDAC. > > And how is mpc85_xxx EDAC handling them? > > mpc85xx_mc_check()

Re: [Patch v3 03/11] driver/edac/mpc85xx_edac: Drop setting/clearing RFXE bit in HID1

On 08/08/2016 10:01 PM, Borislav Petkov wrote: > On Tue, Aug 09, 2016 at 04:31:19AM +0000, york sun wrote: >> Yes, for most SoCs RFXE remains cleared. Uncorrectable errors are >> handled by EDAC. > > And how is mpc85_xxx EDAC handling them? > > mpc85xx_mc_check()

Re: [Patch v3 03/11] driver/edac/mpc85xx_edac: Drop setting/clearing RFXE bit in HID1

On 08/08/2016 08:32 PM, Borislav Petkov wrote: > On Mon, Aug 08, 2016 at 03:39:44PM +0000, york sun wrote: >> RFXE is cleared by default. So for most SoCs, this is not even a concern >> at all. But for e500v1, when RIO or PCI are used, this bit is set >> specifically to catc

Re: [Patch v3 03/11] driver/edac/mpc85xx_edac: Drop setting/clearing RFXE bit in HID1

On 08/08/2016 08:32 PM, Borislav Petkov wrote: > On Mon, Aug 08, 2016 at 03:39:44PM +0000, york sun wrote: >> RFXE is cleared by default. So for most SoCs, this is not even a concern >> at all. But for e500v1, when RIO or PCI are used, this bit is set >> specifically to catc

Re: [Patch v3 08/11] driver/edac/fsl_ddr: Add support of little endian

On 08/08/2016 01:50 AM, Borislav Petkov wrote: > On Thu, Aug 04, 2016 at 03:58:33PM -0700, York Sun wrote: >> Get endianness from device tree. Both big endian and little endian >> are supported. Default to big endian for backward compatibility to >> MPC85xx. >> >&

Re: [Patch v3 08/11] driver/edac/fsl_ddr: Add support of little endian

On 08/08/2016 01:50 AM, Borislav Petkov wrote: > On Thu, Aug 04, 2016 at 03:58:33PM -0700, York Sun wrote: >> Get endianness from device tree. Both big endian and little endian >> are supported. Default to big endian for backward compatibility to >> MPC85xx. >>

Re: [Patch v3 07/11] driver/edac/fsl_ddr: Add DDR4 type

On 08/08/2016 01:31 AM, Borislav Petkov wrote: > On Thu, Aug 04, 2016 at 03:58:32PM -0700, York Sun wrote: > > <--- Missing commit message. > >> Signed-off-by: York Sun <york@nxp.com> >> >> --- >> Change log >> v3: no change >>

Re: [Patch v3 07/11] driver/edac/fsl_ddr: Add DDR4 type

On 08/08/2016 01:31 AM, Borislav Petkov wrote: > On Thu, Aug 04, 2016 at 03:58:32PM -0700, York Sun wrote: > > <--- Missing commit message. > >> Signed-off-by: York Sun >> >> --- >> Change log >> v3: no change >> v2: no change >> >

Re: [Patch v3 10/11] driver/edac/layerscape_edac: Add Layerscape EDAC support

On 08/08/2016 11:07 AM, Marc Zyngier wrote: > On Thu, 4 Aug 2016 15:58:35 -0700 > York Sun <york@nxp.com> wrote: > >> Add DDR EDAC for ARM-based compatible controllers. Both big-endian >> and little-endian are supported. >> >> Signed-off-by: York Sun <

Re: [Patch v3 10/11] driver/edac/layerscape_edac: Add Layerscape EDAC support

On 08/08/2016 11:07 AM, Marc Zyngier wrote: > On Thu, 4 Aug 2016 15:58:35 -0700 > York Sun wrote: > >> Add DDR EDAC for ARM-based compatible controllers. Both big-endian >> and little-endian are supported. >> >> Signed-off-by: York Sun >> >> --- >

Re: [Patch v3 01/11] arch/powerpc/pci: Fix compiling error for mpc85xx_edac

On 08/05/2016 12:01 AM, Borislav Petkov wrote: > On Fri, Aug 05, 2016 at 04:26:26AM +0000, york sun wrote: >> I don't have deep knowledge of this driver. What I am trying is to >> separate the common DDR part and share it with ARM platforms. Along the >> way, I found the com

Re: [Patch v3 01/11] arch/powerpc/pci: Fix compiling error for mpc85xx_edac

On 08/05/2016 12:01 AM, Borislav Petkov wrote: > On Fri, Aug 05, 2016 at 04:26:26AM +0000, york sun wrote: >> I don't have deep knowledge of this driver. What I am trying is to >> separate the common DDR part and share it with ARM platforms. Along the >> way, I found the com

Re: [Patch v3 05/11] driver/edac/fsl-ddr: Separate FSL DDR EDAC driver from MPC85xx

On 08/08/2016 12:37 AM, Borislav Petkov wrote: > On Thu, Aug 04, 2016 at 03:58:30PM -0700, York Sun wrote: >> The mpc85xx compatible DDR controllers are used on ARM-based SoCs. >> Separate the DDR part from mpc85xx EDAC driver and prepare to support >> both architecture. >

Re: [Patch v3 05/11] driver/edac/fsl-ddr: Separate FSL DDR EDAC driver from MPC85xx

On 08/08/2016 12:37 AM, Borislav Petkov wrote: > On Thu, Aug 04, 2016 at 03:58:30PM -0700, York Sun wrote: >> The mpc85xx compatible DDR controllers are used on ARM-based SoCs. >> Separate the DDR part from mpc85xx EDAC driver and prepare to support >> both architecture. >

Re: [Patch v3 03/11] driver/edac/mpc85xx_edac: Drop setting/clearing RFXE bit in HID1

On 08/08/2016 12:11 AM, Borislav Petkov wrote: > On Thu, Aug 04, 2016 at 03:58:28PM -0700, York Sun wrote: >> On e500v1, read fault exception enable (RFXE) controls whether >> assertion of core_fault_in causes a machine check interrupt. >> Assertion of core_fault_in can resu

Re: [Patch v3 03/11] driver/edac/mpc85xx_edac: Drop setting/clearing RFXE bit in HID1

On 08/08/2016 12:11 AM, Borislav Petkov wrote: > On Thu, Aug 04, 2016 at 03:58:28PM -0700, York Sun wrote: >> On e500v1, read fault exception enable (RFXE) controls whether >> assertion of core_fault_in causes a machine check interrupt. >> Assertion of core_fault_in can resu

Re: [Patch v3 10/11] driver/edac/layerscape_edac: Add Layerscape EDAC support

On 08/08/2016 01:57 AM, Alexander Stein wrote: > On Thursday 04 August 2016 15:58:35, York Sun wrote: >> Add DDR EDAC for ARM-based compatible controllers. Both big-endian >> and little-endian are supported. >> >> Signed-off-by: York Sun <york@nxp.com>

Re: [Patch v3 10/11] driver/edac/layerscape_edac: Add Layerscape EDAC support

On 08/08/2016 01:57 AM, Alexander Stein wrote: > On Thursday 04 August 2016 15:58:35, York Sun wrote: >> Add DDR EDAC for ARM-based compatible controllers. Both big-endian >> and little-endian are supported. >> >> Signed-off-by: York Sun >> >> --- >>

Re: [Patch v3 06/11] driver/edac/fsl_ddr: Rename macros and names

On 08/08/2016 12:41 AM, Borislav Petkov wrote: > On Thu, Aug 04, 2016 at 03:58:31PM -0700, York Sun wrote: >> Use generic names for macros, variables and functions. >> >> Signed-off-by: York Sun <york@nxp.com> >> >> --- >> Change log >> v3

Re: [Patch v3 06/11] driver/edac/fsl_ddr: Rename macros and names

On 08/08/2016 12:41 AM, Borislav Petkov wrote: > On Thu, Aug 04, 2016 at 03:58:31PM -0700, York Sun wrote: >> Use generic names for macros, variables and functions. >> >> Signed-off-by: York Sun >> >> --- >> Change log >> v3: Absort changes from pre

Re: [Patch v3 01/11] arch/powerpc/pci: Fix compiling error for mpc85xx_edac

On 08/04/2016 08:43 PM, Michael Ellerman wrote: > York Sun <york@nxp.com> writes: > >> Two symbols are missing if mpc85xx_edac driver is compiled as module. >> >> Signed-off-by: York Sun <york@nxp.com> >> >> --- >> Change log >

Re: [Patch v3 01/11] arch/powerpc/pci: Fix compiling error for mpc85xx_edac

On 08/04/2016 08:43 PM, Michael Ellerman wrote: > York Sun writes: > >> Two symbols are missing if mpc85xx_edac driver is compiled as module. >> >> Signed-off-by: York Sun >> >> --- >> Change log >> v3: Change subject tag >> v2: no chang

Re: [Patch v3 01/11] arch/powerpc/pci: Fix compiling error for mpc85xx_edac

On 08/05/2016 02:09 PM, Scott Wood wrote: > On Fri, 2016-08-05 at 20:29 +0000, york sun wrote: >> On 08/04/2016 08:43 PM, Michael Ellerman wrote: >>> >>> Does the driver really need to use these routines? They're meant for use >>> early in boot, before PCI i

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