This patch removes a bit of duplicated code by introducing a new
function that implements calculations for DMA copy size.
Suggested-by: Vinod Koul
Signed-off-by: Andrea Merello
---
Changes in v4:
- introduce this patch in the patch series
---
drivers/dma/xilinx/xilinx_dma.c | 20
be needed to cause lock
> acquisition to provide full ordering.
IIRC, ctrl+isync is even *weaker* than lwsync in certain respects, e.g.,
the former doesn't provide A-cumulativity according to the architectural
intent.
>The reason for using lwsync instead
> of isync is that the for
Commit-ID: 71b7ff5ebc9b1d5aa95eb48d6388234f1304fd19
Gitweb: https://git.kernel.org/tip/71b7ff5ebc9b1d5aa95eb48d6388234f1304fd19
Author: Andrea Parri
AuthorDate: Mon, 16 Jul 2018 11:06:05 -0700
Committer: Ingo Molnar
CommitDate: Tue, 17 Jul 2018 09:30:36 +0200
tools/memory-model
Commit-ID: 7696f9910a9a40b8a952f57d3428515fabd2d889
Gitweb: https://git.kernel.org/tip/7696f9910a9a40b8a952f57d3428515fabd2d889
Author: Andrea Parri
AuthorDate: Mon, 16 Jul 2018 11:06:03 -0700
Committer: Ingo Molnar
CommitDate: Tue, 17 Jul 2018 09:30:34 +0200
sched/Documentation
Commit-ID: 3d85b2703783636366560c94842affd8608ec9d1
Gitweb: https://git.kernel.org/tip/3d85b2703783636366560c94842affd8608ec9d1
Author: Andrea Parri
AuthorDate: Mon, 16 Jul 2018 11:06:02 -0700
Committer: Ingo Molnar
CommitDate: Tue, 17 Jul 2018 09:30:33 +0200
locking/spinlock, sched
Commit-ID: 76e079fefc8f62bd9b2cd2950814d1ee806e31a5
Gitweb: https://git.kernel.org/tip/76e079fefc8f62bd9b2cd2950814d1ee806e31a5
Author: Andrea Parri
AuthorDate: Mon, 16 Jul 2018 11:06:01 -0700
Committer: Ingo Molnar
CommitDate: Tue, 17 Jul 2018 09:30:33 +0200
sched/core: Use smp_mb
o manage
> to make SYNC happen :-) :-)
One trivia about seems due: it's of course very easy to stick a full
or a "tso" fence in one's spin_lock() implementation, or to tight the
semantics of such a primitive; removing this fence, or weakening the
semantics is another matter...
(/me reminding about that spin_is_locked() discussion...)
Andrea
onversation, would probably be to run/check the
above snippets against the (latest) LKMM, by using the associated tool.
Once "checked" with both people and automated models, I'd probably remain
suspicious about my "magic" code so that I most likely will be prompted to
dig into each single arch. implementation / reference manual...
... Time's up!
Andrea
> loop:
> lr.w.aq a0, [lock] // lock()
> sc.w t1, [lock] // lock()
> bnez loop // lock()
> (b) ...
>
> However, if (a) and (b) are loads to different addresses, then (a) is not
> ordered before (b) here. One unpaired RCsc operation is not a full fence.
&
On Thu, Jul 12, 2018 at 11:13:48PM +0200, Andrea Parri wrote:
> On Thu, Jul 12, 2018 at 04:43:46PM -0400, Alan Stern wrote:
> > On Thu, 12 Jul 2018, Andrea Parri wrote:
> >
> > > > It seems reasonable to ask people to learn that locks have stronger
> > > >
On Thu, Jul 12, 2018 at 04:43:46PM -0400, Alan Stern wrote:
> On Thu, 12 Jul 2018, Andrea Parri wrote:
>
> > > It seems reasonable to ask people to learn that locks have stronger
> > > ordering guarantees than RMW atomics do. Maybe not the greatest
> > > situat
On Thu, Jul 12, 2018 at 09:52:42PM +0200, Andrea Parri wrote:
> On Thu, Jul 12, 2018 at 11:10:58AM -0700, Linus Torvalds wrote:
> > On Thu, Jul 12, 2018 at 11:05 AM Peter Zijlstra
> > wrote:
> > >
> > > The locking pattern is fairly simple and shows where RCpc c
>
> How nasty would be be to make powerpc conform? I will always advocate
> tighter locking and ordering rules over looser ones..
A simple answer is right above (place a sync somewhere in the sequence);
for benchmark results, I must defer...
Andrea
>
>Linus
d up with the v3 patch. If the first
> answer is No and the second is Yes, we end up with the v2 patch. The
> problem is that different people seem to want differing answers.
Again, maybe you're confonding v2 with v1?
Andrea
>
> (The implicit third question, "S
(0)" for all the supported arch. _if_
we sticked to the current implementations, and (2) even if these
implementations changed or some new arch. required a non-trivial
definition, we still would have to find a "pure/TSO" case ;-).
Andrea
On Thu, Jul 12, 2018 at 01:52:49PM +0200, Andrea Parri wrote:
> On Thu, Jul 12, 2018 at 09:40:40AM +0200, Peter Zijlstra wrote:
> > On Wed, Jul 11, 2018 at 02:34:21PM +0200, Andrea Parri wrote:
> > > Simplicity is the eye of the beholder. From my POV (LKMM maintainer), the
>
On Thu, Jul 12, 2018 at 09:40:40AM +0200, Peter Zijlstra wrote:
> On Wed, Jul 11, 2018 at 02:34:21PM +0200, Andrea Parri wrote:
> > Simplicity is the eye of the beholder. From my POV (LKMM maintainer), the
> > simplest solution would be to get rid of rfi-rel-acq and unlock-rf-lock
quot; of this barrier back in:
362a61ad61199e ("fix SMP data race in pagetable setup vs walking")
c.f., the comment in mm/memory.c:__pte_alloc(), but that does not
math our pattern (UNLOCK+LOCK), AFAICT.
Andrea
>
> [1] https://lkml.org/lkml/2015/10/6/805
>
> Dan
s we currently support today, so
> the next best thing is this "everything apart from W->R in the
> inter-thread case" ordering, which isn't going to crop up unless you're
> doing weird stuff anyway afaict.
The "average kernel developer" thinks TSO or about, right? ;-)
Andrea
>
> Will
t; >
> > > Signed-off-by: Alan Stern
> >
> > Thanks, I'm happy with this version of the patch:
> >
> > Reviewed-by: Will Deacon
>
> I have applied your Reviewed-by, and thank you both!
>
> Given that this is a non-trivial cha
On Wed, Jul 11, 2018 at 02:34:21PM +0200, Andrea Parri wrote:
> On Wed, Jul 11, 2018 at 10:43:11AM +0100, Will Deacon wrote:
> > On Tue, Jul 10, 2018 at 11:38:21AM +0200, Andrea Parri wrote:
> > > On Mon, Jul 09, 2018 at 04:01:57PM -0400, Alan Stern wrote:
> > > >
On Wed, Jul 11, 2018 at 10:43:11AM +0100, Will Deacon wrote:
> On Tue, Jul 10, 2018 at 11:38:21AM +0200, Andrea Parri wrote:
> > On Mon, Jul 09, 2018 at 04:01:57PM -0400, Alan Stern wrote:
> > > More than one kernel developer has expressed the opinion that the LKMM
> > >
spin_lock(s); /* A */
spin_unlock(s);
spin_lock(s);
WRITE_ONCE(*x, 1); /* B */
spin_unlock(s);
}
P1(spinlock_t *s, int *x)
{
int r0;
int r1;
r0 = READ_ONCE(*x); /* C */
smp_rmb();
r1 = spin_is_locked(s); /* D */
}
With v3, it's allowed that C reads from B and D reads from (the LKW of) A;
this is not allowed with v2 (unless I mis-applied/mis-read v2).
Andrea
On Tue, Jul 10, 2018 at 11:34:45AM -0400, Alan Stern wrote:
> On Tue, 10 Jul 2018, Andrea Parri wrote:
>
> > > > ACQUIRE operations include LOCK operations and both smp_load_acquire()
> > > > and smp_cond_acquire() operations. [BTW, the latter was replaced by
&
.
Interesting; ;-) What does these statement tells you ;-) when applied
to a: and b: below?
a: WRITE_ONCE(x, 1); // "preceding any prior RELEASE..."
smp_store_release(&s, 1);
smp_load_acquire(&s);
b: WRITE_ONCE(y, 1); // "after an ACQUIRE..."
Andrea
Amend commit 1f03e8d2919270 ("locking/barriers: Replace smp_cond_acquire()
with smp_cond_load_acquire()") by updating the documentation accordingly.
Signed-off-by: Andrea Parri
Cc: Alan Stern
Cc: Will Deacon
Cc: Peter Zijlstra
Cc: Boqun Feng
Cc: Nicholas Piggin
Cc: David Howells
D_ONCE(x);
> + smp_store_release(&s, 1); // Value is forwarded
> +
> +and thus it could load y before x, obtaining r2 = 0 and r1 = 1.
> +
> +Second, when a lock-acquire reads from a lock-release, and some other
> +stores W and W' occur po-before the lock-r
s the smp_mb().
Compare implementations of xchg() and xchg_relaxed(). The following could
also be helpful (in addition to the references pointed out earlier):
Documentation/atomic_t.txt
Andrea
>
> Guo Ren
>
riers.txt
tools/memory-model/
(and please do not hesitate to ask questions about them, if something is
unclear).
Andrea
On Thu, Jul 05, 2018 at 08:38:36PM +0200, Andrea Parri wrote:
> > No, I'm definitely not pushing for anything stronger. I'm still just
> > wondering if the name "RCsc" is right for what you described. For
> > example, Andrea just said this in a paralle
> No, I'm definitely not pushing for anything stronger. I'm still just
> wondering if the name "RCsc" is right for what you described. For
> example, Andrea just said this in a parallel email:
>
> > "RCsc" as ordering everything except for W ->
On Thu, Jul 05, 2018 at 09:58:48AM -0700, Paul E. McKenney wrote:
> On Thu, Jul 05, 2018 at 05:39:06PM +0200, Andrea Parri wrote:
> > > > At any rate, it looks like instead of strengthening the relation, I
> > > > should write a patch that removes it ent
> Only in the presence of smp_mb__after_unlock_lock() or
> smp_mb__after_spinlock(), correct? Or am I confused about RCsc?
There are at least two definitions of RCsc: one as documented in the header
comment for smp_mb__after_spinlock() or rather in the patch under review...,
one as processor architects
ease keep an eye on the (generic)
queued_spin_lock()
queued_spin_unlock()
(just to point out an example). Their implementation (in part.,
the fast-path) suggests that if we will stick to RCsc lock then
we should also stick to RCsc acq. load from RMW and rel. store.
Andrea
>
> Alan
>
On Wed, Jul 04, 2018 at 01:11:04PM +0100, Will Deacon wrote:
> Hi Alan,
>
> On Tue, Jul 03, 2018 at 01:28:17PM -0400, Alan Stern wrote:
> > On Mon, 25 Jun 2018, Andrea Parri wrote:
> >
> > > On Fri, Jun 22, 2018 at 07:30:08PM +0100, Will Deacon wrote:
> > >
previous code was correct for x86 because of course huge_ptep_get is
implemented as *ptep on x86.
For now the current fix is certainly good, any robustness cleanup is
cleaner if done orthogonal anyway.
Thanks!
Andrea
Paul E. McKenney
> Cc: Alan Stern
> Cc: Andrea Parri
> Cc: Will Deacon
> Cc: Peter Zijlstra
> Cc: Boqun Feng
> Cc: Nicholas Piggin
> Cc: David Howells
> Cc: Jade Alglave
> Cc: Luc Maranget
> Cc: Akira Yokosawa
> C
ust asking the question.)
I don't think we *should* ;-), but I'm also OK either way.
Andrea
refcount_inc_not_zero);
> * Will WARN if the refcount is 0, as this represents a possible
> use-after-free
> * condition.
> */
> -void refcount_inc(refcount_t *r)
> +void refcount_inc_chcked(refcount_t *r)
s/chcked/checked
Andrea
(Of course, this will need ACK from the ATOMIC people).
>
> If the merging will take awhile, it might also be good to put
> Documentation/core-api/atomic_ops.rst somewhere as well.
Indeed. And let's not forget the "orphaned":
Documentation/atomic_bitops.txt
Documentation/core-api/refcount-vs-atomic.rst
;-)
Andrea
the barrier to illustrate the
requirements and to link them to the idioms which are relied upon at its
call sites.
Suggested-by: Boqun Feng
Signed-off-by: Andrea Parri
Cc: Peter Zijlstra
Cc: Ingo Molnar
Cc: Will Deacon
Cc: "Paul E. McKenney"
---
Changes since v1:
- reworked th
On Fri, Jun 29, 2018 at 9:37 AM, Vinod wrote:
> On 25-06-18, 11:27, Andrea Merello wrote:
>> The AXIDMA and CDMA HW can be either direct-access or scatter-gather
>> version. These are SW incompatible.
>>
>> The driver can handle both version
On Fri, Jun 29, 2018 at 9:25 AM, Vinod wrote:
> On 25-06-18, 11:27, Andrea Merello wrote:
>> Whenever a single or cyclic transaction is prepared, the driver
>> could eventually split it over several SG descriptors in order
>> to deal with the HW maximum transfer length.
>&
reviewers for their
patch. (Of course, this will need ACK from the ATOMIC people).
Andrea
th the contemporary codebase.
>
> Thanks,
> Mark.
>
> Mark Rutland (2):
> tools/memory-model: remove ACCESS_ONCE() from recipes
> tools/memory-model: remove ACCESS_ONCE() from model
For the series:
Acked-by: Andrea Parri
Cheers,
Andrea
>
> tools/memory-mode
call kasan_check_read() on __ai_ptr.
Maybe I'm misreading the diff: aren't you calling kasan_check_write()?
(not sure if it makes a difference in this case/for KTSan, but CMPXCHG
does not necessarily perform a write...)
Andrea
>
> * invoke the arch_ function, passing the
The width of the "length register" cannot be autodetected, and it is now
specified with a DT property. Add DOC for it.
Cc: Rob Herring
Cc: Mark Rutland
Cc: devicet...@vger.kernel.org
Cc: Radhey Shyam Pandey
Signed-off-by: Andrea Merello
Reviewed-by: Radhey Shyam Pandey
---
Cha
This property is not needed anymore, because the driver now autodetects it.
Delete references in documentation.
Cc: Rob Herring
Cc: Mark Rutland
Cc: devicet...@vger.kernel.org
Cc: Radhey Shyam Pandey
Signed-off-by: Andrea Merello
Reviewed-by: Radhey Shyam Pandey
---
Changes in v2
.
Cc: Rob Herring
Cc: Mark Rutland
Cc: devicet...@vger.kernel.org
Signed-off-by: Radhey Shyam Pandey
Signed-off-by: Michal Simek
Signed-off-by: Andrea Merello [rebase, reword]
---
Changes in v2:
- drop original patch and replace with the one in Xilinx tree
Changes in v3:
-
.
This patch eventually adjusts the transfer size in order to make sure
all operations start from an aligned address.
Cc: Radhey Shyam Pandey
Signed-off-by: Andrea Merello
Reviewed-by: Radhey Shyam Pandey
---
Changes in v2:
- don't introduce copy_mask field, rather rely on already-esi
. The DT
property is not required anymore.
No changes for VDMA.
Cc: Rob Herring
Cc: Mark Rutland
Cc: devicet...@vger.kernel.org
Cc: Radhey Shyam Pandey
Signed-off-by: Andrea Merello
Reviewed-by: Radhey Shyam Pandey
---
Changes in v2:
- autodetect only in !VDMA case
Changes in v3
quire+release are very much simpler operations
> than lock+unlock.
>
> At the very least, lock includes a control-dependency, where acquire
> does not.
I don't see how this is relevant here; roughly, "if something is guaranteed
by a control-dependency, that is also guaranteed by an acquire". Right? ;)
Andrea
t unlikely that they will have
> acquire loads that are similar in semantics to LDAPR. This patch prevents
> them from doing so,
By this same argument, you should not be a "big fan" of rfi-rel-acq in ppo ;)
consider, e.g., the two litmus tests below: what am I missing?
Andrea
C MP+fe
y inbox, but I'm far from an expert in
> >this stuff. He requested to be added as a reviewer, which seem sane to
Nit: which seems
> >me as it'll take a human out of the loop.
> >
> >CC: Daniel Lustig
> >Acked-by: Daniel Lustig
> >
-V (and I missed it in my earlier review): the 2nd
snippet from the commit message would map to something like
fence rw, w
STORE #1,[x]
LOAD [x]
fence r ,rw
STORE #1,[y]
and there would be no guarantee that the stores to x and y will be
propagated in program order to another CPU, AFAICT. Thank you for
pointing this out.
Andrea
by the Linux kernel (including RISC-V)
> do behave this way, albeit for varying reasons. Therefore this patch
> changes the model in accordance with the developers' wishes.
>
> Signed-off-by: Alan Stern
This patch changes the "Result" for ISA2+pooncelock+poonce
e, the new rule will still
> provide ordering. In the fr case, we also have ordering because there
> must be a co link to the same destination starting from the
> write-release.
>
> Signed-off-by: Alan Stern
Reviewed-by: Andrea Parri
Andrea
>
> ---
>
>
.
This patch eventually adjusts the transfer size in order to make sure
all operations start from an aligned address.
Signed-off-by: Andrea Merello
---
Changes in v2:
- don't introduce copy_mask field, rather rely on already-esistent
copy_align field. Suggested by Radhey
The width of the "length register" cannot be autodetected, and it is now
specified with a DT property. Add DOC for it.
Cc: Rob Herring
Signed-off-by: Andrea Merello
---
Changes in v2:
- change property name
- property is now optional
- cc DT maintainer
---
Doc
This property is not needed anymore, because the driver now autodetects it.
Delete references in documentation.
Cc: Rob Herring
Signed-off-by: Andrea Merello
---
Changes in v2:
- cc DT maintainer
---
Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 3 ---
1 file changed, 3
. The DT
property is not required anymore.
No changes for VDMA.
Signed-off-by: Andrea Merello
---
Changes in v2:
- autodetect only in !VDMA case
---
drivers/dma/xilinx/xilinx_dma.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/dma/xilinx
hange.
Signed-off-by: Radhey Shyam Pandey
Signed-off-by: Michal Simek
Signed-off-by: Andrea Merello [rebase, reword]
---
Changes in v2:
- drop original patch and replace with the one in Xilinx tree
---
drivers/dma/xilinx/xilinx_dma.c | 39 +++--
1 file change
On Wed, Jun 20, 2018 at 4:43 PM, Radhey Shyam Pandey wrote:
>> -Original Message-
>> From: dmaengine-ow...@vger.kernel.org [mailto:dmaengine-
>> ow...@vger.kernel.org] On Behalf Of Andrea Merello
>> Sent: Wednesday, June 20, 2018 2:07 PM
>> To: vk...@kernel
On Wed, Jun 20, 2018 at 2:36 PM, Radhey Shyam Pandey wrote:
>> -Original Message-
>> From: dmaengine-ow...@vger.kernel.org [mailto:dmaengine-
>> ow...@vger.kernel.org] On Behalf Of Andrea Merello
>> Sent: Wednesday, June 20, 2018 2:07 PM
>> To: vk...@kernel
On Wed, Jun 20, 2018 at 1:37 PM, Radhey Shyam Pandey wrote:
>> -Original Message-
>> From: dmaengine-ow...@vger.kernel.org [mailto:dmaengine-
>> ow...@vger.kernel.org] On Behalf Of Andrea Merello
>> Sent: Wednesday, June 20, 2018 2:07 PM
>> To: vk...@kernel
adjusts the transfer size in order to make sure
all operations start from an aligned address.
Signed-off-by: Andrea Merello
---
drivers/dma/xilinx/xilinx_dma.c | 27 ---
1 file changed, 20 insertions(+), 7 deletions(-)
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers
-by: Andrea Merello
---
drivers/dma/xilinx/xilinx_dma.c | 24 +---
1 file changed, 17 insertions(+), 7 deletions(-)
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index cf12f7147f07..bdbc8ba9092a 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b
is not required anymore.
Signed-off-by: Andrea Merello
---
drivers/dma/xilinx/xilinx_dma.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index bdbc8ba9092a..8c6e818e596f 100644
--- a/drivers/dma
This property is not needed anymore, because the driver now autodetects it.
Delete references in documentation.
Signed-off-by: Andrea Merello
---
Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 3 ---
1 file changed, 3 deletions(-)
diff --git a/Documentation/devicetree/bindings
The width of the "length register" cannot be autodetected, and it is now
specified with a DT property. Add DOC for it.
Signed-off-by: Andrea Merello
---
Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/
t;xilinx_dma: IrqThreshold set incorrectly, unreliable.")
in my linux-4.6-zynq tree
From: Jeremy Trimble [original patch]
Signed-off-by: Andrea Merello
---
drivers/dma/xilinx/xilinx_dma.c | 39 +
1 file changed, 25 insertions(+), 14 deletions(-)
diff --git
From: Andrea Greco
Add devicetree bindings for smsc com20020
Signed-off-by: Andrea Greco
---
.../devicetree/bindings/net/smsc-com20020.txt | 21 +
1 file changed, 21 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/smsc-com20020.txt
diff --git
From: Andrea Greco
Setup ethtols for export com20020 diag register
Signed-off-by: Andrea Greco
---
drivers/net/arcnet/com20020-io.c | 1 +
drivers/net/arcnet/com20020-isa.c | 1 +
drivers/net/arcnet/com20020.c | 24
drivers/net/arcnet/com20020.h | 1
From: Andrea Greco
If com20020 clock is major of 40Mhz SLOWARB bit is requested.
Signed-off-by: Andrea Greco
---
drivers/net/arcnet/com20020.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/net/arcnet/com20020.c b/drivers/net/arcnet/com20020.c
index 8d979a66d8e9..1a0fd30fe8ae
From: Andrea Greco
Add devicetree bindings for smsc com20020
Signed-off-by: Andrea Greco
---
.../devicetree/bindings/net/smsc-com20020.txt | 21 +
1 file changed, 21 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/smsc-com20020.txt
diff --git
From: Andrea Greco
Add support for com20022I/com20020, io mapped.
Signed-off-by: Andrea Greco
---
drivers/net/arcnet/Kconfig | 9 +-
drivers/net/arcnet/Makefile | 1 +
drivers/net/arcnet/com20020-io.c | 315 +++
drivers/net/arcnet/com20020.c
From: Andrea Greco
Add IO callback. No logic change are intended.
Now every driver implementation could specify IO callback.
Default IO callback is provided.
Signed-off-by: Andrea Greco
---
drivers/net/arcnet/arcdevice.h| 4 ++
drivers/net/arcnet/com20020-isa.c | 21 --
drivers/net
From: Andrea Greco
Only PCI driver depends from leds class.
Signed-off-by: Andrea Greco
---
drivers/net/arcnet/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/arcnet/Kconfig b/drivers/net/arcnet/Kconfig
index 39bd16f3f86d..afc5898e7a16 100644
--- a
t; ...saw the last days in upstream commits that kbuild/kconfig for
> 4.18-rc1 offers possibilities to check for cc-version dependencies.
Good to know! Mind retrieving/sharing the commit id(s)
or links to the corresponding discussion on LKML?
Thanks,
Andrea
>
> - sed@ -
ejia...@gmail.com
> Signed-off-by: Jia He
> Cc: Suzuki K Poulose
> Cc: Andrea Arcangeli
> Cc: Minchan Kim
> Cc: Claudio Imbrenda
> Cc: Arvind Yadav
> Cc: Mike Rapoport
> Cc: Jia He
> Cc:
> Signed-off-by: Andrew Morton
> ---
>
Reviewed-by: Andrea Arcangeli
iler barrier,
due to:
raw_spin_lock_irqsave(&p->pi_lock, flags);
smp_mb__after_spinlock();
The pattern under discussion isn't clear to me, but if you'll end up relying
on this "implicit" barrier I'd suggest documenting it with a comment.
Andrea
then
> immediately read the value back from it. For the purposes of
> litmus-test code generation, Rfi acts identically to PosWR.
> However, they differ for purposes of naming, and they also result
> in different "exists" clauses.
> Example: ???
LGTM, thanks.
Andrea
norm7 produces the 'normalized' name of a litmus test, when the test
can be generated from a single cycle that passes through each process
exactly once. The commit renames such tests in order to comply to the
naming scheme implemented by this tool.
Signed-off-by: Andrea Parri
Cc: Alan
ove is a partial list. To see the full list of
> descriptors, execute the following command:
>
> $ diyone7 -bell linux-kernel.bell -show edges
Thanks. One more nit: I'd indent this and the above "norm7" commands as
we do in our "main" README.
>
> > I al
[] r0 y ;
r[] r1 y | r[] r1 x ;
exists
(0:r0=1 /\ 0:r1=0 /\ 1:r0=1 /\ 1:r1=0)
> +Wse: Write same external. The current process wrote to a variable that
> + was also written to by the previous process. Example: ???
> +Wsi: Write same internal. The current process wrote to a variable and
> + then immediately wrote to it again. Example: ???
The list of descriptors is incomplete; the command:
$ diyone7 -bell linux-kernel.bell -show edges
shows other descriptors (including fences and dependencies). We might
want to list this command; searching the commit history, I found:
3c24730ef6c662 ("gen: Add a new command line option -show
(edges|fences|annotations) that list various categories of candidate
relaxations.")
I also notice that our current names for tests with fences (and cycle)
deviate from the corresponding 'norm7' results; e.g.,
$ norm7 -bell linux-kernel.bell FenceWmbdWW Once Rfe Once FenceRmbdRR Once
Fre Once | sed -e 's/:.*//g'
MP+fencewmbonceonce+fencermbonceonce
while we use 'MP+wmbonceonce+rmbonceonce' (that is, we omit the 'fence'
prefixes).
Andrea
>
suspended parent and can
> do nothing but call exec so they should never show up. Threads of the
> same cgroup are not the thread group leader so also should not show up.
> That leaves the old LinuxThreads library which is probably out of use by
"probably"???
> now, an
_atomic" is so "suggestive"!
(think at x86...), but it's not explicit in the proposed names.
I don't have other names to suggest at the moment... ;/ (aka just saying)
Andrea
>
> IIUC, the void-returning atomic ops are relaxed, so trying to unify that
gt;val, 0, -1);
}
void write_unlock(rwlock_t *s)
{
atomic_set_release(&s->val, 0);
}
filter (~read_lock:r0=-1 /\ write_lock:r0=0)
[...]
> The code is done, I'm just working on the rework for documention stuff,
> so if anyone is interested, could try it out ;-)
Any idea on how to "educate" the LKMM about this code/documentation?
Andrea
?
If your confirm that, ready for: Reviewed-by
Regards, Andrea
On 05/18/2018 07:51 PM, David Miller wrote:
From: Andrea Greco
Date: Fri, 18 May 2018 14:18:41 +0200
In com20020.c found this:
/* FIXME: do this some other way! */
if (!dev->dev_addr[0])
dev->dev_addr[0] = arcnet_inb(ioaddr, 8);
NODE-ID, must be univoque, for all arcnet network.
My pr
On 05/17/2018 10:31 PM, David Miller wrote:
> From: Andrea Greco
> Date: Thu, 17 May 2018 15:05:29 +0200
>
>> + /* Will be set by userspace during if setup */
>> + dev->dev_addr[0] = 0;
>
> Hmmm... really?
>
> Also, every error path from this point forward wil
From: Andrea Greco
Setup ethtols for export com20020 diag register
Signed-off-by: Andrea Greco
---
drivers/net/arcnet/com20020-io.c | 1 +
drivers/net/arcnet/com20020-isa.c | 1 +
drivers/net/arcnet/com20020.c | 24
drivers/net/arcnet/com20020.h | 1
From: Andrea Greco
If com20020 clock is major of 40Mhz SLOWARB bit is requested.
Signed-off-by: Andrea Greco
---
drivers/net/arcnet/com20020.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/net/arcnet/com20020.c b/drivers/net/arcnet/com20020.c
index 2fd00d2dd6bf..f1de02f05305
From: Andrea Greco
Add devicetree bindings for smsc com20020
Signed-off-by: Andrea Greco
---
.../devicetree/bindings/net/smsc-com20020.txt | 21 +
1 file changed, 21 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/smsc-com20020.txt
diff --git
From: Andrea Greco
Add support for com20022I/com20020, io mapped.
Signed-off-by: Andrea Greco
---
drivers/net/arcnet/Kconfig | 9 +-
drivers/net/arcnet/Makefile | 1 +
drivers/net/arcnet/arcdevice.h | 14 ++
drivers/net/arcnet/com20020-io.c | 287
the table. I'd also suggest
sticking to the three entries documented in
Documentation/features/arch-support.txt
and using the header comment to provide any additional information.
A script that refreshes the arch support status file in place (from
the Kconfig files) is currently available in linux-next: c.f.,
Documentation/features/scripts/features-refresh.sh
Andrea
Commit-ID: 1a00b4554d477f05199e22ee71ba4c2525ca44cb
Gitweb: https://git.kernel.org/tip/1a00b4554d477f05199e22ee71ba4c2525ca44cb
Author: Andrea Parri
AuthorDate: Mon, 14 May 2018 16:33:56 -0700
Committer: Ingo Molnar
CommitDate: Tue, 15 May 2018 08:11:18 +0200
tools/memory-model
Commit-ID: 99c12749b172758f6973fc023484f2fc8b91cd5a
Gitweb: https://git.kernel.org/tip/99c12749b172758f6973fc023484f2fc8b91cd5a
Author: Andrea Parri
AuthorDate: Mon, 14 May 2018 16:33:57 -0700
Committer: Ingo Molnar
CommitDate: Tue, 15 May 2018 08:11:19 +0200
tools/memory-model: Add
Commit-ID: 5ccdb7536ebec7a5f8a3883ba1985a80cec80dd3
Gitweb: https://git.kernel.org/tip/5ccdb7536ebec7a5f8a3883ba1985a80cec80dd3
Author: Andrea Parri
AuthorDate: Mon, 14 May 2018 16:33:55 -0700
Committer: Ingo Molnar
CommitDate: Tue, 15 May 2018 08:11:18 +0200
MAINTAINERS, tools/memory
Commit-ID: 05604e7e3adbd78f074b7f86b14f50888bf66252
Gitweb: https://git.kernel.org/tip/05604e7e3adbd78f074b7f86b14f50888bf66252
Author: Andrea Parri
AuthorDate: Mon, 14 May 2018 16:33:54 -0700
Committer: Ingo Molnar
CommitDate: Tue, 15 May 2018 08:11:18 +0200
tools/memory-model: Fix
901 - 1000 of 2931 matches
Mail list logo
