On Tue, 12 Jul 2016 12:16:19 +0100
Colin King wrote:
> From: Colin Ian King
>
> According to the HPT366 data sheet, PCI config space dword 0x40-0x43
> bits 11:8 specify the primary drive cmd_high_time, however,
> currently just 3 bits of the 4 are being used because the mask
> is 0x700 and not
On Tue, Jul 12, 2016 at 12:16:19PM +0100, Colin King wrote:
> From: Colin Ian King
>
> According to the HPT366 data sheet, PCI config space dword 0x40-0x43
> bits 11:8 specify the primary drive cmd_high_time, however,
> currently just 3 bits of the 4 are being used because the mask
> is 0x700 and
On 12/07/16 12:27, Bartlomiej Zolnierkiewicz wrote:
>
> Hi,
>
> On Tuesday, July 12, 2016 12:16:19 PM Colin King wrote:
>> From: Colin Ian King
>>
>> According to the HPT366 data sheet, PCI config space dword 0x40-0x43
>> bits 11:8 specify the primary drive cmd_high_time, however,
>> currently j
Hi,
On Tuesday, July 12, 2016 12:16:19 PM Colin King wrote:
> From: Colin Ian King
>
> According to the HPT366 data sheet, PCI config space dword 0x40-0x43
> bits 11:8 specify the primary drive cmd_high_time, however,
> currently just 3 bits of the 4 are being used because the mask
> is 0x700 a
From: Colin Ian King
According to the HPT366 data sheet, PCI config space dword 0x40-0x43
bits 11:8 specify the primary drive cmd_high_time, however,
currently just 3 bits of the 4 are being used because the mask
is 0x700 and not 0x0f00. Fix the mask, allowing for the 40MHz clock
to be detected.
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