On Mon, Jul 20, 2020 at 11:15:54AM +0200, Peter Zijlstra wrote:
> On Fri, Jul 17, 2020 at 03:34:07PM -0700, Ira Weiny wrote:
> > On Fri, Jul 17, 2020 at 10:59:54AM +0200, Peter Zijlstra wrote:
> > > On Fri, Jul 17, 2020 at 12:20:43AM -0700, ira.we...@intel.com wrote:
> > > > +/*
> > > > + * Write t
On Fri, Jul 17, 2020 at 03:34:07PM -0700, Ira Weiny wrote:
> On Fri, Jul 17, 2020 at 10:59:54AM +0200, Peter Zijlstra wrote:
> > On Fri, Jul 17, 2020 at 12:20:43AM -0700, ira.we...@intel.com wrote:
> > > +/*
> > > + * Write the PKey Register Supervisor. This must be run with preemption
> > > + * d
On Fri, Jul 17, 2020 at 10:59:54AM +0200, Peter Zijlstra wrote:
> On Fri, Jul 17, 2020 at 12:20:43AM -0700, ira.we...@intel.com wrote:
> > +/*
> > + * Write the PKey Register Supervisor. This must be run with preemption
> > + * disabled as it does not guarantee the atomicity of updating the
> > p
On Fri, Jul 17, 2020 at 10:31:40AM +0200, Peter Zijlstra wrote:
> On Fri, Jul 17, 2020 at 12:20:43AM -0700, ira.we...@intel.com wrote:
>
> > diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
> > index f362ce0d5ac0..d69250a7c1bf 100644
> > --- a/arch/x86/kernel/process.c
> > +++ b/
On Fri, Jul 17, 2020 at 12:20:43AM -0700, ira.we...@intel.com wrote:
> +/*
> + * Write the PKey Register Supervisor. This must be run with preemption
> + * disabled as it does not guarantee the atomicity of updating the pkrs_cache
> + * and MSR on its own.
> + */
> +void write_pkrs(u32 pkrs_val)
>
On Fri, Jul 17, 2020 at 12:20:43AM -0700, ira.we...@intel.com wrote:
> diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
> index f362ce0d5ac0..d69250a7c1bf 100644
> --- a/arch/x86/kernel/process.c
> +++ b/arch/x86/kernel/process.c
> @@ -42,6 +42,7 @@
> #include
> #include
> #
From: Ira Weiny
The PKRS MSR is defined as a per-logical-processor register. This
isolates memory access by CPU. Unfortunately, the MSR is not managed
by XSAVE. Therefore, We must preserve the protections for individual
tasks even if they are context switched out and placed on another cpu
late
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