>>>Also, which SPI NOR is this enabled for? I don't see any Micron entries in
>>>spi_nor_ids[] which contain the SPI_NOR_QUAD_READ flag.
>>
>> Yes, we now don't see any Micron entries in spi_nor_ids[] which
>> contain the SPI_NOR_QUAD_READ flag. But Micron spi nor in
>> spi_nor_ids[] all suppor
On Thu, Nov 27, 2014 at 05:55:43AM +, bpqw wrote:
> >What's the difference between using EVCR and the ENTER QUAD I/O MODE
> >(35h) command I see in some of your datasheets? Are both supported on all
> >Micron quad I/O SPI NOR flash?
>
> There is no difference between using EVCR and the ENTE
>First of all, can you fix your mail so that you have a proper 'From'?
>That should be your real name (not bpqw), so that it gives a proper patch
>author.
>If you can't get your mail header to have the right 'From:' line, then it also
>works to begin your mail with:
Sorry for this confusion. Th
First of all, can you fix your mail so that you have a proper 'From'?
That should be your real name (not bpqw), so that it gives a proper
patch author. If you can't get your mail header to have the right
'From:' line, then it also works to begin your mail with:
From: Your Name
On Thu, Nov 06, 20
>You probably aren't based on l2-mtd.git. Your patch still doesn't build.
>I can fix it up if it's easy, but FYI. Still reviewing...
>Brian
Hi, Brian
Thanks for your hard work. Finally received your response, I am very happy.
How about this patch? Whether or not rebuild it based on lastest l2-mt
On Thu, Nov 06, 2014 at 03:09:06AM +, bpqw wrote:
> This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes.
>
> For Micron SPI NOR flash,enabling or disabling quad I/O protocol is controlled
> by EVCR (Enhanced Volatile Configuration Register), Quad I/O protocol bit 7.
> Wh
>> This maybe your spi controller is still extended mode, Once EVCR bit 7
>> is set to 0, the spi nor device will operate in quad
>> I/O.Command-address-data line is 4-x-4.
>> So after send WRITE EVCR command , spi controller also must transfer
>> to quad I/O Mode,and set its Command-address-da
On Wed, 12 Nov 2014, bpqw wrote:
> This maybe your spi controller is still extended mode,
> Once EVCR bit 7 is set to 0, the spi nor device will operate in quad
> I/O.Command-address-data line is 4-x-4.
> So after send WRITE EVCR command , spi controller also must transfer to quad
> I/O Mode
>I have almost verified all the micros parts for operating quad mode and the
>quad enable bit is
>volatile by default and no need to set it on software.
>Why this code is meant for - does micron has changed this bit operation on
>newly added parts?
>thanks!
>--
>Jagan.
For Micron Spi norflash
>Hi, I'm having trouble with this patch using a Cadence QSPI controller and
>Micron n25q00 part.
>I can use quad commands in Extended SPI mode, but I can't make this EVCR Quad
>mode work.
Yes,but if you use quad commands in Extended spi mode,only for Quad
commands,the command line is DQ0,
Add
On 12 November 2014 01:11, Graham Moore wrote:
> On 11/05/2014 09:09 PM, bpqw wrote:
>> This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes.
>>
>> For Micron SPI NOR flash,enabling or disabling quad I/O protocol is
>> controlled
>> by EVCR (Enhanced Volatile Configuration Re
On 11/05/2014 09:09 PM, bpqw wrote:
> This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes.
>
> For Micron SPI NOR flash,enabling or disabling quad I/O protocol is
> controlled
> by EVCR (Enhanced Volatile Configuration Register), Quad I/O protocol bit 7.
> When EVCR bit 7 is
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