On Thu, Mar 30, 2017 at 05:37:41PM +0200, Olliver Schinagl wrote:
> Hey Jon,
>
> On March 30, 2017 3:42:19 PM CEST, Jon Hunter wrote:
> >
> >On 29/03/17 19:48, Olliver Schinagl wrote:
> >> The tegra serial IP seems to be following the common layout and the
> >> interrupt ID's match up nicely. Rep
kernel.org; linux-te...@vger.kernel.org;
linux-kernel@vger.kernel.org; Shardar Mohammed
Subject: Re: [PATCH] serial: tegra: Map the iir register to default
defines
On Thursday 30 March 2017 12:18 AM, Olliver Schinagl wrote:
The tegra serial IP seems to be following the common layout and the
inte
> > From: Laxman Dewangan
> > Sent: Thursday, March 30, 2017 3:48 PM
> > To: Olliver Schinagl ; Greg Kroah-Hartman
> > ; Jiri Slaby ; Stephen
> > Warren ; Thierry Reding
> > ; Alexandre Courbot
> > Cc: linux-ser...@vger.kernel.org; linux-te...@vger.
rnel.org; linux-te...@vger.kernel.org;
> linux-kernel@vger.kernel.org; Shardar Mohammed
> Subject: Re: [PATCH] serial: tegra: Map the iir register to default defines
>
>
> On Thursday 30 March 2017 12:18 AM, Olliver Schinagl wrote:
>> The tegra serial IP seems to be followin
rnel@vger.kernel.org; Shardar Mohammed
Subject: Re: [PATCH] serial: tegra: Map the iir register to default defines
On Thursday 30 March 2017 12:18 AM, Olliver Schinagl wrote:
> The tegra serial IP seems to be following the common layout and the
> interrupt ID's match up nicely. Re
Hey Jon,
On March 30, 2017 3:42:19 PM CEST, Jon Hunter wrote:
>
>On 29/03/17 19:48, Olliver Schinagl wrote:
>> The tegra serial IP seems to be following the common layout and the
>> interrupt ID's match up nicely. Replace the magic values to match the
>> common serial_reg defines, with the additi
On 29/03/17 19:48, Olliver Schinagl wrote:
> The tegra serial IP seems to be following the common layout and the
> interrupt ID's match up nicely. Replace the magic values to match the
> common serial_reg defines, with the addition of the Tegra unique End of
> Data interrupt.
>
> Signed-off-by: O
On Thursday 30 March 2017 12:18 AM, Olliver Schinagl wrote:
The tegra serial IP seems to be following the common layout and the
interrupt ID's match up nicely. Replace the magic values to match the
common serial_reg defines, with the addition of the Tegra unique End of
Data interrupt.
Signed-of
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