On Fri, May 29, 2020 at 01:50:09PM +0300, Andy Shevchenko wrote:
> On Fri, May 29, 2020 at 01:41:19PM +0300, Serge Semin wrote:
> > On Fri, May 29, 2020 at 01:29:02PM +0300, Andy Shevchenko wrote:
> > > On Fri, May 29, 2020 at 01:25:15PM +0300, Andy Shevchenko wrote:
> > > > On Fri, May 29, 2020 at
On Fri, May 29, 2020 at 01:41:19PM +0300, Serge Semin wrote:
> On Fri, May 29, 2020 at 01:29:02PM +0300, Andy Shevchenko wrote:
> > On Fri, May 29, 2020 at 01:25:15PM +0300, Andy Shevchenko wrote:
> > > On Fri, May 29, 2020 at 01:23:59AM +0300, Serge Semin wrote:
...
> > > > /* DMA capabi
On Fri, May 29, 2020 at 01:29:02PM +0300, Andy Shevchenko wrote:
> On Fri, May 29, 2020 at 01:25:15PM +0300, Andy Shevchenko wrote:
> > On Fri, May 29, 2020 at 01:23:59AM +0300, Serge Semin wrote:
> > > According to the DW APB DMAC data book the minimum burst transaction
> > > length is 1 and it's
On Fri, May 29, 2020 at 01:25:15PM +0300, Andy Shevchenko wrote:
> On Fri, May 29, 2020 at 01:23:59AM +0300, Serge Semin wrote:
> > According to the DW APB DMAC data book the minimum burst transaction
> > length is 1 and it's true for any version of the controller since
> > isn't parametrised in th
On Fri, May 29, 2020 at 01:23:59AM +0300, Serge Semin wrote:
> According to the DW APB DMAC data book the minimum burst transaction
> length is 1 and it's true for any version of the controller since
> isn't parametrised in the coreAssembler so can't be changed at the
> IP-core synthesis stage. Let
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