On 03-09-2024 20:02, Mathieu Poirier wrote:
On Tue, 3 Sept 2024 at 04:15, Beleswar Prasad Padhi wrote:
Hi Mathieu,
On 20-08-2024 16:20, Beleswar Padhi wrote:
From: Udit Kumar
Few times, core1 was scheduled to boot first before core0, which leads
to error:
'k3_r5_rproc_start: can not star
On Tue, 3 Sept 2024 at 04:15, Beleswar Prasad Padhi wrote:
>
> Hi Mathieu,
>
> On 20-08-2024 16:20, Beleswar Padhi wrote:
> > From: Udit Kumar
> >
> > Few times, core1 was scheduled to boot first before core0, which leads
> > to error:
> >
> > 'k3_r5_rproc_start: can not start core 1 before core
Hi Mathieu,
On 20-08-2024 16:20, Beleswar Padhi wrote:
From: Udit Kumar
Few times, core1 was scheduled to boot first before core0, which leads
to error:
'k3_r5_rproc_start: can not start core 1 before core 0'.
This was happening due to some scheduling between prepare and start
callback. The
From: Udit Kumar
Few times, core1 was scheduled to boot first before core0, which leads
to error:
'k3_r5_rproc_start: can not start core 1 before core 0'.
This was happening due to some scheduling between prepare and start
callback. The probe function waits for event, which is getting
triggered
On Fri, Aug 09, 2024 at 11:31:32AM +0530, Beleswar Padhi wrote:
> From: Udit Kumar
>
> Few times, core1 was scheduled to boot first before core0, which leads
> to error:
>
> 'k3_r5_rproc_start: can not start core 1 before core 0'.
>
> This was happening due to some scheduling between prepare an
From: Udit Kumar
Few times, core1 was scheduled to boot first before core0, which leads
to error:
'k3_r5_rproc_start: can not start core 1 before core 0'.
This was happening due to some scheduling between prepare and start
callback. The probe function waits for event, which is getting
triggered
EG("uid_map",S_IRUGO|S_IWUSR, proc_uid_map_operations),
REG("gid_map",S_IRUGO|S_IWUSR, proc_gid_map_operations),
diff --git a/kernel/delayacct.c b/kernel/delayacct.c
index ec580cb..87d091a 100644
--- a/kernel/delayacct.c
+++ b/kernel/delayacct.c
@@ -14,6 +14
From: Ryan Lee
[ Upstream commit 3a27875e91fb9c29de436199d20b33f9413aea77 ]
Amp requires 10 ~ 30ms for the power ON and OFF.
Added 30ms delay for stability.
Signed-off-by: Ryan Lee
Link:
https://lore.kernel.org/r/20210325033555.29377-2-ryans@maximintegrated.com
Signed-off-by: Mark Brown
From: Ryan Lee
[ Upstream commit 3a27875e91fb9c29de436199d20b33f9413aea77 ]
Amp requires 10 ~ 30ms for the power ON and OFF.
Added 30ms delay for stability.
Signed-off-by: Ryan Lee
Link:
https://lore.kernel.org/r/20210325033555.29377-2-ryans@maximintegrated.com
Signed-off-by: Mark Brown
From: Ryan Lee
[ Upstream commit 3a27875e91fb9c29de436199d20b33f9413aea77 ]
Amp requires 10 ~ 30ms for the power ON and OFF.
Added 30ms delay for stability.
Signed-off-by: Ryan Lee
Link:
https://lore.kernel.org/r/20210325033555.29377-2-ryans@maximintegrated.com
Signed-off-by: Mark Brown
From: Stefan Raspl
[ Upstream commit 75f94ecbd0dfd2ac4e671f165f5ae864b7301422 ]
If this service is enabled and the system rebooted, Systemd's initial
attempt to start this unit file may fail in case the kvm module is not
loaded. Since we did not specify a delay for the retries, Systemd
res
From: Stefan Raspl
[ Upstream commit 75f94ecbd0dfd2ac4e671f165f5ae864b7301422 ]
If this service is enabled and the system rebooted, Systemd's initial
attempt to start this unit file may fail in case the kvm module is not
loaded. Since we did not specify a delay for the retries, Systemd
res
; + u32 value;
> +
> + gl9750_wt_on(host);
> +
> + value = sdhci_readl(host, SDHCI_GLI_9750_CFG2);
> + value &= ~SDHCI_GLI_9750_CFG2_L1DLY;
> + /* set ASPM L1 entry delay to 7.9us */
> + value |= FIELD_PREP(SDHCI_GLI_9750_CFG2_L1DLY,
> +
On 4/9/21 7:56 PM, Radhey Shyam Pandey wrote:
Program IRQDelay for AXI DMA. The interrupt timeout mechanism causes
the DMA engine to generate an interrupt after the delay time period
has expired. It enables dmaengine to respond in real-time even though
interrupt coalescing is configured. It also
;
+
+ gl9750_wt_on(host);
+
+ value = sdhci_readl(host, SDHCI_GLI_9750_CFG2);
+ value &= ~SDHCI_GLI_9750_CFG2_L1DLY;
+ /* set ASPM L1 entry delay to 7.9us */
+ value |= FIELD_PREP(SDHCI_GLI_9750_CFG2_L1DLY,
+ GLI_9750_CFG2_L1DLY_V
Hi brookxu,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on linus/master]
[also build test ERROR on v5.12-rc7 next-20210413]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
Hi brookxu,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on linus/master]
[also build test WARNING on v5.12-rc7 next-20210412]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as docume
id_map",S_IRUGO|S_IWUSR, proc_gid_map_operations),
diff --git a/kernel/delayacct.c b/kernel/delayacct.c
index ec580cb..990af3b 100644
--- a/kernel/delayacct.c
+++ b/kernel/delayacct.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
int delayacct_on __read_mostly = 1;
On Fri, 09 Apr 2021 23:26:00 +0530, Radhey Shyam Pandey wrote:
> Add an optional AXI DMA property 'xlnx,irq-delay'. It specifies interrupt
> timeout value and causes the DMA engine to generate an interrupt after the
> delay time period has expired. Timer begins counting at
From: Ryan Lee
[ Upstream commit 3a27875e91fb9c29de436199d20b33f9413aea77 ]
Amp requires 10 ~ 30ms for the power ON and OFF.
Added 30ms delay for stability.
Signed-off-by: Ryan Lee
Link:
https://lore.kernel.org/r/20210325033555.29377-2-ryans@maximintegrated.com
Signed-off-by: Mark Brown
From: Ryan Lee
[ Upstream commit 3a27875e91fb9c29de436199d20b33f9413aea77 ]
Amp requires 10 ~ 30ms for the power ON and OFF.
Added 30ms delay for stability.
Signed-off-by: Ryan Lee
Link:
https://lore.kernel.org/r/20210325033555.29377-2-ryans@maximintegrated.com
Signed-off-by: Mark Brown
From: Ryan Lee
[ Upstream commit 3a27875e91fb9c29de436199d20b33f9413aea77 ]
Amp requires 10 ~ 30ms for the power ON and OFF.
Added 30ms delay for stability.
Signed-off-by: Ryan Lee
Link:
https://lore.kernel.org/r/20210325033555.29377-2-ryans@maximintegrated.com
Signed-off-by: Mark Brown
The three-character drain delay was added by commit f1175daa5312 ("USB:
ti_usb_3410_5052: kill custom closing_wait") when removing the custom
closing-wait implementation, which used a fixed 20 ms poll period and
drain delay.
This was likely a bit too conservative as a one-character ti
The f81232 driver now waits for the transmit FIFO to drain during close
so there is no need to keep the time-based drain delay, which would add
up to two seconds on every close for low line speeds.
Fixes: 98405f81036d ("USB: serial: f81232: add tx_empty function")
Signed-off-by: Jo
Unlike the TUSB5052, the TUSB3410 has an LSR TEMT bit to tell if both
the transmitter data and shift registers are empty.
Make sure to check also the shift register on TUSB3410 when waiting for
the transmit buffer to drain during close and drop the time-based
one-char delay which is otherwise
Document that the device line-status register doesn't tell when the
transmitter shift register has emptied and that this is why the
one-character drain delay is needed.
Signed-off-by: Johan Hovold
---
drivers/usb/serial/io_ti.c | 4
1 file changed, 4 insertions(+)
diff --git a/driver
On Wed, 7 Apr 2021 at 11:35, Ben Chuang wrote:
>
> From: Ben Chuang
>
> For GL9763E, although there is the best performance at the maximum delay.
> Change the value to 20us in order to have better power consumption.
> This change may reduce the maximum performance by 10%.
>
Return the exactly delay time given by root hub descriptor,
this helps to reduce resume time etc.
Due to the root hub descriptor is usually provided by the host
controller driver, if there is compatibility for a root hub,
we can fix it easily without affect other root hub
Acked-by: Alan Stern
Program IRQDelay for AXI DMA. The interrupt timeout mechanism causes
the DMA engine to generate an interrupt after the delay time period
has expired. It enables dmaengine to respond in real-time even though
interrupt coalescing is configured. It also remove the placeholder
for delay interrupt and
Add an optional AXI DMA property 'xlnx,irq-delay'. It specifies interrupt
timeout value and causes the DMA engine to generate an interrupt after the
delay time period has expired. Timer begins counting at the end of a packet
and resets with receipt of a new packet or a timeout event occ
On Thu, Apr 08, 2021 at 07:05:27PM +, Raphael Norwitz wrote:
> Like the Intel DC P3700 NVMe, the Intel P4510 NVMe exhibits a timeout
> failure when the driver tries to interact with the device to soon after
> an FLR. The same reset quirk the P3700 uses also resolves the failure
> for the P4510,
On Fri, Apr 09, 2021 at 10:39:07AM +0800, Chunfeng Yun wrote:
> Return the exactly delay time given by root hub descriptor,
> this helps to reduce resume time etc.
>
> Due to the root hub descriptor is usually provided by the host
> controller driver, if there is compatibility
ce/pcie-cadence-ep.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c
@@ -552,6 +552,23 @@ static const struct pci_epc_ops cdns_pcie_epc_ops = {
.get_features = cdns_pcie_ep_get_features,
};
+static void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie_ep *ep)
+{
+
Return the exactly delay time given by root hub descriptor,
this helps to reduce resume time etc.
Due to the root hub descriptor is usually provided by the host
controller driver, if there is compatibility for a root hub,
we can fix it easily without affect other root hub
Signed-off-by: Chunfeng
Like the Intel DC P3700 NVMe, the Intel P4510 NVMe exhibits a timeout
failure when the driver tries to interact with the device to soon after
an FLR. The same reset quirk the P3700 uses also resolves the failure
for the P4510, so this change introduces the same reset quirk for the
P4510.
Reviewed-
From: Ben Chuang
For GL9763E, although there is the best performance at the maximum delay.
Change the value to 20us in order to have better power consumption.
This change may reduce the maximum performance by 10%.
Signed-off-by: Ben Chuang
---
drivers/mmc/host/sdhci-pci-gli.c | 6 +++---
1
From: Ben Chuang
Although there is the best performance at the maximum delay.
Change the value to 20us in order to have better power consumption.
This change may reduce the maximum performance by 10%.
Signed-off-by: Ben Chuang
---
drivers/mmc/host/sdhci-pci-gli.c | 6 +++---
1 file changed, 3
From: Liam Beguin
The digital delay allows outputs to be delayed from 8 to 1023 VCO
cycles. The delay step can be as small as half the period of the clock
distribution path. For example, a 3.2-GHz VCO frequency results in
156.25-ps steps. The digital delay value takes effect on the clock
output
xit_reason.
> Speaking from experience, debugging those types of issues is beyond painful.
>
> It also means CR3 is double loaded in the from_vmentry case.
>
> And it will cause KVM to incorrectly return NVMX_VMENTRY_KVM_INTERNAL_ERROR
> if a consistency check fails when nes
Gentle Ping.
Are there any comments about these two patches?
Thank you,
On Tue, 9 Mar 2021 09:37:15 +0900
Kunihiko Hayashi wrote:
> After applying the commit bbc4d71d6354
> ("net: phy: realtek: fix rtl8211e rx/tx delay config"), the configuration
> register for TXDLY and RXD
From: Stefan Raspl
[ Upstream commit 75f94ecbd0dfd2ac4e671f165f5ae864b7301422 ]
If this service is enabled and the system rebooted, Systemd's initial
attempt to start this unit file may fail in case the kvm module is not
loaded. Since we did not specify a delay for the retries, Systemd
res
From: Stefan Raspl
[ Upstream commit 75f94ecbd0dfd2ac4e671f165f5ae864b7301422 ]
If this service is enabled and the system rebooted, Systemd's initial
attempt to start this unit file may fail in case the kvm module is not
loaded. Since we did not specify a delay for the retries, Systemd
res
Use generic regamp ramp-delay helper function instead of implementing own.
Signed-off-by: Matti Vaittinen
Acked-by: Mark Brown
---
No changes since v4
drivers/regulator/bd71828-regulator.c | 51 ---
drivers/regulator/bd718x7-regulator.c | 60 ---
2
On Fri, 2021-04-02 at 20:02 +0100, Mark Brown wrote:
> On Mon, Mar 29, 2021 at 04:00:13PM +0300, Matti Vaittinen wrote:
> > Use generic regamp ramp-delay helper function instead of
> > implementing own.
>
> This is patching something which was just added in the previous
>
On Mon, Mar 29, 2021 at 04:00:13PM +0300, Matti Vaittinen wrote:
> Use generic regamp ramp-delay helper function instead of implementing own.
This is patching something which was just added in the previous patch...
Acked-by: Mark Brown
signature.asc
Description: PGP signature
On Mon, Mar 29, 2021 at 03:59:28PM +0300, Matti Vaittinen wrote:
> Use generic regamp ramp-delay helper function instead of implementing own.
>
Acked-by: Mark Brown
signature.asc
Description: PGP signature
On Thu, Apr 01, 2021, Maxim Levitsky wrote:
> Similar to the rest of guest page accesses after migration,
> this should be delayed to KVM_REQ_GET_NESTED_STATE_PAGES
> request.
FWIW, I still object to this approach, and this patch has a plethora of issues.
I'm not against deferring various state l
On 01/04/21 16:18, Maxim Levitsky wrote:
Similar to the rest of guest page accesses after migration,
this should be delayed to KVM_REQ_GET_NESTED_STATE_PAGES
request.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/vmx/nested.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions
Similar to the rest of guest page accesses after migration,
this should be delayed to KVM_REQ_GET_NESTED_STATE_PAGES
request.
Signed-off-by: Maxim Levitsky
---
arch/x86/kvm/vmx/nested.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/arch/x86/kvm/vmx/nested.c b
id_map",S_IRUGO|S_IWUSR, proc_gid_map_operations),
diff --git a/kernel/delayacct.c b/kernel/delayacct.c
index ec580cb..990af3b 100644
--- a/kernel/delayacct.c
+++ b/kernel/delayacct.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
int delayacct_on __read_mostly = 1;
The Torrent spec specifies delay of 660.5us after phy_reset is
asserted by the controller. To be on the safe side provide a delay
of 5ms to 10ms in ->phy_on() callback where the SERDES is already
configured in bootloader.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cade
Use generic regamp ramp-delay helper function instead of implementing own.
Signed-off-by: Matti Vaittinen
---
Changes since v4:
- new patch
drivers/regulator/bd71815-regulator.c | 37 +--
1 file changed, 6 insertions(+), 31 deletions(-)
diff --git a/drivers/regulator
Quite a few regulator ICs do support setting ramp-delay by writing a value
matching the delay to a ramp-delay register.
Provide a simple helper for table-based delay setting.
Signed-off-by: Matti Vaittinen
---
Changes since v4:
- new patch
drivers/regulator/helpers.c | 65
Use generic regamp ramp-delay helper function instead of implementing own.
Signed-off-by: Matti Vaittinen
---
Changes since v4:
- new patch
drivers/regulator/bd71828-regulator.c | 51 ---
drivers/regulator/bd718x7-regulator.c | 60 ---
2 files
From: Florian Fainelli
[ Upstream commit 7a1468ba0e02eee24ae1353e8933793a27198e20 ]
Per the datasheet, when we clear the power down bit, the PHY remains in
an internal reset state for 40us and then resume normal operation.
Account for that delay to avoid any issues in the future if
From: Florian Fainelli
[ Upstream commit 7a1468ba0e02eee24ae1353e8933793a27198e20 ]
Per the datasheet, when we clear the power down bit, the PHY remains in
an internal reset state for 40us and then resume normal operation.
Account for that delay to avoid any issues in the future if
ltage regulator device tree nodes
> and corresponding pinmux details, to power cycle and voltage switch cards.
> Set respective tags in sdhci0 and remove no-1-8-v tag from sdhci1
> device tree nodes.
>
> Also update the delay values for various speed modes supported, based on
> the rev
and voltage switch cards.
Set respective tags in sdhci0 and remove no-1-8-v tag from sdhci1
device tree nodes.
Also update the delay values for various speed modes supported, based on
the revised january 2021 J7200 datasheet[2].
[1] - section 12.3.6.1.1 MMCSD Features, in
https://www.ti.com
UHS-I speed modes in MMCSD1 subsystem [1].
>>
>> Add support for UHS-I modes by adding voltage regulator device tree nodes
>> and corresponding pinmux details, to power cycle and voltage switch cards.
>> Set respective tags in sdhci0 and remove no-1-8-v tag from sdhci1
>&
adding voltage regulator device tree nodes
> and corresponding pinmux details, to power cycle and voltage switch cards.
> Set respective tags in sdhci0 and remove no-1-8-v tag from sdhci1
> device tree nodes.
>
> Also update the delay values for various speed modes supported, based on
&g
Amp requires 10 ~ 30ms for the power ON and OFF.
Added 30ms delay for stability.
Signed-off-by: Ryan Lee
---
sound/soc/codecs/max98373.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/sound/soc/codecs/max98373.c b/sound/soc/codecs/max98373.c
index 746c829312b8..1346a98ce8a1 100644
--- a
From: Arnd Bergmann
> Sent: 23 March 2021 13:20
> Passing an 8-bit constant into delay() triggers a warning when building
> with 'make W=1' using clang:
>
> drivers/clk/actions/owl-pll.c:182:2: error: result of comparison of constant
> 2000 with expression of
> typ
and voltage switch cards.
Set respective tags in sdhci0 and remove no-1-8-v tag from sdhci1
device tree nodes.
Also update the delay values for various speed modes supported, based on
the revised january 2021 J7200 datasheet[2].
[1] - section 12.3.6.1.1 MMCSD Features, in
https://www.ti.com
On Tue, Mar 23, 2021 at 02:20:23PM +0100, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> Passing an 8-bit constant into delay() triggers a warning when building
> with 'make W=1' using clang:
>
> drivers/clk/actions/owl-pll.c:182:2: error: result of compari
From: Arnd Bergmann
Passing an 8-bit constant into delay() triggers a warning when building
with 'make W=1' using clang:
drivers/clk/actions/owl-pll.c:182:2: error: result of comparison of constant
2000 with expression of type 'u8' (aka 'unsigned char') is always
device tree nodes
>>>> and corresponding pinmux details, to power cycle and voltage switch cards.
>>>> Set respective tags in sdhci0 and remove no-1-8-v tag from sdhci1
>>>> device tree nodes.
>>>>
>>>> Also update the delay values for vari
; Set respective tags in sdhci0 and remove no-1-8-v tag from sdhci1
>>> device tree nodes.
>>>
>>> Also update the delay values for various speed modes supported, based on
>>> the revised january 2021 J7200 datasheet[2].
>>>
>>> [1] - sectio
system [1].
>>
>> Add support for UHS-I modes by adding voltage regulator device tree nodes
>> and corresponding pinmux details, to power cycle and voltage switch cards.
>> Set respective tags in sdhci0 and remove no-1-8-v tag from sdhci1
>> device tree nodes.
>>
tor device tree nodes
> and corresponding pinmux details, to power cycle and voltage switch cards.
> Set respective tags in sdhci0 and remove no-1-8-v tag from sdhci1
> device tree nodes.
>
> Also update the delay values for various speed modes supported, based on
> the revis
system [1].
>>
>> Add support for UHS-I modes by adding voltage regulator device tree nodes
>> and corresponding pinmux details, to power cycle and voltage switch cards.
>> Set respective tags in sdhci0 and remove no-1-8-v tag from sdhci1
>> device tree nodes.
>>
and voltage switch cards.
Set respective tags in sdhci0 and remove no-1-8-v tag from sdhci1
device tree nodes.
Also update the delay values for various speed modes supported, based on
the revised january 2021 J7200 datasheet[2].
[1] - section 12.3.6.1.1 MMCSD Features, in
https://www.ti.com
tor device tree nodes
> and corresponding pinmux details, to power cycle and voltage switch cards.
> Set respective tags in sdhci0 and remove no-1-8-v tag from sdhci1
> device tree nodes.
>
> Also update the delay values for various speed modes supported, based on
> the revis
On Thu, Mar 18, 2021 at 08:39:13PM +, Sargun Dhillon wrote:
> On Thu, Mar 18, 2021 at 03:54:54PM +0100, Christian Brauner wrote:
> > Sorry, I just found that mail.
> >
> > On Mon, Mar 01, 2021 at 03:44:06PM -0800, Kees Cook wrote:
> > > On Mon, Mar 01, 2021 at 02:21:56PM +0100, Christian Braun
On Thu, Mar 18, 2021 at 9:39 PM Sargun Dhillon wrote:
> I believe that the OCI spec[2] is going to run into this class of problem
> unless
> we introduce an out of band signaling mechanism. I think a valid way to handle
> this is do a send() of the fd number (literal), and wait for the other side
adding voltage regulator device tree nodes
> and corresponding pinmux details, to power cycle and voltage switch cards.
> Set respective tags in sdhci0 and remove no-1-8-v tag from sdhci1
> device tree nodes.
>
> Also update the delay values for various speed modes supported, based on
&g
d modes in MMCSD1 subsystem [1].
>>
>> Add support for UHS-I modes by adding voltage regulator device tree nodes
>> and corresponding pinmux details, to power cycle and voltage switch cards.
>> Set respective tags in sdhci0 and remove no-1-8-v tag from sdhci1
>>
and voltage switch cards.
Set respective tags in sdhci0 and remove no-1-8-v tag from sdhci1
device tree nodes.
Also update the delay values for various speed modes supported, based on
the revised january 2021 J7200 datasheet[2].
[1] - section 12.3.6.1.1 MMCSD Features, in
https://www.ti.com
On Thu, Mar 18, 2021 at 03:54:54PM +0100, Christian Brauner wrote:
> Sorry, I just found that mail.
>
> On Mon, Mar 01, 2021 at 03:44:06PM -0800, Kees Cook wrote:
> > On Mon, Mar 01, 2021 at 02:21:56PM +0100, Christian Brauner wrote:
> > > On Mon, Mar 01, 2021 at 12:09:09PM +0100, Christian Braune
ltage regulator device tree nodes
> and corresponding pinmux details, to power cycle and voltage switch cards.
> Set respective tags in sdhci0 and remove no-1-8-v tag from sdhci1
> device tree nodes.
>
> Also update the delay values for various speed modes supported, based on
> t
Sorry, I just found that mail.
On Mon, Mar 01, 2021 at 03:44:06PM -0800, Kees Cook wrote:
> On Mon, Mar 01, 2021 at 02:21:56PM +0100, Christian Brauner wrote:
> > On Mon, Mar 01, 2021 at 12:09:09PM +0100, Christian Brauner wrote:
> > > On Sat, Feb 20, 2021 at 01:31:57AM -0800, Sargun Dhillon wrote
From: Greg Kroah-Hartman
From: John Ernberg
commit fc7c5c208eb7bc2df3a9f4234f14eca250001cb6 upstream.
The microphone in the Plantronics C320-M headset will randomly
fail to initialize properly, at least when using Microsoft Teams.
Introducing a 20ms delay on the control messages appears to
From: Greg Kroah-Hartman
From: John Ernberg
commit fc7c5c208eb7bc2df3a9f4234f14eca250001cb6 upstream.
The microphone in the Plantronics C320-M headset will randomly
fail to initialize properly, at least when using Microsoft Teams.
Introducing a 20ms delay on the control messages appears to
From: Greg Kroah-Hartman
From: John Ernberg
commit fc7c5c208eb7bc2df3a9f4234f14eca250001cb6 upstream.
The microphone in the Plantronics C320-M headset will randomly
fail to initialize properly, at least when using Microsoft Teams.
Introducing a 20ms delay on the control messages appears to
From: Greg Kroah-Hartman
From: John Ernberg
commit fc7c5c208eb7bc2df3a9f4234f14eca250001cb6 upstream.
The microphone in the Plantronics C320-M headset will randomly
fail to initialize properly, at least when using Microsoft Teams.
Introducing a 20ms delay on the control messages appears to
controller/cadence/pcie-cadence-host.c
> @@ -461,6 +461,20 @@ static int cdns_pcie_host_init(struct device *dev,
> return cdns_pcie_host_init_address_translation(rc);
> }
>
> +static void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie_rc *rc)
> +{
> + st
raham I ;
> Milind Parab ; Swapnil Kashinath Jakhade
> ; Parshuram Raju Thombare
>
> Subject: Re: [PATCH 1/2] dt-bindings:pci: Set LTSSM Detect.Quiet state delay.
>
> EXTERNAL MAIL
>
>
> On Tue, Mar 9, 2021 at 12:31 AM Nadeem Athani
> wrote:
> >
> > The param
Hello:
This patch was applied to netdev/net.git (refs/heads/master):
On Wed, 10 Mar 2021 20:53:42 -0800 you wrote:
> Per the datasheet, when we clear the power down bit, the PHY remains in
> an internal reset state for 40us and then resume normal operation.
> Account for that delay to
t; in MMCSD0 subsystem and add a sdhci mask to disable SDR104 speed mode.
>
> Also, update the itap delay values for all the MMCSD subsystems according
> the latest J721e data sheet[2]
>
> [...]
Hi Aswath Govindraju,
I have applied the following to branch ti-k3-dts-next on [1].
Thank
Per the datasheet, when we clear the power down bit, the PHY remains in
an internal reset state for 40us and then resume normal operation.
Account for that delay to avoid any issues in the future if
genphy_resume() changes.
Fixes: fe26821fa614 ("net: phy: broadcom: Wire suspend/resum
and voltage switch cards.
Set respective tags in sdhci0 and remove no-1-8-v tag from sdhci1
device tree nodes.
Also update the delay values for various speed modes supported, based on
the latest J7200 datasheet[2]
[1] - section 12.3.6.1.1 MMCSD Features, in
https://www.ti.com/lit/ug
On Tue, 09 Mar 2021 08:31:41 +0100, Nadeem Athani wrote:
> The parameter detect-quiet-min-delay can be used to program the minimum
> time that LTSSM waits on entering Detect.Quiet state.
> 00 : 0us minimum wait time in Detect.Quiet state.
> 01 : 100us minimum wait time in Detect.Quiet
On Tue, Mar 9, 2021 at 12:31 AM Nadeem Athani wrote:
>
> The parameter detect-quiet-min-delay can be used to program the minimum
> time that LTSSM waits on entering Detect.Quiet state.
> 00 : 0us minimum wait time in Detect.Quiet state.
> 01 : 100us minimum wait time in Detect.Qu
ubsystem and add a sdhci mask to disable SDR104 speed mode.
>
> Also, update the itap delay values for all the MMCSD subsystems according
> the latest J721e data sheet[2]
>
> [1] - https://www.ti.com/lit/er/sprz455/sprz455.pdf
> [2] - https://www.ti.com/lit/ds/symlink/tda4v
On Mon, Mar 08, 2021 at 04:54:58PM +0200, Alexandru Ardelean wrote:
> The intent is the removal of the 'delay_usecs' field from the
> spi_transfer struct, as there is a 'delay' field that does the same
> thing.
>
> The spi_delay_to_ns() can be used to get the
ch-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -82,12 +82,6 @@ static int ar8031_phy_fixup(struct phy_device *dev)
val |= 0x18;
phy_write(dev, 0xe, val);
- /* introduce tx clock delay */
- phy_write(dev, 0x1d, 0x5);
- val = phy_read(dev, 0x1e);
- val
Hi,
On Tue, Mar 09, 2021 at 09:58:09AM +0530, Viresh Kumar wrote:
> On 08-03-21, 16:54, Alexandru Ardelean wrote:
> > The intent is the removal of the 'delay_usecs' field from the
> > spi_transfer struct, as there is a 'delay' field that does the same
> >
The parameter detect-quiet-min-delay can be used to program the minimum
time that LTSSM waits on entering Detect.Quiet state.
00 : 0us minimum wait time in Detect.Quiet state.
01 : 100us minimum wait time in Detect.Quiet state.
10 : 1000us minimum wait time in Detect.Quiet state.
11 : 2000us
);
}
+static void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie_rc *rc)
+{
+ struct cdns_pcie *pcie = &rc->pcie;
+ u32 delay = rc->detect_quiet_min_delay;
+ u32 ltssm_control_cap;
+
+ ltssm_control_cap = cdns_pcie_readl(pcie, CDNS_PCIE_LTSSM_C
This patch includes a set of two patches.
First patch for adding a new property detect-quiet-min-delay in yaml file.
Second patch programs the delay value in host pcie driver.
The parameter detect-quiet-min-delay can be used to program the minimum
time that LTSSM waits on entering Detect.Quiet
to support this; OTOH
> the kernel does contain lots of workarounds for quirks and hardware
> bugs.
>
>
>
>
> Rasmus Villemoes (3):
> clk: add devm_clk_prepare_enable() helper
> dt-bindings: watchdog: add optional "delay" clock to gpio-wdt bindi
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