On Fri, 2019-06-14 at 17:46 +0800, Ulf Hansson wrote:
> On Fri, 14 Jun 2019 at 07:26, Jjian Zhou wrote:
> >
> > From: jjian zhou
> >
> > SDIO IRQ is triggered by low level. It need disable SDIO IRQ
> > detected function. Otherwise the interrupt register can't be cleared.
> > It will process the
On Mon, 17 Jun 2019 at 02:09, Alistair Popple wrote:
>
> On Monday, 21 January 2019 11:15:58 AM AEST Eddie James wrote:
> > SBE fifo operations should be allowed while the SBE is in any of the
> > "IPL" states. Operations should succeed in this state.
> >
> > Signed-off-by: Eddie James
>
> This
Chang,
On Mon, 17 Jun 2019, Bae, Chang Seok wrote:
Can you please use proper quoting style?
> On Jun 16, 2019, at 15:00, Thomas Gleixner
> mailto:t...@linutronix.de>> wrote:
> >
> > > -GCC version 4.6.4 and newer provide instrinsics for the FSGSBASE
> > > +GCC version 6 and newer provide
Greetings
My name is Mr. Emmanuel Akwasi from Odikro Royal Family Upper East
Region, Ghana. We are a group of local gold Miners and end sellers we
are looking for a direct buyer or an agent who will help us look for
buyer on Commission basis.
The Purity of our gold is 93% and 22Carats Plus
Remove BUG, BUG_ON as it makes system usable:
- Remove redundant BUG_ON calls or replace with WARN_ON_ONCE
as needed.
- Remove BUG() and mask Rx interrupt similar as Tx
for message fully sent case.
- Add caller error handling and WARN_ON_ONCE check for non-zero
rx_fifo_avail in
The target is to compare the performance difference (cycles
diff) for the same basic blocks in different data files.
The same basic block means same function, same start address
and same end address. This patch finds the same basic blocks
from different data files and link them together and
perf record -b ./div
perf record -b ./div
Following is the default perf diff output
# perf diff
# Event 'cycles'
#
# Baseline Delta Abs Shared Object Symbol
# .
#
49.03% +0.30% div [.]
Documentation the new computation selection 'cycles'.
Signed-off-by: Jin Yao
---
tools/perf/Documentation/perf-diff.txt | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/tools/perf/Documentation/perf-diff.txt
b/tools/perf/Documentation/perf-diff.txt
index
We will expand perf diff to support diff cycles of individual programs
blocks, so it requires all data files having branch stacks.
This patch checks HEADER_BRANCH_STACK in header, and only set the flag
has_br_stack when HEADER_BRANCH_STACK are set in all data files.
v2:
---
Move
The block_info contains the program basic block information, i.e,
contains the start address and the end address of this basic block and
how much cycles it takes. We need to compare, sort and even print out
the basic block by some orders, i.e. sort by cycles.
For this purpose, we add block_info
The hist__account_cycles() can account cycles per basic
block. The basic block information is saved in cycles_hist
structure.
This patch processes each symbol, get basic blocks from
cycles_hist and add the basic block entries to a new hists
(in 'struct block_hist'). Using a hists is because
we
perf diff currently can only diff symbols(functions). We should expand it
to diff cycles of individual programs blocks as reported by timed LBR.
This would allow to identify changes in specific code accurately.
We need a new structure to maintain the basic block information, such as,
In some cases small changes in hot loops can show big differences.
But it's difficult to identify these differences.
perf diff currently can only diff symbols (functions). We can also expand
it to diff cycles of individual programs blocks as reported by timed LBR.
This would allow to identify
Hi all,
After merging the clockevents tree, today's linux-next build (arm
multi_v7_defconfig) produced these warnings:
In file included from arch/arm/kernel/vdso.c:30:
arch/arm/include/asm/arch_timer.h: In function 'arch_timer_set_evtstrm_feature':
arch/arm/include/asm/arch_timer.h:131:1:
From: Alastair D'Silva
These functions don't exist, so remove the prototypes for them.
Signed-off-by: Alastair D'Silva
---
drivers/nvdimm/nd-core.h | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/nvdimm/nd-core.h b/drivers/nvdimm/nd-core.h
index 391e88de3a29..57d162dbefaa
On Mon, Jun 17, 2019 at 9:49 AM Yash Shah wrote:
>
> On FU540, the management IP block is tightly coupled with the Cadence
> MACB IP block. It manages many of the boundary signals from the MACB IP
> This patchset controls the tx_clk input signal to the MACB IP. It
> switches between the local TX
From: Alastair D'Silva
If an OpenCAPI context is to be used directly by a kernel driver, there
may not be a suitable mm to use.
The patch makes the mm parameter to ocxl_context_attach optional.
Signed-off-by: Alastair D'Silva
---
drivers/misc/ocxl/context.c | 9 ++---
From: Alastair D'Silva
If a memory section comes in where the physical address is greater than
that which is managed by the kernel, this function would not trigger the
bug and instead return a bogus section number.
This patch tracks whether the section was actually found, and triggers the
bug
From: Alastair D'Silva
When removing sufficiently large amounts of memory, we trigger RCU stall
detection. By periodically calling cond_resched(), we avoid bogus stall
warnings.
Signed-off-by: Alastair D'Silva
---
mm/memory_hotplug.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
From: Alastair D'Silva
This series addresses some minor issues found when developing a
persistent memory driver.
As well as cleanup code, it also exports try_online_node so that
it can be called from driver modules that provide access to additional
physical memory.
Alastair D'Silva (5):
mm:
From: Alastair D'Silva
If an external driver module supplies physical memory and needs to expose
the memory on a specific NUMA node, it needs to be able to call
try_online_node to allocate the data structures for the node.
The previous assertion that all callers want to online the node, and
From: Alastair D'Silva
By adding offset to memmap before passing it in to clear_hwpoisoned_pages,
is hides a potentially null memmap from the null check inside
clear_hwpoisoned_pages.
This patch passes the offset to clear_hwpoisoned_pages instead, allowing
memmap to successfully peform it's
From: Alastair D'Silva
Use the function written to do it instead.
Signed-off-by: Alastair D'Silva
---
mm/sparse.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/mm/sparse.c b/mm/sparse.c
index 66a99da9b11b..e2402937efe4 100644
--- a/mm/sparse.c
+++ b/mm/sparse.c
@@
Hi,
On 10/06/19 9:55 PM, Sergei Shtylyov wrote:
> Hello!
>
> On 06/09/2019 01:32 PM, Vignesh Raghavendra wrote:
>
>> Add binding documentation for TI's HyperBus memory controller present on
>> AM654 SoC.
>>
>> Signed-off-by: Vignesh Raghavendra
>> ---
>> v5:
>> Update binding example to show
On Thu, Jun 13, 2019 at 10:58 AM Song Liu wrote:
>
> This set makes uprobe aware of THPs.
>
> Currently, when uprobe is attached to text on THP, the page is split by
> FOLL_SPLIT. As a result, uprobe eliminates the performance benefit of THP.
>
> This set makes uprobe THP-aware. Instead of
On Thu 13 Jun 22:30 PDT 2019, Vinod Koul wrote:
> From: Prasad Sodagudi
>
> Add initial pinctrl driver to support pin configuration with
> pinctrl framework for SM8150
>
> Signed-off-by: Prasad Sodagudi
> Signed-off-by: Isaac J. Manjarres
I presume you did stuff to make it fit with my
The management IP block is tightly coupled with the Cadence MACB IP
block on the FU540, and manages many of the boundary signals from the
MACB IP. This patch only controls the tx_clk input signal to the MACB
IP. Future patches may add support for monitoring or controlling other
IP boundary
Add the compatibility string documentation for SiFive FU540-C
interface.
On the FU540, this driver also needs to read and write registers in a
management IP block that monitors or drives boundary signals for the
GEMGXL IP block that are not directly mapped to GEMGXL registers.
Therefore, add
On Thu 13 Jun 22:30 PDT 2019, Vinod Koul wrote:
> From: Prasad Sodagudi
>
> Add the binding for the TLMM pinctrl block found in the SM8150 platform.
>
> Signed-off-by: Prasad Sodagudi
> Signed-off-by: Isaac J. Manjarres
> Signed-off-by: Vinod Koul
> ---
>
On FU540, the management IP block is tightly coupled with the Cadence
MACB IP block. It manages many of the boundary signals from the MACB IP
This patchset controls the tx_clk input signal to the MACB IP. It
switches between the local TX clock (125MHz) and PHY TX clocks. This
is necessary to
On Mon, Jun 03, 2019 at 09:29:44PM +0800, Peter Xu wrote:
> get_target_base() in the timer code is not using the "base" parameter
> at all. My gut feeling is that instead of removing that extra
> parameter, what we really want to do is "return the old base if it
> does not suite for a new one".
On 6/14/2019 12:02 PM, Viresh Kumar wrote:
On 20-03-19, 15:19, Rajendra Nayak wrote:
For devices with performance state, we use dev_pm_opp_set_rate()
to set the appropriate clk rate and the performance state.
We do need a way to *remove* the performance state vote when
we idle the device and
On Fri, 2019-06-14 at 10:32 +0800, Walter Wu wrote:
> On Fri, 2019-06-14 at 01:46 +0800, Walter Wu wrote:
> > On Thu, 2019-06-13 at 15:27 +0300, Andrey Ryabinin wrote:
> > >
> > > On 6/13/19 11:13 AM, Walter Wu wrote:
> > > > This patch adds memory corruption identification at bug report for
> >
On Wed, Jun 12, 2019 at 12:36:47PM +0200, Vitaly Kuznetsov wrote:
> Maya Nakamura writes:
>
> > Introduce two new functions, hv_alloc_hyperv_page() and
> > hv_free_hyperv_page(), to allocate/deallocate memory with the size and
> > alignment that Hyper-V expects as a page. Although currently they
The supported formats are S16_LE and S24_LE now. However, S24_LE is
not supported when TDM is 0 and it is not in the right justified mode.
We should remove 24-bit format in that situation to avoid triggering
error.
Signed-off-by: Yu-Hsuan Hsu
---
The datasheet said that when TDM=0 and RJ=0,
On Mon, Jun 17, 2019 at 12:19:59PM +1000, Stephen Rothwell wrote:
> Hi Leon,
>
> Today's linux-next merge of the mlx5-next tree got a conflict in:
>
> include/linux/mlx5/eswitch.h
>
> between commit:
>
> 02f3afd97556 ("net/mlx5: E-Switch, Correct type to u16 for vport_num and
> int for
On 14-06-19, 10:57, Viresh Kumar wrote:
> Hmm, so this patch won't break anything and I am inclined to apply it again :)
>
> Does anyone see any other issues with it, which I might be missing ?
I have updated the commit log a bit more to clarify on things, please let me
know if it looks okay.
On Sun 16 Jun 17:18 PDT 2019, Brian Masney wrote:
> Hi Bjorn,
>
> On Sun, Jun 16, 2019 at 11:06:33AM -0700, Bjorn Andersson wrote:
> > > diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> > > b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> > > index 6f7f4114afcf..e0a9409c8a32 100644
> > > ---
On Sun, Jun 16, 2019 at 07:52:33PM +0200, Borislav Petkov wrote:
> On Sun, Jun 16, 2019 at 10:14:08AM -0700, Fenghua Yu wrote:
> > @@ -617,13 +617,20 @@ static void l3_mon_evt_init(struct rdt_resource *r)
> > list_add_tail(_local_event.list, >evt_list);
> > }
> >
> > -int
Hi all,
Today's linux-next merge of the imx-drm tree got a conflict in:
drivers/staging/media/imx/imx-ic-prpencvf.c
between commits:
6d01b7ff5233 ("media: staging/imx: Switch to sync registration for IPU
subdevs")
34ff38745b16 ("media: staging/imx: Pass device to alloc/free_dma_buf")
Hi Alan,
On Sun, Jun 16, 2019 at 10:11:13PM -0500, Alan Tull wrote:
> I'm moving on to a new position and stepping down as FPGA subsystem
> maintainer. Moritz has graciously agreed to take over the
> maintainership.
Thanks a lot for all the work you put into this, it was good fun working
with
On 6/16/2019 5:55 PM, Tao Xu wrote:
UMWAIT and TPAUSE instructions use IA32_UMWAIT_CONTROL at MSR index E1H
to determines the maximum time in TSC-quanta that the processor can reside
in either C0.1 or C0.2.
This patch emulates MSR IA32_UMWAIT_CONTROL in guest and differentiate
Hi, Yongqiang:
On Wed, 2019-06-05 at 19:43 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add support for mediatek SOC MT8183
> 1.ovl_2l share driver with ovl
> 2.rdma1 share drive with rdma0, but fifo size is different
> 3.add mt8183 mutex private data, and mmsys
On Sat, Jun 15, 2019 at 2:10 AM Stephen Boyd wrote:
>
> We want to allow the parent lookup to happen even if the index is some
> value less than 0. This may be the case if a clk provider only specifies
> the .name member to match a string in the "clock-names" DT property. We
> shouldn't require
On Sun, Jun 16, 2019 at 10:24:13PM +0200, Thomas Gleixner wrote:
> On Sun, 16 Jun 2019, Fenghua Yu wrote:
>
> > Although x86_cache_max_rmid and x86_cache_occ_scale are only read once
> > during resctrl initialization, they are always stored in cpuinfo_x86 for
> > each CPU during run time without
Hi all,
On Wed, 12 Jun 2019 11:46:15 +1000 Stephen Rothwell
wrote:
>
> Hi all,
>
> Today's linux-next merge of the drm-misc tree got a conflict in:
>
> drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
>
> between commit:
>
> c7c7192c56d2 ("drm/amd/display: add audio related regs")
>
>
Hi all,
Today's linux-next merge of the drm-intel tree got a conflict in:
drivers/gpu/drm/i915/i915_drv.h
between commit:
151f4e2bdc7a ("docs: power: convert docs to ReST and rename to *.rst")
from the pci tree and commit:
1bf676cc2dba ("drm/i915: move and rename i915_runtime_pm")
On 2019/06/13 23:15, Josef Bacik wrote:
> On Fri, Jun 07, 2019 at 10:10:18PM +0900, Naohiro Aota wrote:
>> It is possible to have bios stalled in the submit buffer due to some bug or
>> device problem. In such situation, btrfs stops working waiting for buffered
>> bios completions. To avoid such
Josef,
On 2019/06/13 23:15, Josef Bacik wrote:
> On Fri, Jun 07, 2019 at 10:10:17PM +0900, Naohiro Aota wrote:
>> Sequential allocation is not enough to maintain sequential delivery of
>> write IOs to the device. Various features (async compress, async checksum,
>> ...) of btrfs affect ordering
On Fri, 2019-06-14 at 13:56 +0200, Peter Zijlstra wrote:
> On Wed, May 08, 2019 at 05:44:09PM +0300, Kirill A. Shutemov wrote:
> > From: Kai Huang
> >
> > KVM needs those variables to get/set memory encryption mask.
> >
> > Signed-off-by: Kai Huang
> > Signed-off-by: Kirill A. Shutemov
> >
Hi Alex,
Today's linux-next merge of the amdgpu tree got a conflict in:
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
between commits:
192905989302 ("drm/amd/amdgpu: add RLC firmware to support raven1 refresh")
f3a5231c8f14 ("drm/amdgpu: return 0 by default in
amdgpu_pm_load_smu_firmware")
I'm moving on to a new position and stepping down as FPGA subsystem
maintainer. Moritz has graciously agreed to take over the
maintainership.
Signed-off-by: Alan Tull
---
MAINTAINERS | 1 -
1 file changed, 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 80e2bfa049d7..448730982545
On Sun, 16 Jun 2019 10:54:06 PDT (-0700), j...@sing.id.au wrote:
On 19-06-07 15:22:22, Palmer Dabbelt wrote:
The comment describes why in detail. This was found because QEMU never
gives up load reservations, the issue is unlikely to manifest on real
hardware.
Makes sense, however it
On 14-06-19, 10:14, Matthias Kaehlcke wrote:
> Hi Viresh,
>
> On Mon, Jun 10, 2019 at 04:21:36PM +0530, Viresh Kumar wrote:
> > This implements QoS requests to manage userspace configuration of min
> > and max frequency.
> >
> > Signed-off-by: Viresh Kumar
> > ---
> > drivers/cpufreq/cpufreq.c
On Sat, 15 Jun 2019, at 07:11, Vijay Khemka wrote:
> Hi Andrew,
> Any update on this patch or do I need any more rework.
No, no more reworks. I've pinged Joel, he'll pick it up.
Andrew
Hi, Yongqiang:
On Wed, 2019-06-05 at 19:43 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add clock property check before get it
In the binding document [1], clock is required property. In this patch,
you change it to optional property. I think you should change
On 14-06-19, 09:46, Matthias Kaehlcke wrote:
> Hi Viresh,
>
> On Mon, Jun 10, 2019 at 04:21:35PM +0530, Viresh Kumar wrote:
> > This registers the notifiers for min/max frequency constraints with the
> > PM QoS framework. The constraints are also taken into consideration in
> >
syzbot has found a reproducer for the following crash on:
HEAD commit:963172d9 Merge branch 'x86-urgent-for-linus' of git://git...
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=11422276a0
kernel config:
On Thu, Jun 13, 2019 at 11:22 AM Julien Desfossez
wrote:
>
> On 12-Jun-2019 05:03:08 PM, Subhra Mazumdar wrote:
> >
> > On 6/12/19 9:33 AM, Julien Desfossez wrote:
> > >After reading more traces and trying to understand why only untagged
> > >tasks are starving when there are cpu-intensive tasks
Add a Intel event file for perf.
Signed-off-by: Haiyan Song
---
tools/perf/pmu-events/arch/x86/icelake/cache.json | 552 +
.../arch/x86/icelake/floating-point.json | 102 +++
.../perf/pmu-events/arch/x86/icelake/frontend.json | 424 ++
David,
On 2019/06/13 22:45, David Sterba wrote:
> On Thu, Jun 13, 2019 at 04:59:23AM +, Naohiro Aota wrote:
>> On 2019/06/13 2:50, David Sterba wrote:
>>> On Fri, Jun 07, 2019 at 10:10:06PM +0900, Naohiro Aota wrote:
btrfs zoned block device support
This series adds zoned block
Christoph Hellwig 於 2019年6月14日 週五 下午8:22寫道：
>
> On Fri, Jun 14, 2019 at 07:35:29PM +0800, Greentime Hu wrote:
> > It looks good to me. I just verified in nds32 platform and it works fine.
> > Should I put it in my next-tree or you will pick it up in your tree? :)
>
> Either way works for me, let
Kernel warning while running kernel selftest bpf test_sockmap test case on
x86_64 and arm64.
The kernel warning log pops up continuously.
Linux version 5.1.10-rc2
Steps to reproduce:
Boot stable rc 5.1.10-rc2 kernel on x86_64 or arm64
cd selftests/bpf
./test_sockmap
[ 37.600406] WARNING: CPU:
> On Jun 16, 2019, at 11:42 AM, Dan Williams wrote:
>
> On Fri, Jun 14, 2019 at 1:43 PM Qian Cai wrote:
>>
>> On Fri, 2019-06-14 at 12:48 -0700, Dan Williams wrote:
>>> On Fri, Jun 14, 2019 at 12:40 PM Qian Cai wrote:
On Fri, 2019-06-14 at 11:57 -0700, Dan Williams wrote:
>
Hi Leon,
Today's linux-next merge of the mlx5-next tree got a conflict in:
include/linux/mlx5/eswitch.h
between commit:
02f3afd97556 ("net/mlx5: E-Switch, Correct type to u16 for vport_num and int
for vport_index")
from Linus' tree and commit:
82b11f071936 ("net/mlx5: Expose eswitch
This fixed the problem I was having trying to issue istep operations to the
SBE.
Tested-by: Alistair Popple
On Monday, 21 January 2019 11:15:58 AM AEST Eddie James wrote:
> SBE fifo operations should be allowed while the SBE is in any of the
> "IPL" states. Operations should succeed in this
From: Alastair D'Silva
Some buffers may only be partially filled with useful data, while the rest
is padded (typically with 0x00 or 0xff).
This patch introduces a flag to allow the supression of lines of repeated
bytes, which are replaced with '** Skipped %u bytes of value 0x%x **'
An inline
From: Alastair D'Silva
Similar to the previous patch, this patch separates groups by 2 spaces for
the hex fields, and 1 space for the ASCII field.
eg.
buf:: 454d414e 43415053 4e495f45 00584544 NAMESPAC E_INDEX.
buf:0010: 0002
From: Alastair D'Silva
The behaviour of hexdump groups is to print the data out as if
it was a native-endian number.
This patch tweaks the documentation to make this clear, and also
adds the HEXDUMP_RETAIN_BYTE_ORDER flag to allow groups of
multiple bytes to be printed without affecting the
From: Alastair D'Silva
This patch removes the hardcoded row limits and allows for
other lengths. These lengths must still be a multiple of
groupsize.
This allows structs that are not 16/32 bytes to display on
a single line.
This patch also expands the self-tests to test row sizes
up to 64
From: Alastair D'Silva
The overflow tests did not account for the situation where no
overflow occurs and len < rowsize.
This patch renames the cryptic variables and accounts for the
above case.
The selftests now pass.
Signed-off-by: Alastair D'Silva
---
lib/test_hexdump.c | 47
From: Alastair D'Silva
With the wider display format, it can become hard to identify how many
bytes into the line you are looking at.
The patch adds new flags to hex_dump_to_buffer() and print_hex_dump() to
print vertical lines to separate every N groups of bytes.
eg.
buf:: 454d414e
From: Alastair D'Silva
Apologies for the large CC list, it's a heads up for those responsible
for subsystems where a prototype change in generic code causes a change
in those subsystems.
This series enhances hexdump.
These improve the readability of the dumped data in certain situations
(eg.
From: Alastair D'Silva
In order to support additional features in hex_dump_to_buffer, replace
the ascii bool parameter with flags.
Signed-off-by: Alastair D'Silva
---
drivers/gpu/drm/i915/intel_engine_cs.c| 2 +-
drivers/isdn/hardware/mISDN/mISDNisar.c | 6 --
Hi, Yongqiang:
On Wed, 2019-06-05 at 19:42 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add function to background color input select for ovl/ovl_2l
> direct link
> for ovl/ovl_2l direct link usecase, we need set background color
> input select for these
Hi all,
Today's linux-next merge of the net-next tree got a conflict in:
net/wireless/nl80211.c
between commit:
180aa422ef27 ("nl80211: fill all policy .type entries")
from the net tree and commit:
1a28ed213696 ("nl80211: fill all policy .type entries")
from the net-next tree.
I
On 06/14/19 at 09:15pm, Lendacky, Thomas wrote:
> The memory occupied by the kernel is reserved using memblock_reserve()
> in setup_arch(). Currently, the area is from symbols _text to __bss_stop.
> Everything after __bss_stop must be specifically reserved otherwise it
> is discarded. This is not
Hi all,
Today's linux-next merge of the net-next tree got a conflict in:
net/vmw_vsock/hyperv_transport.c
between commit:
d424a2afd7da ("hv_sock: Suppress bogus "may be used uninitialized" warnings")
from the net tree and commit:
ac383f58f3c9 ("hv_sock: perf: Allow the socket buffer
> -Original Message-
> From: Rob Herring
> Sent: 2019年6月14日 4:08
> To: Wen He
> Cc: linux-kernel@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> devicet...@vger.kernel.org; shawn...@kernel.org; Leo Li
>
> Subject: [EXT] Re: [v1 1/4] dt-bindings: display: Add DT bindings for
Hi all,
Today's linux-next merge of the net-next tree got a conflict in:
net/mac80211/cfg.c
between commit:
28c61a66abd6 ("treewide: Replace GPLv2 boilerplate/reference with SPDX - rule
432")
from Linus' tree and commit:
bd718fc11d5b ("mac80211: use STA info in
> On Jun 16, 2019, at 9:32 PM, Anshuman Khandual
> wrote:
>
> Hello Qian,
>
> On 06/14/2019 05:45 PM, Qian Cai wrote:
>> On Fri, 2019-06-14 at 11:20 +0100, Will Deacon wrote:
>>> Hi Qian,
>>>
>>> On Thu, Jun 13, 2019 at 05:34:01PM -0400, Qian Cai wrote:
LTP hugemmap05 test case [1]
Hi all,
Today's linux-next merge of the net-next tree got conflicts in:
arch/sh/configs/se7712_defconfig
arch/sh/configs/se7721_defconfig
arch/sh/configs/titan_defconfig
between commit:
7c04efc8d2ef ("sh: configs: Remove useless UEVENT_HELPER_PATH")
from the sh tree and commit:
Same as Intel, Zhaoxin MP CPUs support C3 share cache and on all
recent Zhaoxin platforms ARB_DISABLE is a nop. So set related
flags correctly in the same way as Intel does.
Signed-off-by: Tony W Wang-oc
---
arch/x86/kernel/acpi/cstate.c | 15 +++
1 file changed, 15 insertions(+)
Zhaoxin CPUs have NONSTOP TSC feature, so enable the ACPI
driver support for it.
Signed-off-by: Tony W Wang-oc
---
drivers/acpi/acpi_pad.c | 1 +
drivers/acpi/processor_idle.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/acpi/acpi_pad.c b/drivers/acpi/acpi_pad.c
index
Hello Qian,
On 06/14/2019 05:45 PM, Qian Cai wrote:
> On Fri, 2019-06-14 at 11:20 +0100, Will Deacon wrote:
>> Hi Qian,
>>
>> On Thu, Jun 13, 2019 at 05:34:01PM -0400, Qian Cai wrote:
>>> LTP hugemmap05 test case [1] could not exit itself properly and then degrade
>>> the
>>> system performance
Hi Pali,
Since design architecture change of CS19, input device connection has been
changed to below architecture,
Touchpad has been moved to I2C connection.
kernel/host <--PS/2--> EC <--PS/2--> external PS/2 mouse
| |
|<--PS/2-->
On 2019/6/16 21:11, Jonathan Cameron wrote:
> On Fri, 14 Jun 2019 23:28:46 +0800
> YueHaibing wrote:
>
>> Fix build error:
>>
>> drivers/staging/iio/addac/adt7316.c: In function adt7316_store_update_DAC:
>> drivers/staging/iio/addac/adt7316.c:949:3: error: implicit declaration of
>> function
On Tue, May 21, 2019 at 10:10:29AM +0200, Gerd Hoffmann wrote:
> Hi,
>
> The bug is in the driver, so ...
>
> > Bisecting the issue for commits to drivers/gpu/drm/bochs/ points to:
> > 6579c39594ae ("drm/bochs: atomic: switch planes to atomic, wire up
> > helpers.")
> > ... but the issue also
Hi, Bibby:
On Wed, 2019-06-12 at 16:53 +0800, Bibby Hsieh wrote:
> GCE cannot know the register base address, this function
> can help cmdq client to get the cmdq_client_reg structure.
>
> Signed-off-by: Bibby Hsieh
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 24
>
The minimum number of "cycles" is limited to 1 by
clockevents_config_and_register().
Signed-off-by: Dmitry Osipenko
---
drivers/clocksource/timer-tegra.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/clocksource/timer-tegra.c
b/drivers/clocksource/timer-tegra.c
Tegra's timer has 29 bits for the counter. The counter's value is smaller
than the actual value by 1, hence the maximum equals to 29 bits + 1.
Signed-off-by: Dmitry Osipenko
---
drivers/clocksource/timer-tegra.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Add device-tree binding for NVIDIA Tegra30 External Memory Controller.
The binding is based on the Tegra124 EMC binding since hardware is
similar, although there are couple significant differences.
Note that the memory timing description is given in a platform-specific
form because there is no
Add External Memory Controller node to the device-tree.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra30.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index e074258d4518..92c4aeafab29 100644
---
The register polling code was gone, but the included header change was
missed. Fix it up for consistency.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/tegra20-emc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/memory/tegra/tegra20-emc.c
Timing control debug features should be disabled at a boot time, but you
never now and hence it's better to disable them explicitly because some of
those features are crucial for the driver to do a proper thing.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/mc.c | 3 +++
The memory frequency scaling will be managed by tegra20-devfreq driver
and PM QoS once all the prerequisite patches will get upstreamed.
The parent clock is now managed by the clock driver and we also should
assume that PLLM rate can't be changed on some devices (Galaxy Tab 10.1
for example).
Introduce driver for the External Memory Controller (EMC) found on Tegra30
chips, it controls the external DRAM on the board. The purpose of this
driver is to program memory timing for external memory on the EMC clock
rate change.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/Kconfig
The emc_mux clock is gone now and EMC driver should provide the clock
rounding functionality.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/tegra20-emc.c | 55 --
1 file changed, 45 insertions(+), 10 deletions(-)
diff --git
A proper External Memory Controller clock rounding and parent selection
functionality is required by the EMC drivers. It is not available using
the generic clock implementation, hence add a custom one. The clock rate
rounding shall be done by the EMC drivers because they have information
about
There is no problem for drivers to request pll_m and pll_p clocks for
the device, hence there is no need to use clk_get_sys() and it could be
replaced with devm_clk_get() for consistency.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/tegra20-emc.c | 12
1 file changed, 4
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