Am 07.12.20 um 02:04 schrieb Tian Tao:
switch to using devm_add_action_or_reset() instead of devm_add_action.
Signed-off-by: Tian Tao
I'm surprised that devm_drm_dev_init() didn't already use
devm_add_action_or_reset(). But it doesn't look special, so
Acked-by: Thomas Zimmermann
---
Adrian,
On Thu, Dec 03, 2020 at 11:55:23AM +0200, Adrian Hunter wrote:
> On 1/12/20 5:09 am, AKASHI Takahiro wrote:
> > Adrian,
> >
> > Thank you for your review comments.
> >
> > On Thu, Nov 26, 2020 at 10:18:55AM +0200, Adrian Hunter wrote:
> >> On 25/11/20 9:41 am, AKASHI Takahiro wrote:
>
Abhishek Kumar wrote:
> In some devices difference in chip-id should be enough to pick
> the right BDF. Add another support for chip-id based BDF selection.
> With this new option, ath10k supports 2 fallback options.
>
> The board name with chip-id as option looks as follows
> board name
> From: Bean Huo
>
> Change dev_err() print message from "dme-reset" to "dme_enable" in
> function
> ufshcd_dme_enable().
>
> Signed-off-by: Bean Huo
Acked-by: Avri Altman
On Tue, Dec 8, 2020 at 3:21 PM Pankaj Gupta
wrote:
>
> > Although the ratio of the slab is one, we also should read the ratio
> > from the related memory_stats instead of hard-coding. And the local
> > variable of size is already the value of slab_unreclaimable. So we
> > do not need to read
> From: Bean Huo
>
> No user uses POWER_DESC_MAX_SIZE, remove it.
>
> Signed-off-by: Bean Huo
Acked-by: Avri Altman
On 07/12/2020 23:44, Rob Herring wrote:
> On Mon, Nov 23, 2020 at 03:51:56PM +0100, Neil Armstrong wrote:
>> The Amlogic G12A SoCs embeds an Analog MIPI D-PHY to communicate with DSI
>> panels, this adds the bindings.
>>
>> This Analog D-PHY works with a separate Digital MIPI D-PHY.
>>
>>
On 05.12.20 08:06, Sven Eckelmann wrote:
Hi,
> Is there some explanation besides an opinion? Some kind goal which you want
> to
> achieve with it maybe?
Just a cleanup. I've been under the impression that this version is just
an relic from oot times.
> At least for us it was an easy way to
在 2020/12/8 15:44, Qing Zhang 写道:
Add spi-ls7a binding documentation.
Signed-off-by: Qing Zhang
---
Documentation/devicetree/bindings/spi/spi-ls7a.txt | 31 ++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/spi-ls7a.txt
Use devm_drm_irq_install to register interrupts so that
drm_irq_uninstall is not needed to be called.
Signed-off-by: Tian Tao
---
drivers/gpu/drm/tidss/tidss_drv.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/tidss/tidss_drv.c
t...@redhat.com wrote:
> The macro use will already have a semicolon.
>
> Signed-off-by: Tom Rix
> Signed-off-by: Kalle Valo
Patch applied to ath-next branch of ath.git, thanks.
e65e8b608f68 carl9170: remove trailing semicolon in macro definition
--
The SPI controller has the following characteristics:
- Full-duplex synchronous serial data transmission
- Support up to 4 variable length byte transmission
- Main mode support
- Mode failure generates an error flag and issues an interrupt request
- Double buffer receiver
- Serial clock with
On 2020-12-07, John Ogness wrote:
> diff --git a/kernel/printk/printk.c b/kernel/printk/printk.c
> index e1f068677a74..f3c0fcc3163f 100644
> --- a/kernel/printk/printk.c
> +++ b/kernel/printk/printk.c
[...]
> int vprintk_store(int facility, int level,
> const struct
Add spi-ls7a binding documentation.
Signed-off-by: Qing Zhang
---
Documentation/devicetree/bindings/spi/spi-ls7a.txt | 31 ++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/spi-ls7a.txt
diff --git
This is now supported, enable for Loongson systems.
Signed-off-by: Qing Zhang
---
v2:
- Modify CONFIG_SPI_LOONGSON to CONFIG_SPI_LS7A
---
arch/mips/configs/loongson3_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/mips/configs/loongson3_defconfig
add spi and amd node support.
Signed-off-by: Qing Zhang
---
v2:
- Add spi about pci device DT
---
arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
On Mon, Dec 07, 2020 at 04:14:53PM -0800, Sowjanya Komatineni wrote:
> On 12/6/20 10:16 AM, Lukas Wunner wrote:
> > However, be sure to use the devm variant to *allocate* the SPI controller,
> > i.e. use devm_spi_alloc_master() instead of spi_alloc_master().
>
> Thanks Lukas. I see
On Mon, 7 Dec 2020 at 14:50, Horia Geantă wrote:
>
> On 11/26/2020 9:09 AM, Ard Biesheuvel wrote:
> > On Wed, 25 Nov 2020 at 22:39, Iuliana Prodan wrote:
> >>
> >> On 11/25/2020 11:16 PM, Ard Biesheuvel wrote:
> >>> On Wed, 25 Nov 2020 at 22:14, Iuliana Prodan (OSS)
> >>> wrote:
>
>
On Thu, Dec 03, 2020 at 11:42:34AM +0200, Adrian Hunter wrote:
> On 6/11/20 4:27 am, AKASHI Takahiro wrote:
> > This is a UHS-II version of sdhci's add_host/remove_host operation.
> > Any sdhci drivers which are capable of handling UHS-II cards must
> > call those functions instead of the
On 2020-12-07, John Ogness wrote:
> CONSOLE_EXT_LOG_MAX for extended console messages is already defined
> in printk.h. Define CONSOLE_LOG_MAX there as well so that future
> changes can make use of the constant for non-extended console
> messages.
Actually this patch is not necessary for this
From: Martin KaFai Lau
Date: Mon, 7 Dec 2020 22:54:18 -0800
> On Tue, Dec 01, 2020 at 11:44:10PM +0900, Kuniyuki Iwashima wrote:
>
> > @@ -242,8 +244,12 @@ void reuseport_detach_sock(struct sock *sk)
> >
> > reuse->num_socks--;
> > reuse->socks[i] =
On Thu, 26 Nov 2020 12:51:57 +0100 SeongJae Park wrote:
> Hi Shakeel,
>
>
> Thanks for the review! :D
>
> On Wed, 25 Nov 2020 07:29:10 -0800 Shakeel Butt wrote:
>
> > On Tue, Oct 20, 2020 at 2:01 AM SeongJae Park wrote:
> > >
> > > From: SeongJae Park
> > >
> > > DAMON is a data access
Hello,
syzbot found the following issue on:
HEAD commit:b3298500 Merge tag 'for-5.10/dm-fixes' of git://git.kernel..
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=144f0bf750
kernel config: https://syzkaller.appspot.com/x/.config?x=e49433cfed49b7d9
On Tue, Dec 01, 2020 at 06:46:39PM +0200, Adrian Hunter wrote:
> On 6/11/20 4:27 am, AKASHI Takahiro wrote:
> > This is a UHS-II version of sdhci's request() operation.
> > It handles UHS-II related command interrupts and errors.
> >
> > Signed-off-by: Ben Chuang
> > Signed-off-by: AKASHI
From: Leon Romanovsky
Hi,
This is set of various and unrelated fixes that we collected over time.
Thanks
Avihai Horon (1):
RDMA/uverbs: Fix incorrect variable type
Jack Morgenstein (2):
RDMA/core: Clean up cq pool mechanism
RDMA/core: Do not indicate device ready when device enablement
On Tue, Dec 08, 2020 at 03:31:34PM +0900, Kuniyuki Iwashima wrote:
> From: Martin KaFai Lau
> Date: Mon, 7 Dec 2020 12:33:15 -0800
> > On Thu, Dec 03, 2020 at 11:14:24PM +0900, Kuniyuki Iwashima wrote:
> > > From: Eric Dumazet
> > > Date: Tue, 1 Dec 2020 16:25:51 +0100
> > > > On 12/1/20
On 12/8/2020 11:29 AM, Artur Petrosyan wrote:
> On 12/4/2020 12:36, Xu Wang wrote:
>> Because clk_prepare_enable() and clk_disable_unprepare() already checked
>> NULL clock parameter, so the additional checks are unnecessary, just
>> remove them.
>>
>> Signed-off-by: Xu Wang
>
> Reviewed-by:
Xiaohui Zhang wrote:
> From: Zhang Xiaohui
>
> mwifiex_cmd_802_11_ad_hoc_start() calls memcpy() without checking
> the destination size may trigger a buffer overflower,
> which a local user could use to cause denial of service
> or the execution of arbitrary code.
> Fix it by putting the
Hi Doug,
On Mon, Dec 7, 2020 at 11:15 PM Doug Anderson wrote:
> On Mon, Dec 7, 2020 at 1:55 PM Arnd Bergmann wrote:
> > On Mon, Dec 7, 2020 at 9:23 PM Geert Uytterhoeven
> > wrote:
> > > On Tue, Dec 1, 2020 at 3:06 PM Arnd Bergmann wrote:
> > > > On Tue, Dec 1, 2020 at 12:39 PM Ulf Hansson
Please use --thread=shallow while creating the patches, I use the following
options normally, so they appear as a thread.
git format-patch -C -M --thread=shallow
--
viresh
On 12/4/2020 12:36, Xu Wang wrote:
> Because clk_prepare_enable() and clk_disable_unprepare() already checked
> NULL clock parameter, so the additional checks are unnecessary, just
> remove them.
>
> Signed-off-by: Xu Wang
Reviewed-by: Artur Petrosyan
> ---
> drivers/usb/dwc2/platform.c |
Hi Johan,
Yes, I will post NFC code to Uboot，but it may take a while to modify the code
for Uboot.
--
yifeng
>Hi Yifeng,
>
>Meanwhile, could you post a RFC version for Uboot based on this version
>plus comments, so people can test the whole process from programming,
>booting and
Hi Laurent,
On 07. 12. 20 23:16, Laurent Pinchart wrote:
> Hi Michal,
>
> On Mon, Dec 07, 2020 at 10:39:25AM +0100, Michal Simek wrote:
>> On 06. 12. 20 23:46, Laurent Pinchart wrote:
>>> On Wed, Dec 02, 2020 at 03:06:05PM +0100, Michal Simek wrote:
Add label which is used by bootloader for
On Mon, Dec 7, 2020 at 12:43 PM syzbot
wrote:
>
> Hello,
>
> syzbot found the following issue on:
>
> HEAD commit:bcd684aa net/nfc/nci: Support NCI 2.x initial sequence
> git tree: net-next
> console output: https://syzkaller.appspot.com/x/log.txt?x=12001bd350
> kernel config:
On 08-12-20, 07:22, Nicola Mazzucato wrote:
> On 12/8/20 5:50 AM, Viresh Kumar wrote:
> > On 02-12-20, 17:23, Nicola Mazzucato wrote:
> >>nr_opp = dev_pm_opp_get_opp_count(cpu_dev);
> >>if (nr_opp <= 0) {
> >> - dev_dbg(cpu_dev, "OPP table is not ready, deferring probe\n");
> >> -
On Mon, Dec 7, 2020 at 9:03 PM syzbot
wrote:
>
> Hello,
>
> syzbot found the following issue on:
>
> HEAD commit:34da8721 selftests/bpf: Test bpf_sk_storage_get in tcp ite..
> git tree: bpf-next
> console output: https://syzkaller.appspot.com/x/log.txt?x=10c3b83750
> kernel config:
On Mon, Nov 30, 2020 at 11:01 AM Suren Baghdasaryan wrote:
>
> On Wed, Nov 25, 2020 at 3:43 PM Minchan Kim wrote:
> >
> > On Wed, Nov 25, 2020 at 03:23:40PM -0800, Suren Baghdasaryan wrote:
> > > On Wed, Nov 25, 2020 at 3:13 PM Minchan Kim wrote:
> > > >
> > > > On Mon, Nov 23, 2020 at
Enable cpufreq for all CPU cores on a100.
Signed-off-by: Shuosheng Huang
---
.../allwinner/sun50i-a100-allwinner-perf1.dts| 16
arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 6 +++---
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git
a...@linux-foundation.org wrote:
> The patch titled
> Subject: revert "mm/filemap: add static for function
> __add_to_page_cache_locked"
> has been added to the -mm tree. Its filename is
>
> revert-mm-filemap-add-static-for-function-__add_to_page_cache_locked.patch
>
> This patch
The ETM device can't keep up with the core pipeline when cpu core
is at full speed. This may cause overflow within core and its ETM.
This is a common phenomenon on ETM devices.
On HiSilicon Hip08 platform, a specific feature is added to set
core pipeline. So commit rate can be reduced manually to
> Although the ratio of the slab is one, we also should read the ratio
> from the related memory_stats instead of hard-coding. And the local
> variable of size is already the value of slab_unreclaimable. So we
> do not need to read again.
>
> We can drop the ratio in struct memory_stat. This can
Add an Operating Performance Points table for the CPU cores to
enable Dynamic Voltage & Frequency Scaling on the A100.
Signed-off-by: Shuosheng Huang
---
.../allwinner/sun50i-a100-allwinner-perf1.dts | 1 +
.../dts/allwinner/sun50i-a100-cpu-opp.dtsi| 90 +++
2 files
Add CPU speed grade efuse cell for a100.
Signed-off-by: Shuosheng Huang
---
arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
index
Add clocks to CPU cores for a100.
Signed-off-by: Shuosheng Huang
---
arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
index
Hi Viresh,
thanks for looking into this. Please find below
On 12/8/20 5:50 AM, Viresh Kumar wrote:
> On 02-12-20, 17:23, Nicola Mazzucato wrote:
>> By design, SCMI performance domains define the granularity of
>> performance controls, they do not describe any underlying hardware
>> dependencies
It's better to use efuse_xlate to extract the differentiated part
regarding different SoC.
Signed-off-by: Shuosheng Huang
---
drivers/cpufreq/sun50i-cpufreq-nvmem.c | 82 --
1 file changed, 51 insertions(+), 31 deletions(-)
diff --git
Add cpufreq nvmem based for allwinner a100 SoC, it's similar to h6.
Signed-off-by: Shuosheng Huang
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
drivers/cpufreq/sun50i-cpufreq-nvmem.c | 32 ++
2 files changed, 33 insertions(+)
diff --git
The clk enable bit should be 31 instead of 24.
Signed-off-by: Zong Li
Reported-by: Pragnesh Patel
---
drivers/clk/sifive/sifive-prci.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h
index
Add driver code for the SiFive FU740 PRCI IP block. This IP block
handles reset and clock control for the SiFive FU740 device and
implements SoC-level clock tree controls and dividers.
The link of unmatched as follow, and the U740-C000 manual would
be present in the same page as soon.
Use generic name CLK_SIFIVE_PRCI instead of CLK_SIFIVE_FU540_PRCI. This
patch is prepared for fu740 support.
Signed-off-by: Zong Li
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
Reviewed-by: Pragnesh Patel
---
arch/riscv/Kconfig.socs | 2 +-
drivers/clk/sifive/Kconfig | 6 +++---
From: Pragnesh Patel
Add new functions "sifive_prci_clock_enable(), sifive_prci_clock_disable()
and sifive_clk_is_enabled()" to enable or disable the PRCI clock
Signed-off-by: Pragnesh Patel
Tested-by: Zong Li
---
drivers/clk/sifive/fu540-prci.c | 6 +++
drivers/clk/sifive/fu740-prci.c |
Add a driver for the SiFive FU740 PRCI IP block, which handles more
clocks than FU540. These patches also refactor the original
implementation by spliting the dependent-code of fu540 and fu740
respectively.
We also add a separate patch for DT binding documentation of FU740 PRCI:
Extract common core of prci driver to an independent file, it could
allow other chips to reuse it. Separate SoCs-dependent code 'fu540'
from prci core, then we can easily add 'fu740' later.
Almost these changes are code movement. The different is adding the
private data for each SoC use, so it
On 2020-12-06 18:13, Bean Huo wrote:
From: Bean Huo
Currently UFS WriteBooster driver uses clock scaling up/down to set
WB on/off, for the platform which doesn't support
UFSHCD_CAP_CLK_SCALING,
WB will be always on. Provide a sysfs attribute to enable/disable WB
during runtime. Write 1/0 to
On (20/12/08 13:54), Tomasz Figa wrote:
>
> In any case, Sergey is going to share a preliminary patch on how the
> current API would be used in the V4L2 videobuf2 framework. That should
> give us more input on how such a helper could look.
HUGE apologies for the previous screw up! I replied in
Hi Viresh,
thanks for your comments. I will update subject and content as you suggested.
Regards,
Nicola
On 12/8/20 4:29 AM, Viresh Kumar wrote:
> Subject should rather be:
>
> dt-bindings: opp: Allow empty OPP tables
>
> On 02-12-20, 17:23, Nicola Mazzucato wrote:
>> Currently the optional
As reported by sparse:
drivers/media/test-drivers/vidtv/vidtv_ts.h:47:47: warning: array of
flexible structures
drivers/media/test-drivers/vidtv/vidtv_channel.c:458:54: warning:
incorrect type in argument 3 (different base types)
On 08.12.20 03:36, Jason Wang wrote:
Hi,
> So we endup with two solutions (without a prompt):
>
> 1) using select, user may end up with driver without transport
IMHO not an entirely unusual situation in other places of the kernel,
eg. one can enable USB devices, w/o having an usb host adapter
On Mon, Dec 7, 2020 at 7:12 PM Robin Murphy wrote:
>
> On 2020-12-02 10:29, Laurentiu Tudor wrote:
> > Hi Robin,
> >
> > Sorry for the late reply, we had a few days of over here. Comments inline.
> >
> > On 11/25/2020 8:10 PM, Robin Murphy wrote:
> >> On 2020-11-25 15:50, laurentiu.tu...@nxp.com
> -Original Message-
> From: Krzysztof Kozlowski
> Sent: Tuesday, December 8, 2020 12:35 AM
> To: Krzysztof Kozlowski ; linux-arm-
> ker...@lists.infradead.org; linux-samsung-...@vger.kernel.org; linux-
> ker...@vger.kernel.org
> Cc: Sylwester Nawrocki ; Marek Szyprowski
> ; Bartlomiej
On Tue, Dec 01, 2020 at 11:44:10PM +0900, Kuniyuki Iwashima wrote:
> @@ -242,8 +244,12 @@ void reuseport_detach_sock(struct sock *sk)
>
> reuse->num_socks--;
> reuse->socks[i] = reuse->socks[reuse->num_socks];
> + prog = rcu_dereference(reuse->prog);
>
From: Vivek Aknurwar
This adds Global Clock controller (GCC) driver for SM8350 SoC
Signed-off-by: Vivek Aknurwar
Signed-off-by: Jeevan Shriram
[vkoul: rebase and tidy up for upstream]
Signed-off-by: Vinod Koul
---
drivers/clk/qcom/Kconfig |9 +
drivers/clk/qcom/Makefile |1
From: Vivek Aknurwar
Lucid 5LPE is a slightly different Lucid PLL with different offsets and
porgramming sequence so add support for these
Signed-off-by: Vivek Aknurwar
Signed-off-by: Jeevan Shriram
[vkoul: rebase and tidy up for upstream]
Signed-off-by: Vinod Koul
---
Add bindings and update documentation for clock rpmh driver on SM8350.
Reviewed-by: Bjorn Andersson
Signed-off-by: Vinod Koul
---
Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
Add device tree bindings for global clock controller on SM8350 SoCs.
Signed-off-by: Vinod Koul
---
.../bindings/clock/qcom,gcc-sm8350.yaml | 68 +
include/dt-bindings/clock/qcom,gcc-sm8350.h | 261 ++
2 files changed, 329 insertions(+)
create mode 100644
This adds rpmhcc and gcc clock controller drivers for the controllers found
in SM8350 SoC
Changes in v2:
- Add r-b from Bjorn
- Add the gcc_qupv3_wrap_1_{m|s}_ahb_clk and gcc_qupv3_wrap1_s5_clk
Vinod Koul (3):
dt-bindings: clock: Add RPMHCC bindings for SM8350
clk: qcom: rpmh: add support
This adds the RPMH clocks present in SM8350 SoC
Reviewed-by: Bjorn Andersson
Signed-off-by: Vinod Koul
---
drivers/clk/qcom/clk-rpmh.c | 34 +++
include/dt-bindings/clock/qcom,rpmh.h | 8 +++
2 files changed, 42 insertions(+)
diff --git
On Thu, 3 Dec 2020, Jinyang He wrote:
> Thus, only one synci operation is required when synci_step is 0
> on Loongson64 platform. I guess that some other platforms have
> similar implementations on synci, so add judgment conditions in
> `while` to ensure that at least all platforms perform synci
On 07.12.20 21:48, Jason Andryuk wrote:
On Mon, Dec 7, 2020 at 8:30 AM Juergen Gross wrote:
Commit 9e2369c06c8a18 ("xen: add helpers to allocate unpopulated
memory") introduced usage of ZONE_DEVICE memory for foreign memory
mappings.
Unfortunately this collides with using page->lru for Xen
On Mon, Dec 07, 2020 at 06:32:55PM +0100, Lukas Bulwahn wrote:
> Commit 66f57b871efc ("RDMA/restrack: Support all QP types") extends
> ib_create_qp() to a named ib_create_named_qp(), which takes the caller's
> name as argument, but it did not add the new argument description to the
> function's
On 12/7/20 11:12 PM, Douglas Gilbert wrote:
On 2020-12-07 9:56 a.m., Hannes Reinecke wrote:
On 12/7/20 3:11 PM, Christoph Hellwig wrote:
So, I'm really worried about:
a) a good use case. GC in f2fs or btrfs seem like good use cases, as
does accelating dm-kcopyd. I agree with Damien
Brendan Jackman wrote:
> This adds two atomic opcodes, both of which include the BPF_FETCH
> flag. XCHG without the BPF_FETCH flag would naturally encode
> atomic_set. This is not supported because it would be of limited
> value to userspace (it doesn't imply any barriers). CMPXCHG without
>
Hi Rob,
On 07/12/2020 21.42, Rob Herring wrote:
> On Tue, Nov 17, 2020 at 12:56:47PM +0200, Peter Ujfalusi wrote:
>> New binding document for
>> Texas Instruments K3 Block Copy DMA (BCDMA).
>>
>> BCDMA is introduced as part of AM64.
>>
>> Signed-off-by: Peter Ujfalusi
>> ---
>>
Brendan Jackman wrote:
> This adds two atomic opcodes, both of which include the BPF_FETCH
> flag. XCHG without the BPF_FETCH flag would naturally encode
> atomic_set. This is not supported because it would be of limited
> value to userspace (it doesn't imply any barriers). CMPXCHG without
>
On Mon, Dec 07, 2020 at 12:36:43PM -0800, Saravana Kannan wrote:
> On Mon, Dec 7, 2020 at 11:54 AM Leon Romanovsky wrote:
> >
> > On Mon, Dec 07, 2020 at 11:25:15AM -0800, Saravana Kannan wrote:
> > > On Sat, Dec 5, 2020 at 11:26 PM Leon Romanovsky wrote:
> > > >
> > > > On Fri, Nov 20, 2020 at
On Mon, Dec 7, 2020 at 9:06 PM syzbot
wrote:
>
> syzbot suspects this issue was fixed by commit:
>
> commit 1d0e850a49a5b56f8f3cb51e74a11e2fedb96be6
> Author: David Howells
> Date: Fri Oct 16 12:21:14 2020 +
>
> afs: Fix cell removal
>
> bisection log:
From: Martin KaFai Lau
Date: Mon, 7 Dec 2020 12:33:15 -0800
> On Thu, Dec 03, 2020 at 11:14:24PM +0900, Kuniyuki Iwashima wrote:
> > From: Eric Dumazet
> > Date: Tue, 1 Dec 2020 16:25:51 +0100
> > > On 12/1/20 3:44 PM, Kuniyuki Iwashima wrote:
> > > > This patch lets
From: Martin KaFai Lau
Date: Mon, 7 Dec 2020 12:14:38 -0800
> On Sun, Dec 06, 2020 at 01:03:07AM +0900, Kuniyuki Iwashima wrote:
> > From: Martin KaFai Lau
> > Date: Fri, 4 Dec 2020 17:42:41 -0800
> > > On Tue, Dec 01, 2020 at 11:44:10PM +0900, Kuniyuki Iwashima wrote:
> > > [ ... ]
> >
Since the host->ops->prepare_hs400_tuning had been moved to
mmc_select_hs400() the tuning for hs200 can simplify and
the function mmc_hs200_tuning() can be removed.
Signed-off-by: Chris Ruehl
---
drivers/mmc/core/mmc.c | 22 +-
1 file changed, 1 insertion(+), 21 deletions(-)
Function mmc_select_hs400() and mmc_select_hs400es have almost
identical code it seems okay to merge them.
Add the function calls for enhanced strobe to mmc_select_hs400 and
add a bool variable to the function call to enable them if HS400ES
is selected.
mmc_select_hs400es() becomes obsolate and
Move mmc_select_hs400() out from hs200 init path and make hs400
independent.
The patch makes quite some changes and needs to be reviewed carefully.
In function mmc_select_timing() call for mmc_select_hs400().
HS400 requires a host bus with of 8bit, if not supported we
return with -ENOTSUPP,
Enhanced strobe function had been merged in mmc_select_hs400();
mmc_select_hs400es() is obsolate and removed.
Signed-off-by: Chris Ruehl
---
drivers/mmc/core/mmc.c | 94 --
1 file changed, 94 deletions(-)
diff --git a/drivers/mmc/core/mmc.c
Fix the probe if hs400-1_8v / hs400-1_2v is used in the
dts and mmc-hs400-enhanced-strobe isn't set.
That was the first attemped, but it turns out that some
more cleanups and simplifications can be done.
* move mmc_select_hs400() in between hs200 & hs400es (preparation)
* make mmc_select_hs400()
This patch didn't change functionality just move
mmc_select_hs400() and mmc_hs200_to_hs400() between
mmc_select_hs400es() and mmc_select_hs200.
fix checkpatch --script warings.
Signed-off-by: Chris Ruehl
---
drivers/mmc/core/mmc.c | 184 -
1 file changed,
When set mmc-hs400-1_8(2)v in dts, hs200 capabilities are not checked
in the mmc logic. Thus cleanup and remove MMC_CAP2_HS200_1_8V_SDR /
MMC_CAP2_HS200_1_2V_SDR from host->caps2.
Signed-off-by: Chris Ruehl
---
drivers/mmc/core/host.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
> -Original Message-
> From: Krzysztof Kozlowski
> Sent: Tuesday, December 8, 2020 12:35 AM
> To: Krzysztof Kozlowski ; linux-arm-
> ker...@lists.infradead.org; linux-samsung-...@vger.kernel.org; linux-
> ker...@vger.kernel.org
> Cc: Sylwester Nawrocki ; Marek Szyprowski
> ; Bartlomiej
> -Original Message-
> From: Krzysztof Kozlowski
> Sent: Tuesday, December 8, 2020 12:35 AM
> To: Krzysztof Kozlowski ; linux-arm-
> ker...@lists.infradead.org; linux-samsung-...@vger.kernel.org; linux-
> ker...@vger.kernel.org
> Cc: Sylwester Nawrocki ; Marek Szyprowski
> ; Bartlomiej
On 12/8/2020 2:07 AM, Bjorn Helgaas wrote:
External email: Use caution opening links or attachments
[+cc Jingoo, Gustavo]
On Thu, Dec 03, 2020 at 07:04:51PM +0530, Vidya Sagar wrote:
PCIe cards like Marvell SATA controller and some of the Samsung NVMe
drives don't support taking the link
From: Carlo Caione
The WiFi media button on the Quanta NL3 reports keycodes 0x8b and 0x9b
to the platform driver. Add the mapping to support these codes.
Signed-off-by: Carlo Caione
Reviewed-by: Chris Chiu
---
drivers/platform/x86/classmate-laptop.c | 2 ++
1 file changed, 2 insertions(+)
On Tue, Dec 08, 2020 at 08:51:45AM +0900, Daeho Jeong wrote:
> > I am trying to review this but it is very hard, as the f2fs compression
> > code is
> > very hard to understand.
> >
> > It looks like a 'struct decompress_io_ctx' represents the work to
> > decompress a
> > particular cluster.
Hi Bjorn,
On 11/30/20 5:11 PM, Kuppuswamy, Sathyanarayanan wrote:
Hi Bjorn,
On 11/25/20 7:48 PM, Kuppuswamy, Sathyanarayanan wrote:
Along with above patch, you also left following two cleanup patches. Is this
intentional? Following fixes have no dependency on pcie_ports_dpc_native change.
Tha ARCHOS Cesium 140 tablet has problem with the jack-sensing,
thus the heaset functions are not working.
Add quirk for this model to select the correct input map, jack-detect
options and channel map to enable jack sensing and headset microphone.
This device uses IN1 for its internal MIC and JD2
>I'm not sure about the logic here. Why would the secondary master
>initialize the bus? If you make a distinction between primary and
>secondary, then the primary should be the owner of the bus and it should
>have enumerated it already. You should populate the bus structure with
>info provided by
> -Original Message-
> From: Krzysztof Kozlowski
> Sent: Tuesday, December 8, 2020 12:35 AM
> To: Krzysztof Kozlowski ; linux-arm-
> ker...@lists.infradead.org; linux-samsung-...@vger.kernel.org; linux-
> ker...@vger.kernel.org
> Cc: Sylwester Nawrocki ; Marek Szyprowski
> ; Bartlomiej
This introduces the pureLiFi LiFi driver for LiFi-X, LiFi-XC
and LiFi-XL USB devices.
This driver implementation has been based on the zd1211rw driver.
Driver is based on 802.11 softMAC Architecture and uses
native 802.11 for configuration and management.
The driver is compiled and tested in
On 02-12-20, 17:23, Nicola Mazzucato wrote:
> By design, SCMI performance domains define the granularity of
> performance controls, they do not describe any underlying hardware
> dependencies (although they may match in many cases).
>
> It is therefore possible to have some platforms where
UFS 3.1 specification mentions that below WriteBooster flags will be
set to default value, say disabled, after power cycle or any type
of reset event. Thus we need to reset those flag variables kept
in struct hba to align the device status and ensure WriteBooster
related functions being configured
>This looks a bit confusing. Here you're rolling back detailss in
>i3c_primary_master_register() that were factored out in
>i3c_master_init(). If i3c_master_init() is successful, then you
>shouldn't be undoing its things openly in i3c_primary_master_register().
>Instead, there should be another
Hi Bjorn,
On Mon, Dec 07, 2020 at 10:44:46PM -0600, Bjorn Andersson wrote:
> Some bridge chips, such as the TI SN65DSI86 DSI/eDP bridge, provides
> means of generating a PWM signal for backlight control of the attached
> panel. The provided PWM chip is typically controlled by the
> pwm-backlight
arm64 references the start address of .builtin_fw (__start_builtin_fw)
with a pair of R_AARCH64_ADR_PREL_PG_HI21/R_AARCH64_LDST64_ABS_LO12_NC
relocations. The compiler is allowed to emit the
R_AARCH64_LDST64_ABS_LO12_NC relocation because struct builtin_fw in
include/linux/firmware.h is 8-byte
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