On Fri, 5 Oct 2018 17:40:44 +0200
Ricardo Ribalda Delgado wrote:
> Hi Boris
> On Fri, Oct 5, 2018 at 4:52 PM Boris Brezillon
> wrote:
> >
> > On Fri, 5 Oct 2018 16:06:57 +0200
> > Ricardo Ribalda Delgado wrote:
> >
> > > Hi again Boris
> > &g
On Fri, 5 Oct 2018 17:40:44 +0200
Ricardo Ribalda Delgado wrote:
> Hi Boris
> On Fri, Oct 5, 2018 at 4:52 PM Boris Brezillon
> wrote:
> >
> > On Fri, 5 Oct 2018 16:06:57 +0200
> > Ricardo Ribalda Delgado wrote:
> >
> > > Hi again Boris
> > &g
On Fri, 5 Oct 2018 14:04:52 +0200
Ricardo Ribalda Delgado wrote:
> Hi Boris
> On Fri, Oct 5, 2018 at 12:12 PM Boris Brezillon
> wrote:
> >
> > On Fri, 5 Oct 2018 11:54:18 +0200
> > Ricardo Ribalda Delgado wrote:
> >
> > > Hi Boris
> > &g
On Fri, 5 Oct 2018 14:04:52 +0200
Ricardo Ribalda Delgado wrote:
> Hi Boris
> On Fri, Oct 5, 2018 at 12:12 PM Boris Brezillon
> wrote:
> >
> > On Fri, 5 Oct 2018 11:54:18 +0200
> > Ricardo Ribalda Delgado wrote:
> >
> > > Hi Boris
> > &g
On Fri, 5 Oct 2018 16:06:57 +0200
Ricardo Ribalda Delgado wrote:
> Hi again Boris
>
>
> On Fri, Oct 5, 2018 at 2:10 PM Boris Brezillon
> wrote:
> >
> > On Fri, 5 Oct 2018 14:04:52 +0200
> > Ricardo Ribalda Delgado wrote:
> >
> > > Hi B
On Fri, 5 Oct 2018 16:06:57 +0200
Ricardo Ribalda Delgado wrote:
> Hi again Boris
>
>
> On Fri, Oct 5, 2018 at 2:10 PM Boris Brezillon
> wrote:
> >
> > On Fri, 5 Oct 2018 14:04:52 +0200
> > Ricardo Ribalda Delgado wrote:
> >
> > > Hi B
On Fri, 5 Oct 2018 14:04:52 +0200
Ricardo Ribalda Delgado wrote:
> Hi Boris
> On Fri, Oct 5, 2018 at 12:12 PM Boris Brezillon
> wrote:
> >
> > On Fri, 5 Oct 2018 11:54:18 +0200
> > Ricardo Ribalda Delgado wrote:
> >
> > > Hi Boris
> > &g
On Fri, 5 Oct 2018 14:04:52 +0200
Ricardo Ribalda Delgado wrote:
> Hi Boris
> On Fri, Oct 5, 2018 at 12:12 PM Boris Brezillon
> wrote:
> >
> > On Fri, 5 Oct 2018 11:54:18 +0200
> > Ricardo Ribalda Delgado wrote:
> >
> > > Hi Boris
> > &g
On Fri, 5 Oct 2018 14:04:52 +0200
Ricardo Ribalda Delgado wrote:
> Hi Boris
> On Fri, Oct 5, 2018 at 12:12 PM Boris Brezillon
> wrote:
> >
> > On Fri, 5 Oct 2018 11:54:18 +0200
> > Ricardo Ribalda Delgado wrote:
> >
> > > Hi Boris
> > &g
On Fri, 5 Oct 2018 14:04:52 +0200
Ricardo Ribalda Delgado wrote:
> Hi Boris
> On Fri, Oct 5, 2018 at 12:12 PM Boris Brezillon
> wrote:
> >
> > On Fri, 5 Oct 2018 11:54:18 +0200
> > Ricardo Ribalda Delgado wrote:
> >
> > > Hi Boris
> > &g
On Fri, 5 Oct 2018 11:54:18 +0200
Ricardo Ribalda Delgado wrote:
> Hi Boris
>
> Just seen that you already did the rebase at
> https://github.com/bbrezillon/linux-0day/commits/mtd/physmap-cleanup
>
> Thanks for that.
>
> I am about to test it in real hw (unless you want me wait)
Sure, go
On Fri, 5 Oct 2018 11:54:18 +0200
Ricardo Ribalda Delgado wrote:
> Hi Boris
>
> Just seen that you already did the rebase at
> https://github.com/bbrezillon/linux-0day/commits/mtd/physmap-cleanup
>
> Thanks for that.
>
> I am about to test it in real hw (unless you want me wait)
Sure, go
On Fri, 5 Oct 2018 11:41:59 +0200
wrote:
> +struct stm32_fmc2 {
You should inherit from nand_controller even if the nand_chip already
embeds a dummy nand controller object.
struct nand_controller base;
> + struct stm32_fmc2_nand nand;
> + struct device *dev;
> + void
On Fri, 5 Oct 2018 11:41:59 +0200
wrote:
> +struct stm32_fmc2 {
You should inherit from nand_controller even if the nand_chip already
embeds a dummy nand controller object.
struct nand_controller base;
> + struct stm32_fmc2_nand nand;
> + struct device *dev;
> + void
ns 5 to 7 contain the same areas for CS1.
Maybe you could use reg-names here ("nfc", "csX-data", "csX-cmd",
"csX-addr"). Anyway, even without this
Reviewed-by: Boris Brezillon
> +- interrupts: The interrupt number
> +- pinctrl-0: Standard Pinctr
ns 5 to 7 contain the same areas for CS1.
Maybe you could use reg-names here ("nfc", "csX-data", "csX-cmd",
"csX-addr"). Anyway, even without this
Reviewed-by: Boris Brezillon
> +- interrupts: The interrupt number
> +- pinctrl-0: Standard Pinctr
On Fri, 5 Oct 2018 10:10:22 +0200
Ricardo Ribalda Delgado wrote:
> On Fri, Oct 5, 2018 at 9:08 AM Boris Brezillon
> wrote:
> >
> > Hi Ricardo,
> >
> > On Fri, 5 Oct 2018 08:31:35 +0200
> > Ricardo Ribalda Delgado wrote:
> >
> > > Hi Bori
On Fri, 5 Oct 2018 10:10:22 +0200
Ricardo Ribalda Delgado wrote:
> On Fri, Oct 5, 2018 at 9:08 AM Boris Brezillon
> wrote:
> >
> > Hi Ricardo,
> >
> > On Fri, 5 Oct 2018 08:31:35 +0200
> > Ricardo Ribalda Delgado wrote:
> >
> > > Hi Bori
Hi Ricardo,
On Fri, 5 Oct 2018 08:31:35 +0200
Ricardo Ribalda Delgado wrote:
> Hi Boris
>
>
> On Fri, Oct 5, 2018 at 12:21 AM Boris Brezillon
> wrote:
> >
> > Hi Ricardo,
> >
> > On Thu, 4 Oct 2018 16:29:42 +0200
> > Ricardo Ribalda Delgado wrot
Hi Ricardo,
On Fri, 5 Oct 2018 08:31:35 +0200
Ricardo Ribalda Delgado wrote:
> Hi Boris
>
>
> On Fri, Oct 5, 2018 at 12:21 AM Boris Brezillon
> wrote:
> >
> > Hi Ricardo,
> >
> > On Thu, 4 Oct 2018 16:29:42 +0200
> > Ricardo Ribalda Delgado wrot
Hi Ricardo,
On Thu, 4 Oct 2018 16:29:42 +0200
Ricardo Ribalda Delgado wrote:
> Allow creating gpio-addr-flash via device-tree and not just via platform
> data.
>
> Mimic what physmap_of_versatile and physmap_of_gemini does to reduce
> code duplicity.
>
> Signed-off-by: Ricardo Ribalda
Hi Ricardo,
On Thu, 4 Oct 2018 16:29:42 +0200
Ricardo Ribalda Delgado wrote:
> Allow creating gpio-addr-flash via device-tree and not just via platform
> data.
>
> Mimic what physmap_of_versatile and physmap_of_gemini does to reduce
> code duplicity.
>
> Signed-off-by: Ricardo Ribalda
On Thu, 04 Oct 2018 16:11:42 +0200
Janusz Krzysztofik wrote:
>
> Legacy nand_wait_ready() uses a hardcoded timeout value of 400 ms. Should
> we
> follow the same approach in nand_gpio_waitrdy(), or should we rather let
> drivers pass the timeout value, like in case of nand_soft_waitrdy()?
On Thu, 04 Oct 2018 16:11:42 +0200
Janusz Krzysztofik wrote:
>
> Legacy nand_wait_ready() uses a hardcoded timeout value of 400 ms. Should
> we
> follow the same approach in nand_gpio_waitrdy(), or should we rather let
> drivers pass the timeout value, like in case of nand_soft_waitrdy()?
On Thu, 4 Oct 2018 15:01:09 +0200
Ricardo Ribalda Delgado wrote:
> Add documentation for gpio-addr-flash. This binding allow creating
> flash devices that are paged using GPIOs.
>
> Cc: devicet...@vger.kernel.org
> Reviewed-by: Rob Herring
> Signed-off-by: Ricardo Ribalda Delgado
> ---
>
On Thu, 4 Oct 2018 15:01:09 +0200
Ricardo Ribalda Delgado wrote:
> Add documentation for gpio-addr-flash. This binding allow creating
> flash devices that are paged using GPIOs.
>
> Cc: devicet...@vger.kernel.org
> Reviewed-by: Rob Herring
> Signed-off-by: Ricardo Ribalda Delgado
> ---
>
On Thu, 04 Oct 2018 15:52:57 +0200
Janusz Krzysztofik wrote:
> Hi Boris,
>
> On Wednesday, October 3, 2018 4:06:34 PM CEST Boris Brezillon wrote:
> > On Wed, 03 Oct 2018 15:55:25 +0200
> > Janusz Krzysztofik wrote:
> >
> > > > >
> > > &
On Thu, 04 Oct 2018 15:52:57 +0200
Janusz Krzysztofik wrote:
> Hi Boris,
>
> On Wednesday, October 3, 2018 4:06:34 PM CEST Boris Brezillon wrote:
> > On Wed, 03 Oct 2018 15:55:25 +0200
> > Janusz Krzysztofik wrote:
> >
> > > > >
> > > &
On Thu, 4 Oct 2018 15:01:02 +0200
Ricardo Ribalda Delgado wrote:
> This struct does not seem to be used anywhere on the code
>
> Signed-off-by: Ricardo Ribalda Delgado
Already queued that one.
> ---
> drivers/mtd/maps/physmap_of_gemini.c | 5 -
> 1 file changed, 5 deletions(-)
>
>
On Thu, 4 Oct 2018 15:01:02 +0200
Ricardo Ribalda Delgado wrote:
> This struct does not seem to be used anywhere on the code
>
> Signed-off-by: Ricardo Ribalda Delgado
Already queued that one.
> ---
> drivers/mtd/maps/physmap_of_gemini.c | 5 -
> 1 file changed, 5 deletions(-)
>
>
Hi Ricardo,
On Thu, 4 Oct 2018 15:01:01 +0200
Ricardo Ribalda Delgado wrote:
> During probe, if there was an error the memory region and the memory
> map were not properly released.
>
> This can lead a system unusable if deferred probe is in use.
>
> Signed-off-by: Ricardo Ribalda Delgado
>
Hi Ricardo,
On Thu, 4 Oct 2018 15:01:01 +0200
Ricardo Ribalda Delgado wrote:
> During probe, if there was an error the memory region and the memory
> map were not properly released.
>
> This can lead a system unusable if deferred probe is in use.
>
> Signed-off-by: Ricardo Ribalda Delgado
>
On Thu, 4 Oct 2018 12:07:17 +
Yogesh Narayan Gaur wrote:
> Hi Boris,
>
> > -Original Message-
> > From: Yogesh Narayan Gaur
> > Sent: Thursday, October 4, 2018 2:56 PM
> > To: 'Boris Brezillon'
> > Cc: linux-...@lists.infradead.org; marek.va...@g
On Thu, 4 Oct 2018 12:07:17 +
Yogesh Narayan Gaur wrote:
> Hi Boris,
>
> > -Original Message-
> > From: Yogesh Narayan Gaur
> > Sent: Thursday, October 4, 2018 2:56 PM
> > To: 'Boris Brezillon'
> > Cc: linux-...@lists.infradead.org; marek.va...@g
On Thu, 4 Oct 2018 16:42:22 +0530
Vignesh R wrote:
> On Thursday 04 October 2018 03:15 PM, Boris Brezillon wrote:
> > On Wed, 3 Oct 2018 22:26:01 +0530
> > Vignesh R wrote:
> >
> >> Micron's mt35xu512aba flash is an Octal flash that has x8 IO lines. It
>
On Thu, 4 Oct 2018 16:42:22 +0530
Vignesh R wrote:
> On Thursday 04 October 2018 03:15 PM, Boris Brezillon wrote:
> > On Wed, 3 Oct 2018 22:26:01 +0530
> > Vignesh R wrote:
> >
> >> Micron's mt35xu512aba flash is an Octal flash that has x8 IO lines. It
>
On Thu, 4 Oct 2018 16:05:36 +0530
Vignesh R wrote:
> >>
> >> .../devicetree/bindings/mtd/cadence-quadspi.txt | 1 +
> >> drivers/mtd/spi-nor/cadence-quadspi.c | 9 +
> >
> > On a slightly different topic, do you plan to convert the Cadence
> > driver to
On Thu, 4 Oct 2018 16:05:36 +0530
Vignesh R wrote:
> >>
> >> .../devicetree/bindings/mtd/cadence-quadspi.txt | 1 +
> >> drivers/mtd/spi-nor/cadence-quadspi.c | 9 +
> >
> > On a slightly different topic, do you plan to convert the Cadence
> > driver to
On Wed, 3 Oct 2018 22:26:01 +0530
Vignesh R wrote:
> Micron's mt35xu512aba flash is an Octal flash that has x8 IO lines. It
> supports read/write over 8 IO lines simulatenously. Add support for
> Octal read mode for Micron mt35xu512aba.
> Unfortunately, this flash is only complaint to SFDP
On Wed, 3 Oct 2018 22:26:01 +0530
Vignesh R wrote:
> Micron's mt35xu512aba flash is an Octal flash that has x8 IO lines. It
> supports read/write over 8 IO lines simulatenously. Add support for
> Octal read mode for Micron mt35xu512aba.
> Unfortunately, this flash is only complaint to SFDP
On Thu, 4 Oct 2018 09:24:57 +
Yogesh Narayan Gaur wrote:
> Hi Boris,
>
> > -Original Message-
> > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > Sent: Thursday, October 4, 2018 2:48 PM
> > To: Yogesh Narayan Gaur
> > Cc: lin
On Thu, 4 Oct 2018 09:24:57 +
Yogesh Narayan Gaur wrote:
> Hi Boris,
>
> > -Original Message-
> > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > Sent: Thursday, October 4, 2018 2:48 PM
> > To: Yogesh Narayan Gaur
> > Cc: lin
On Thu, 4 Oct 2018 09:14:36 +
Yogesh Narayan Gaur wrote:
> Hi Boris,
>
> > -Original Message-
> > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > Sent: Thursday, October 4, 2018 2:35 PM
> > To: Yogesh Narayan Gaur
> > Cc: lin
On Thu, 4 Oct 2018 09:14:36 +
Yogesh Narayan Gaur wrote:
> Hi Boris,
>
> > -Original Message-
> > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > Sent: Thursday, October 4, 2018 2:35 PM
> > To: Yogesh Narayan Gaur
> > Cc: lin
On Thu, 4 Oct 2018 14:18:40 +0530
Yogesh Gaur wrote:
> Flash mt35xu512aba connected to FlexSPI controller supports
> 1-1-8 protocol.
> Added flag spi-rx-bus-width and spi-tx-bus-width with values as
> 8 and 1 respectively for both flashes connected at CS0 and CS1.
>
> Signed-off-by: Yogesh
On Thu, 4 Oct 2018 14:18:40 +0530
Yogesh Gaur wrote:
> Flash mt35xu512aba connected to FlexSPI controller supports
> 1-1-8 protocol.
> Added flag spi-rx-bus-width and spi-tx-bus-width with values as
> 8 and 1 respectively for both flashes connected at CS0 and CS1.
>
> Signed-off-by: Yogesh
On Thu, 4 Oct 2018 14:18:38 +0530
Yogesh Gaur wrote:
> Add support for octal mode data transfer for Micron mt35xu512aba.
>
> Unfortunately, this flash is only complaint to SFDP JESD216B and does
> not seem to support newer JESD216C standard that provides auto detection
> of Octal mode
On Thu, 4 Oct 2018 14:18:38 +0530
Yogesh Gaur wrote:
> Add support for octal mode data transfer for Micron mt35xu512aba.
>
> Unfortunately, this flash is only complaint to SFDP JESD216B and does
> not seem to support newer JESD216C standard that provides auto detection
> of Octal mode
On Thu, 4 Oct 2018 08:47:33 +
Yogesh Narayan Gaur wrote:
> >
> > Yogesh, you already sent "spi: add flags for octal I/O data
> > transfer" [3] which is only adding the new OCTAL flags but is not
> > patching spi.c and spi-mem.c to take those new flags into account.
> > Here is my version of
On Thu, 4 Oct 2018 08:47:33 +
Yogesh Narayan Gaur wrote:
> >
> > Yogesh, you already sent "spi: add flags for octal I/O data
> > transfer" [3] which is only adding the new OCTAL flags but is not
> > patching spi.c and spi-mem.c to take those new flags into account.
> > Here is my version of
Hi Yogesh,
On Thu, 4 Oct 2018 14:18:37 +0530
Yogesh Gaur wrote:
> Add flags for Octal I/O data transfer
> Required for the SPI controller which can do the data transfer (TX/RX)
> on 8 data lines e.g. NXP FlexSPI controller.
> SPI_TX_OCTAL: transmit with 8 wires
> SPI_RX_OCTAL: receive with 8
Hi Yogesh,
On Thu, 4 Oct 2018 14:18:37 +0530
Yogesh Gaur wrote:
> Add flags for Octal I/O data transfer
> Required for the SPI controller which can do the data transfer (TX/RX)
> on 8 data lines e.g. NXP FlexSPI controller.
> SPI_TX_OCTAL: transmit with 8 wires
> SPI_RX_OCTAL: receive with 8
+Julien, Zhengxunli and Mason from Macronix
Hi Yogesh,
On Thu, 4 Oct 2018 06:51:41 +
Yogesh Narayan Gaur wrote:
> Hi Vignesh,
>
> > -Original Message-
> > From: Vignesh R [mailto:vigne...@ti.com]
> > Sent: Wednesday, October 3, 2018 10:26 PM
> > To:
+Julien, Zhengxunli and Mason from Macronix
Hi Yogesh,
On Thu, 4 Oct 2018 06:51:41 +
Yogesh Narayan Gaur wrote:
> Hi Vignesh,
>
> > -Original Message-
> > From: Vignesh R [mailto:vigne...@ti.com]
> > Sent: Wednesday, October 3, 2018 10:26 PM
> > To:
On Thu, 4 Oct 2018 00:14:15 +0200
Boris Brezillon wrote:
> On Wed, 3 Oct 2018 23:53:27 +0200
> Ricardo Ribalda Delgado wrote:
>
> > Hi Boris
> > On Wed, Oct 3, 2018 at 11:27 PM Boris Brezillon
> > wrote:
> > >
> > > On Wed, 3 Oct 2018 21:38:
On Thu, 4 Oct 2018 00:14:15 +0200
Boris Brezillon wrote:
> On Wed, 3 Oct 2018 23:53:27 +0200
> Ricardo Ribalda Delgado wrote:
>
> > Hi Boris
> > On Wed, Oct 3, 2018 at 11:27 PM Boris Brezillon
> > wrote:
> > >
> > > On Wed, 3 Oct 2018 21:38:
On Wed, 3 Oct 2018 23:53:27 +0200
Ricardo Ribalda Delgado wrote:
> Hi Boris
> On Wed, Oct 3, 2018 at 11:27 PM Boris Brezillon
> wrote:
> >
> > On Wed, 3 Oct 2018 21:38:58 +0200
> > Ricardo Ribalda Delgado wrote:
> >
> > > Add documentation for gp
On Wed, 3 Oct 2018 23:53:27 +0200
Ricardo Ribalda Delgado wrote:
> Hi Boris
> On Wed, Oct 3, 2018 at 11:27 PM Boris Brezillon
> wrote:
> >
> > On Wed, 3 Oct 2018 21:38:58 +0200
> > Ricardo Ribalda Delgado wrote:
> >
> > > Add documentation for gp
On Wed, 3 Oct 2018 21:38:58 +0200
Ricardo Ribalda Delgado wrote:
> Add documentation for gpio-addr-flash. This binding allow creating
> flash devices that are paged using GPIOs.
>
> Cc: devicet...@vger.kernel.org
> Reviewed-by: Rob Herring
> Signed-off-by: Ricardo Ribalda Delgado
> ---
>
On Wed, 3 Oct 2018 21:38:58 +0200
Ricardo Ribalda Delgado wrote:
> Add documentation for gpio-addr-flash. This binding allow creating
> flash devices that are paged using GPIOs.
>
> Cc: devicet...@vger.kernel.org
> Reviewed-by: Rob Herring
> Signed-off-by: Ricardo Ribalda Delgado
> ---
>
On Wed, 3 Oct 2018 21:38:59 +0200
Ricardo Ribalda Delgado wrote:
> Allow creating gpio-addr-flash via device-tree and not just via platform
> data.
>
> Option parsing has been moved to separated functions.
>
> Signed-off-by: Ricardo Ribalda Delgado
> ---
> drivers/mtd/maps/gpio-addr-flash.c
On Wed, 3 Oct 2018 21:38:59 +0200
Ricardo Ribalda Delgado wrote:
> Allow creating gpio-addr-flash via device-tree and not just via platform
> data.
>
> Option parsing has been moved to separated functions.
>
> Signed-off-by: Ricardo Ribalda Delgado
> ---
> drivers/mtd/maps/gpio-addr-flash.c
On Wed, 3 Oct 2018 21:38:58 +0200
Ricardo Ribalda Delgado wrote:
> Add documentation for gpio-addr-flash. This binding allow creating
> flash devices that are paged using GPIOs.
>
> Cc: devicet...@vger.kernel.org
> Reviewed-by: Rob Herring
> Signed-off-by: Ricardo Ribalda Delgado
> ---
>
On Wed, 3 Oct 2018 21:38:58 +0200
Ricardo Ribalda Delgado wrote:
> Add documentation for gpio-addr-flash. This binding allow creating
> flash devices that are paged using GPIOs.
>
> Cc: devicet...@vger.kernel.org
> Reviewed-by: Rob Herring
> Signed-off-by: Ricardo Ribalda Delgado
> ---
>
On Tue, 25 Sep 2018 17:50:31 +0530
Naga Sureshkumar Relli wrote:
> +static int anfc_zero_len_page_write_type_exec(struct nand_chip *chip,
> + const struct nand_subop *subop)
> +{
> + const struct nand_op_instr *instr;
> + struct anfc_nand_chip
On Tue, 25 Sep 2018 17:50:31 +0530
Naga Sureshkumar Relli wrote:
> +static int anfc_zero_len_page_write_type_exec(struct nand_chip *chip,
> + const struct nand_subop *subop)
> +{
> + const struct nand_op_instr *instr;
> + struct anfc_nand_chip
Hi Naga,
On Tue, 25 Sep 2018 17:50:31 +0530
Naga Sureshkumar Relli wrote:
> +static int anfc_read_param_get_feature_sp_read_type_exec(struct nand_chip
> *chip,
> + const struct nand_subop
> +
Hi Naga,
On Tue, 25 Sep 2018 17:50:31 +0530
Naga Sureshkumar Relli wrote:
> +static int anfc_read_param_get_feature_sp_read_type_exec(struct nand_chip
> *chip,
> + const struct nand_subop
> +
mode: sdr timing mode value
@mode: ONFI timing mode
> */
> struct nand_sdr_timings {
> u64 tBERS_max;
> @@ -763,6 +764,7 @@ struct nand_sdr_timings {
> u32 tWHR_min;
> u32 tWP_min;
> u32 tWW_min;
> + u8 mode;
> };
>
> /**
With this addressed, you can add
Reviewed-by: Boris Brezillon
mode: sdr timing mode value
@mode: ONFI timing mode
> */
> struct nand_sdr_timings {
> u64 tBERS_max;
> @@ -763,6 +764,7 @@ struct nand_sdr_timings {
> u32 tWHR_min;
> u32 tWP_min;
> u32 tWW_min;
> + u8 mode;
> };
>
> /**
With this addressed, you can add
Reviewed-by: Boris Brezillon
On Wed, 3 Oct 2018 22:26:00 +0530
Vignesh R wrote:
> This series adds support for octal mode of mt35x flash. Also, adds
> support for OSPI version of Cadence QSPI controller.
>
> Based on top of patches adding basic support for mt35xu512aba here:
> https://patchwork.ozlabs.org/cover/971437/
>
On Wed, 3 Oct 2018 22:26:00 +0530
Vignesh R wrote:
> This series adds support for octal mode of mt35x flash. Also, adds
> support for OSPI version of Cadence QSPI controller.
>
> Based on top of patches adding basic support for mt35xu512aba here:
> https://patchwork.ozlabs.org/cover/971437/
>
On Mon, 1 Oct 2018 14:43:51 +0200
Ricardo Ribalda Delgado wrote:
> +static int gpio_flash_probe_gpios(struct platform_device *pdev,
> + struct async_state *state)
> +{
> + struct physmap_flash_data *pdata;
> + struct device_node *dn;
> + struct resource
On Mon, 1 Oct 2018 14:43:51 +0200
Ricardo Ribalda Delgado wrote:
> +static int gpio_flash_probe_gpios(struct platform_device *pdev,
> + struct async_state *state)
> +{
> + struct physmap_flash_data *pdata;
> + struct device_node *dn;
> + struct resource
Hi Ricardo,
On Wed, 3 Oct 2018 17:56:03 +0200
Ricardo Ribalda Delgado wrote:
> Hi Boris
> On Wed, Oct 3, 2018 at 5:17 PM Boris Brezillon
> wrote:
> >
> > On Wed, 3 Oct 2018 17:11:14 +0200
> > Boris Brezillon wrote:
> >
> > > Hi Ricardo,
>
Hi Ricardo,
On Wed, 3 Oct 2018 17:56:03 +0200
Ricardo Ribalda Delgado wrote:
> Hi Boris
> On Wed, Oct 3, 2018 at 5:17 PM Boris Brezillon
> wrote:
> >
> > On Wed, 3 Oct 2018 17:11:14 +0200
> > Boris Brezillon wrote:
> >
> > > Hi Ricardo,
>
On Wed, 3 Oct 2018 17:11:14 +0200
Boris Brezillon wrote:
> Hi Ricardo,
>
> On Mon, 1 Oct 2018 14:43:49 +0200
> Ricardo Ribalda Delgado wrote:
>
> > @@ -248,14 +252,19 @@ static int gpio_flash_probe(struct platform_device
> > *pdev)
>
On Wed, 3 Oct 2018 17:11:14 +0200
Boris Brezillon wrote:
> Hi Ricardo,
>
> On Mon, 1 Oct 2018 14:43:49 +0200
> Ricardo Ribalda Delgado wrote:
>
> > @@ -248,14 +252,19 @@ static int gpio_flash_probe(struct platform_device
> > *pdev)
>
Hi Ricardo,
On Mon, 1 Oct 2018 14:43:49 +0200
Ricardo Ribalda Delgado wrote:
> @@ -248,14 +252,19 @@ static int gpio_flash_probe(struct platform_device
> *pdev)
>
> i = 0;
> do {
> - if (devm_gpio_request(>dev, state->gpio_addrs[i],
> -
Hi Ricardo,
On Mon, 1 Oct 2018 14:43:49 +0200
Ricardo Ribalda Delgado wrote:
> @@ -248,14 +252,19 @@ static int gpio_flash_probe(struct platform_device
> *pdev)
>
> i = 0;
> do {
> - if (devm_gpio_request(>dev, state->gpio_addrs[i],
> -
On Wed, 03 Oct 2018 15:55:25 +0200
Janusz Krzysztofik wrote:
> > >
> > > Implementation of NAND_OP_WAITRDY_INSTR has been based on legacy
> > > nand_wait_ready(),
> >
> > I don't remember what the ams-delta ->dev_ready()/->waitfunc() hooks
> > are doing, but is shouldn't be too hard to
On Wed, 03 Oct 2018 15:55:25 +0200
Janusz Krzysztofik wrote:
> > >
> > > Implementation of NAND_OP_WAITRDY_INSTR has been based on legacy
> > > nand_wait_ready(),
> >
> > I don't remember what the ams-delta ->dev_ready()/->waitfunc() hooks
> > are doing, but is shouldn't be too hard to
ams_delta
private struct so that this driver no longer uses the ->IO_ADDR_R/W
fields?
>
> Suggested-by: Boris Brezillon
> Signed-off-by: Janusz Krzysztofik
> ---
> Hi,
>
> I've not tested the change on hardware yet as I'm not sure if:
> - handling of NCE limited to that insi
ams_delta
private struct so that this driver no longer uses the ->IO_ADDR_R/W
fields?
>
> Suggested-by: Boris Brezillon
> Signed-off-by: Janusz Krzysztofik
> ---
> Hi,
>
> I've not tested the change on hardware yet as I'm not sure if:
> - handling of NCE limited to that insi
On Wed, 13 Jun 2018 11:38:12 +0530
Yogesh Gaur wrote:
> Some SPI controllers can't write nor->page_size bytes in a single
> step because their TX FIFO is too small.
>
> Allow nor->write() to return a size that is smaller than the requested
> write size to gracefully handle this case.
>
>
On Wed, 13 Jun 2018 11:38:12 +0530
Yogesh Gaur wrote:
> Some SPI controllers can't write nor->page_size bytes in a single
> step because their TX FIFO is too small.
>
> Allow nor->write() to return a size that is smaller than the requested
> write size to gracefully handle this case.
>
>
On Wed, 13 Jun 2018 11:39:18 +0530
Yogesh Gaur wrote:
> Some SPI controllers can't write nor->page_size bytes in a single step
> because their TX FIFO is too small, but when that happens we should
> make sure a WRITE_EN command before each write access and READ_SR command
> after each write
On Wed, 13 Jun 2018 11:39:18 +0530
Yogesh Gaur wrote:
> Some SPI controllers can't write nor->page_size bytes in a single step
> because their TX FIFO is too small, but when that happens we should
> make sure a WRITE_EN command before each write access and READ_SR command
> after each write
3] was suggested
> as a counter-implementation.
> (https://lore.kernel.org/patchwork/patch/983055/)
>
> The default value 8 was chosen to match to the boot ROM of the UniPhier
> platform. The preferred value may vary by platform. If so, please
> trade up to a different solution.
3] was suggested
> as a counter-implementation.
> (https://lore.kernel.org/patchwork/patch/983055/)
>
> The default value 8 was chosen to match to the boot ROM of the UniPhier
> platform. The preferred value may vary by platform. If so, please
> trade up to a different solution.
On Mon, 1 Oct 2018 14:10:03 +0200
Ricardo Ribalda Delgado wrote:
> > > + return;
> > > +
> > > + for (i = 0; i < state->gpio_count; i++) {
> > > + if ((ofs & BIT(i)) == (state->gpio_values & BIT(i)))
> >
> > Parens around the xx & BIT(i) operations are unneeded.
>
On Mon, 1 Oct 2018 14:10:03 +0200
Ricardo Ribalda Delgado wrote:
> > > + return;
> > > +
> > > + for (i = 0; i < state->gpio_count; i++) {
> > > + if ((ofs & BIT(i)) == (state->gpio_values & BIT(i)))
> >
> > Parens around the xx & BIT(i) operations are unneeded.
>
On Mon, 1 Oct 2018 11:58:49 +0200
Ricardo Ribalda Delgado wrote:
> Hi Boris
>
> PLEASE do not apply this one!
Okay, should I wait for a v6 of the whole series, or do you still want
me to apply patches 1 to 5?
On Mon, 1 Oct 2018 11:58:49 +0200
Ricardo Ribalda Delgado wrote:
> Hi Boris
>
> PLEASE do not apply this one!
Okay, should I wait for a v6 of the whole series, or do you still want
me to apply patches 1 to 5?
On Mon, 1 Oct 2018 09:02:32 +
Yogesh Narayan Gaur wrote:
> > > static void fspi_writel(struct nxp_fspi *f, u32 val, void __iomem
> > > *addr) {
> > > if (f->big_endian)
> > > iowrite32be(val, addr);
> > > else
> > > iowrite32(val, addr);
> > > }
> > >
> > >
> > >
On Mon, 1 Oct 2018 09:02:32 +
Yogesh Narayan Gaur wrote:
> > > static void fspi_writel(struct nxp_fspi *f, u32 val, void __iomem
> > > *addr) {
> > > if (f->big_endian)
> > > iowrite32be(val, addr);
> > > else
> > > iowrite32(val, addr);
> > > }
> > >
> > >
> > >
On Sun, 30 Sep 2018 12:37:38 +0200
Esben Haabendal wrote:
> Boris Brezillon writes:
>
> > On Sun, 30 Sep 2018 10:10:14 +
> > Chuanhua Han wrote:
> >
> >> > -Original Message-
> >> > From: Boris Brezillon
> >> > Sen
On Sun, 30 Sep 2018 12:37:38 +0200
Esben Haabendal wrote:
> Boris Brezillon writes:
>
> > On Sun, 30 Sep 2018 10:10:14 +
> > Chuanhua Han wrote:
> >
> >> > -Original Message-
> >> > From: Boris Brezillon
> >> > Sen
On Sun, 30 Sep 2018 10:18:18 +
Chuanhua Han wrote:
> > -Original Message-
> > From: Boris Brezillon
> > Sent: 2018年9月30日 18:04
> > To: Chuanhua Han
> > Cc: broo...@kernel.org; linux-...@vger.kernel.org;
> > linux-kernel@vger.kernel.org; e...@dei
On Sun, 30 Sep 2018 10:18:18 +
Chuanhua Han wrote:
> > -Original Message-
> > From: Boris Brezillon
> > Sent: 2018年9月30日 18:04
> > To: Chuanhua Han
> > Cc: broo...@kernel.org; linux-...@vger.kernel.org;
> > linux-kernel@vger.kernel.org; e...@dei
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