[PATCH] reset: socfpga: add an early reset driver for SoCFPGA

Create a separate reset driver that uses the reset operations in reset-simple. The reset driver for the SoCFPGA platform needs to register early in order to be able bring online timers that needed early in the kernel bootup. Signed-off-by: Dinh Nguyen --- arch/arm/mach-socfpga/socfpga.c | 4

[RFC] reset: make reset controller driver initialize early

Hi Philipp, I need to make the reset controller on the SoCFPGA platform initialize early. I have one solution which is similar to what reset-sunxi is doing, making the "altr,rst-mgr" initialize early in a separate reset-socfpga.c but using the reset-simple operations. I'm guessing SoCFPGA may

[RFC] reset: make reset controller driver initialize early

Hi Philipp, I need to make the reset controller on the SoCFPGA platform initialize early. I have one solution which is similar to what reset-sunxi is doing, making the "altr,rst-mgr" initialize early in a separate reset-socfpga.c but using the reset-simple operations. I'm guessing SoCFPGA may

Re: [PATCH] ARM: dts: socfpga: use stdout-path for chosen node

On 08/08/2018 04:09 AM, Simon Goldschmidt wrote: > Use stdout-path dts property for kernel console. > > There were two socfpga boards left not using stdout-path: > socrates and vining. Make sure they match the other boards. > > Signed-off-by: Simon Goldschmidt > --- >

Re: [PATCH] ARM: dts: socfpga: use stdout-path for chosen node

On 08/08/2018 04:09 AM, Simon Goldschmidt wrote: > Use stdout-path dts property for kernel console. > > There were two socfpga boards left not using stdout-path: > socrates and vining. Make sure they match the other boards. > > Signed-off-by: Simon Goldschmidt > --- >

Re: [PATCH] arm64: dts: stratix10: i2c clock running out of spec

On 08/08/2018 10:42 AM, Alan Tull wrote: > DesignWare I2C controller was observed running at 105.93kHz rather > than the specified 100kHz. Adjust device tree settings to bring it > within spec (a slightly conservative 98 MHz). > > Signed-off-by: Alan Tull > --- >

Re: [PATCH] arm64: dts: stratix10: i2c clock running out of spec

On 08/08/2018 10:42 AM, Alan Tull wrote: > DesignWare I2C controller was observed running at 105.93kHz rather > than the specified 100kHz. Adjust device tree settings to bring it > within spec (a slightly conservative 98 MHz). > > Signed-off-by: Alan Tull > --- >

Re: [PATCH] arm: dts: socfpga: denali needs nand_x_clk too

On 07/01/2018 08:35 PM, Masahiro Yamada wrote: > Hi Dinh, > > 2018-06-27 23:55 GMT+09:00 Dinh Nguyen : >> Hi Masahiro, >> >> On 06/26/2018 09:52 PM, Masahiro Yamada wrote: >>> 2018-06-27 3:09 GMT+09:00 Miquel Raynal : >>>> Hi Masahiro, >&g

Re: [PATCH] arm: dts: socfpga: denali needs nand_x_clk too

On 07/01/2018 08:35 PM, Masahiro Yamada wrote: > Hi Dinh, > > 2018-06-27 23:55 GMT+09:00 Dinh Nguyen : >> Hi Masahiro, >> >> On 06/26/2018 09:52 PM, Masahiro Yamada wrote: >>> 2018-06-27 3:09 GMT+09:00 Miquel Raynal : >>>> Hi Masahiro, >&g

Re: [PATCH] arm: dts: socfpga: denali needs nand_x_clk too

Hi Masahiro, On 06/26/2018 09:52 PM, Masahiro Yamada wrote: > 2018-06-27 3:09 GMT+09:00 Miquel Raynal : >> Hi Masahiro, >> >> On Tue, 26 Jun 2018 11:38:21 +0900, Masahiro Yamada >> wrote: >> >>> 2018-06-25 23:55 GMT+09:00 Boris Brezillon : >>>&g

Re: [PATCH] arm: dts: socfpga: denali needs nand_x_clk too

Hi Masahiro, On 06/26/2018 09:52 PM, Masahiro Yamada wrote: > 2018-06-27 3:09 GMT+09:00 Miquel Raynal : >> Hi Masahiro, >> >> On Tue, 26 Jun 2018 11:38:21 +0900, Masahiro Yamada >> wrote: >> >>> 2018-06-25 23:55 GMT+09:00 Boris Brezillon : >>>&g

Re: [PATCH] arm: dts: socfpga: denali needs nand_x_clk too

On 06/22/2018 10:58 AM, Richard Weinberger wrote: > Masahiro, > > Am Freitag, 22. Juni 2018, 16:37:21 CEST schrieb Masahiro Yamada: >> Hi Richard, >> >> >> 2018-06-19 21:07 GMT+09:00 Richard Weinberger : >>> The denali NAND flash controller needs at least two clocks to operate, >>> nand_clk

Re: [PATCH] arm: dts: socfpga: denali needs nand_x_clk too

On 06/22/2018 10:58 AM, Richard Weinberger wrote: > Masahiro, > > Am Freitag, 22. Juni 2018, 16:37:21 CEST schrieb Masahiro Yamada: >> Hi Richard, >> >> >> 2018-06-19 21:07 GMT+09:00 Richard Weinberger : >>> The denali NAND flash controller needs at least two clocks to operate, >>> nand_clk

Re: [PATCHv3] arm64: dts: stratix10: Add QSPI support for Stratix10

On 05/15/2018 05:26 PM, thor.tha...@linux.intel.com wrote: > From: Thor Thayer > > Add qspi_clock >The qspi_clk frequency is updated by U-Boot before starting Linux. > Add QSPI interface node. > Add QSPI flash memory child node. >Setup the QSPI memory in 2

Re: [PATCHv3] arm64: dts: stratix10: Add QSPI support for Stratix10

On 05/15/2018 05:26 PM, thor.tha...@linux.intel.com wrote: > From: Thor Thayer > > Add qspi_clock >The qspi_clk frequency is updated by U-Boot before starting Linux. > Add QSPI interface node. > Add QSPI flash memory child node. >Setup the QSPI memory in 2 partitions. > >

Re: [PATCHv2] arm64: dts: stratix10: Add QSPI support for Stratix10

On 05/11/2018 11:10 AM, thor.tha...@linux.intel.com wrote: > From: Thor Thayer > > Add qspi_clock >The qspi_clk frequency is updated by U-Boot before starting Linux. > Add QSPI interface node. > Add QSPI flash memory child node. >Setup the QSPI memory in 2

Re: [PATCHv2] arm64: dts: stratix10: Add QSPI support for Stratix10

On 05/11/2018 11:10 AM, thor.tha...@linux.intel.com wrote: > From: Thor Thayer > > Add qspi_clock >The qspi_clk frequency is updated by U-Boot before starting Linux. > Add QSPI interface node. > Add QSPI flash memory child node. >Setup the QSPI memory in 2 partitions. > >

[PATCH 2/2] clk: socfpga: stratix10: suppress unbinding platform's clock driver

The Stratix10 clock driver is essential to system operation, so their removal should never happen. Signed-off-by: Dinh Nguyen <dingu...@kernel.org> --- drivers/clk/socfpga/clk-s10.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/socfpga/clk-s10.c b/drivers/clk/socfpga/clk

[PATCH 2/2] clk: socfpga: stratix10: suppress unbinding platform's clock driver

The Stratix10 clock driver is essential to system operation, so their removal should never happen. Signed-off-by: Dinh Nguyen --- drivers/clk/socfpga/clk-s10.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/socfpga/clk-s10.c b/drivers/clk/socfpga/clk-s10.c index c788997

[PATCH 1/2] clk: socfpga: stratix10: use platform driver APIs

Use platform driver APIs to map memory so that it will automatically free the memory in case of errors. Signed-off-by: Dinh Nguyen <dingu...@kernel.org> --- drivers/clk/socfpga/clk-s10.c | 35 +++ 1 file changed, 15 insertions(+), 20 deletions(-) diff

[PATCH 1/2] clk: socfpga: stratix10: use platform driver APIs

Use platform driver APIs to map memory so that it will automatically free the memory in case of errors. Signed-off-by: Dinh Nguyen --- drivers/clk/socfpga/clk-s10.c | 35 +++ 1 file changed, 15 insertions(+), 20 deletions(-) diff --git a/drivers/clk/socfpga/clk

Re: [PATCH] arm64: dts: stratix10: Change pad skew values for EMAC0 PHY driver

On 04/23/2018 10:01 PM, Ooi, Joyce wrote: > The HPS EMAC0 drive strength is changed to 4mA because the initial 8mA > drive strength has caused CE test to fail. This requires changes on the > pad skew for EMAC0 PHY driver. Based on several measurements done, Tx > clock does not require the extra

Re: [PATCH] arm64: dts: stratix10: Change pad skew values for EMAC0 PHY driver

On 04/23/2018 10:01 PM, Ooi, Joyce wrote: > The HPS EMAC0 drive strength is changed to 4mA because the initial 8mA > drive strength has caused CE test to fail. This requires changes on the > pad skew for EMAC0 PHY driver. Based on several measurements done, Tx > clock does not require the extra

Re: [RESEND PATCH] ARM: dts: consistently use 'atmel' as at24 manufacturer in cyclone5

On 04/17/2018 04:45 AM, Bartosz Golaszewski wrote: > Using 'at' or 'at24' as the part of the compatible > string is now deprecated. Use a correct value: 'atmel,'. > > Signed-off-by: Bartosz Golaszewski > --- > arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts | 6 +++--- > 1

Re: [RESEND PATCH] ARM: dts: consistently use 'atmel' as at24 manufacturer in cyclone5

On 04/17/2018 04:45 AM, Bartosz Golaszewski wrote: > Using 'at' or 'at24' as the part of the compatible > string is now deprecated. Use a correct value: 'atmel,'. > > Signed-off-by: Bartosz Golaszewski > --- > arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts | 6 +++--- > 1 file changed, 3

Re: [PATCH] ARM: socfpga_defconfig: Remove QSPI Sector 4K size force

On 04/11/2018 10:20 AM, Thor Thayer wrote: > Hi. Any comments on this patch? > > On 03/26/2018 02:50 PM, thor.tha...@linux.intel.com wrote: >> From: Thor Thayer >> >> Remove QSPI Sector 4K size force which is causing QSPI boot >> problems with the JFFS2 root

Re: [PATCH] ARM: socfpga_defconfig: Remove QSPI Sector 4K size force

On 04/11/2018 10:20 AM, Thor Thayer wrote: > Hi. Any comments on this patch? > > On 03/26/2018 02:50 PM, thor.tha...@linux.intel.com wrote: >> From: Thor Thayer >> >> Remove QSPI Sector 4K size force which is causing QSPI boot >> problems with the JFFS2 root filesystem. >> >> Fixes the

Re: [PATCH] arm: dts: socfpga: fix GIC PPI warning

On 03/23/2018 04:22 AM, Philipp Puschmann wrote: > Fixes the warning "GIC: PPI13 is secure or misconfigured" by > changing the interrupt type from level_low to edge_raising > > Signed-off-by: Philipp Puschmann > --- > arch/arm/boot/dts/socfpga.dtsi | 2 +- > 1 file changed, 1

Re: [PATCH] arm: dts: socfpga: fix GIC PPI warning

On 03/23/2018 04:22 AM, Philipp Puschmann wrote: > Fixes the warning "GIC: PPI13 is secure or misconfigured" by > changing the interrupt type from level_low to edge_raising > > Signed-off-by: Philipp Puschmann > --- > arch/arm/boot/dts/socfpga.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1

Re: [PATCH 4/6] arm64: dts: stratix10: remove 'num-slots' property for dwmmc

4/boot/dts/altera/socfpga_stratix10_socdk.dts > @@ -88,7 +88,6 @@ > > { > status = "okay"; > - num-slots = <1>; > cap-sd-highspeed; > broken-cd; > bus-width = <4>; > Acked-by: Dinh Nguyen <dingu...@kernel.org>

Re: [PATCH 4/6] arm64: dts: stratix10: remove 'num-slots' property for dwmmc

ga_stratix10_socdk.dts > @@ -88,7 +88,6 @@ > > { > status = "okay"; > - num-slots = <1>; > cap-sd-highspeed; > broken-cd; > bus-width = <4>; > Acked-by: Dinh Nguyen

Re: [PATCH] arm64: dts: stratix10: Add PL330 DMAC to Stratix10 dts

On 02/20/2018 09:38 AM, Graham Moore wrote: > The Stratix10 SoCFPGA uses the PL330 DMAC. This patch adds the PL330 > DMAC to the Stratix10 device tree. > > Signed-off-by: Graham Moore > --- > arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 19

Re: [PATCH] arm64: dts: stratix10: Add PL330 DMAC to Stratix10 dts

On 02/20/2018 09:38 AM, Graham Moore wrote: > The Stratix10 SoCFPGA uses the PL330 DMAC. This patch adds the PL330 > DMAC to the Stratix10 device tree. > > Signed-off-by: Graham Moore > --- > arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 19 +++ > 1 file changed, 19

Re: [PATCH] arm64: dts: stratix10: enable i2c, add i2c periperals

Hi Alan, On 02/21/2018 02:25 PM, Alan Tull wrote: > Add clock for i2c > Enable i2c1 > Set the i2c bus speed to 100KHz > Add the following i2c peripherals > * ds1339 RTC > * 24c32 EEPROM > * max1619 temperature monitor > * ltc2497 ADC > * Add a fixed regulator for the ADC's Vref. > > This

Re: [PATCH] arm64: dts: stratix10: enable i2c, add i2c periperals

Hi Alan, On 02/21/2018 02:25 PM, Alan Tull wrote: > Add clock for i2c > Enable i2c1 > Set the i2c bus speed to 100KHz > Add the following i2c peripherals > * ds1339 RTC > * 24c32 EEPROM > * max1619 temperature monitor > * ltc2497 ADC > * Add a fixed regulator for the ADC's Vref. > > This

Re: [PATCH] ARM: dts: socfpga: add i2c reset signals

On 01/16/2018 03:29 AM, Steffen Trumtrar wrote: > From: Tim Sander > > Add the reset signals for the i2c controllers on Cyclone5-based > SoCFPGA boards to the dtsi. > > Signed-off-by: Tim Sander > Signed-off-by: Steffen Trumtrar

Re: [PATCH] ARM: dts: socfpga: add i2c reset signals

On 01/16/2018 03:29 AM, Steffen Trumtrar wrote: > From: Tim Sander > > Add the reset signals for the i2c controllers on Cyclone5-based > SoCFPGA boards to the dtsi. > > Signed-off-by: Tim Sander > Signed-off-by: Steffen Trumtrar > --- > arch/arm/boot/dts/socfpga.dtsi | 4 > 1 file

Re: [PATCH] arm64: dts: socfpga: add missing interrupt-parent

ent property so we can correct parse > that interrupt number. > > Signed-off-by: Arnd Bergmann <a...@arndb.de> > --- > If this looks ok, I'd apply it directly to the fixes branch > for 4.15, as the warning is one that was introduced in this > release. Acked-by: Dinh Nguyen

Re: [PATCH] arm64: dts: socfpga: add missing interrupt-parent

ent property so we can correct parse > that interrupt number. > > Signed-off-by: Arnd Bergmann > --- > If this looks ok, I'd apply it directly to the fixes branch > for 4.15, as the warning is one that was introduced in this > release. Acked-by: Dinh Nguyen Yes, please feel free to apply it. And thanks alot! Dinh

Re: [PATCH] usb: dwc2: add optional usb ecc reset bit

Hi John, was wondering if you have gotten a chance to review this? Thank, Dinh On 11/01/2017 10:34 AM, Dinh Nguyen wrote: > The dwc2 USB controller in Stratix10 has an additional ECC reset bit that > needs to get de-asserted in order for the controller to work properly. > > Signed-

Re: [PATCH] usb: dwc2: add optional usb ecc reset bit

Hi John, was wondering if you have gotten a chance to review this? Thank, Dinh On 11/01/2017 10:34 AM, Dinh Nguyen wrote: > The dwc2 USB controller in Stratix10 has an additional ECC reset bit that > needs to get de-asserted in order for the controller to work properly. > > Signed-

Re: Suspend to disk with usb connected fails to detect usb(reset) during resume

On 11/08/2017 06:29 AM, Ivid Suvarna wrote: > On Tue, Nov 7, 2017 at 9:19 PM, Alan Stern wrote: >> On Tue, 7 Nov 2017, Ivid Suvarna wrote: >> >>> Hi, >>> >>> I am trying to support suspend to disk(hibernate) on Hikey with 4.4 >>> kernel. During suspend, I could see

Re: Suspend to disk with usb connected fails to detect usb(reset) during resume

On 11/08/2017 06:29 AM, Ivid Suvarna wrote: > On Tue, Nov 7, 2017 at 9:19 PM, Alan Stern wrote: >> On Tue, 7 Nov 2017, Ivid Suvarna wrote: >> >>> Hi, >>> >>> I am trying to support suspend to disk(hibernate) on Hikey with 4.4 >>> kernel. During suspend, I could see the usb devices getting reset

[PATCH] usb: dwc2: add optional usb ecc reset bit

The dwc2 USB controller in Stratix10 has an additional ECC reset bit that needs to get de-asserted in order for the controller to work properly. Signed-off-by: Dinh Nguyen <dingu...@kernel.org> --- drivers/usb/dwc2/core.h | 1 + drivers/usb/dwc2/platform.c | 10 ++ 2 files c

[PATCH] usb: dwc2: add optional usb ecc reset bit

The dwc2 USB controller in Stratix10 has an additional ECC reset bit that needs to get de-asserted in order for the controller to work properly. Signed-off-by: Dinh Nguyen --- drivers/usb/dwc2/core.h | 1 + drivers/usb/dwc2/platform.c | 10 ++ 2 files changed, 11 insertions

[PATCH] usb: dwc2: disable erroneous overcurrent condition

the over-current condition. Signed-off-by: Dinh Nguyen <dingu...@kernel.org> --- drivers/usb/dwc2/core.h | 4 drivers/usb/dwc2/hcd.c| 5 + drivers/usb/dwc2/params.c | 3 +++ 3 files changed, 12 insertions(+) diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h index 83

[PATCH] usb: dwc2: disable erroneous overcurrent condition

the over-current condition. Signed-off-by: Dinh Nguyen --- drivers/usb/dwc2/core.h | 4 drivers/usb/dwc2/hcd.c| 5 + drivers/usb/dwc2/params.c | 3 +++ 3 files changed, 12 insertions(+) diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h index 8367d4f9..730d7eb 100644

Re: [PATCH 2/2] arm64: dts: stratix10: enable gpio and leds

On 10/10/2017 04:25 PM, Alan Tull wrote: > Enable gpio and leds for socdk OOBE daughtercard. > > pushbutton PB_SW0 = gpio1.io4 > pushbutton PB_SW1 = gpio1.io5 > LED HPS_LED0 = gpio1.io20 > LED HPS_LED1 = gpio1.io19 > LED HPS_LED2 = gpio1.io21 > > Signed-off-by: Alan Tull

Re: [PATCH 2/2] arm64: dts: stratix10: enable gpio and leds

On 10/10/2017 04:25 PM, Alan Tull wrote: > Enable gpio and leds for socdk OOBE daughtercard. > > pushbutton PB_SW0 = gpio1.io4 > pushbutton PB_SW1 = gpio1.io5 > LED HPS_LED0 = gpio1.io20 > LED HPS_LED1 = gpio1.io19 > LED HPS_LED2 = gpio1.io21 > > Signed-off-by: Alan Tull > ---

Re: [PATCH] reset: socfpga: fix for 64-bit compilation

On 10/04/2017 04:27 AM, Philipp Zabel wrote: > Hi Dinh, > > On Mon, 2017-10-02 at 16:36 -0500, Dinh Nguyen wrote: >> Gentle ping? > > Thank you, I've applied this patch to the reset/fixes branch. > thanks Philipp! Dinh

Re: [PATCH] reset: socfpga: fix for 64-bit compilation

On 10/04/2017 04:27 AM, Philipp Zabel wrote: > Hi Dinh, > > On Mon, 2017-10-02 at 16:36 -0500, Dinh Nguyen wrote: >> Gentle ping? > > Thank you, I've applied this patch to the reset/fixes branch. > thanks Philipp! Dinh

Re: [PATCH] reset: socfpga: fix for 64-bit compilation

Gentle ping? Dinh On 09/22/2017 01:42 PM, Dinh Nguyen wrote: > The SoCFPGA Stratix10 reset controller has 32-bit registers. Thus, we > cannot use BITS_PER_LONG in computing the register and bit offset. Instead, > we should be using the width of the hardware register for the ca

Re: [PATCH] reset: socfpga: fix for 64-bit compilation

Gentle ping? Dinh On 09/22/2017 01:42 PM, Dinh Nguyen wrote: > The SoCFPGA Stratix10 reset controller has 32-bit registers. Thus, we > cannot use BITS_PER_LONG in computing the register and bit offset. Instead, > we should be using the width of the hardware register for the ca

[PATCH] reset: socfpga: fix for 64-bit compilation

The SoCFPGA Stratix10 reset controller has 32-bit registers. Thus, we cannot use BITS_PER_LONG in computing the register and bit offset. Instead, we should be using the width of the hardware register for the calculation. Signed-off-by: Dinh Nguyen <dingu...@kernel.org> --- drivers/reset

[PATCH] reset: socfpga: fix for 64-bit compilation

The SoCFPGA Stratix10 reset controller has 32-bit registers. Thus, we cannot use BITS_PER_LONG in computing the register and bit offset. Instead, we should be using the width of the hardware register for the calculation. Signed-off-by: Dinh Nguyen --- drivers/reset/reset-socfpga.c | 17

[PATCH] reset: socfpga: build the reset-socfpga for Stratix10 SOC

Enable the reset driver to get built for the Stratix10 platform. Signed-off-by: Dinh Nguyen <dingu...@kernel.org> --- drivers/reset/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 608c071..ab8895b

[PATCH] reset: socfpga: build the reset-socfpga for Stratix10 SOC

Enable the reset driver to get built for the Stratix10 platform. Signed-off-by: Dinh Nguyen --- drivers/reset/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 608c071..ab8895b 100644 --- a/drivers/reset/Kconfig +++ b

Re: [PATCH v2 1/5] reset: add reset-simple to unify socfpga, stm32, sunxi, and zx2967

Hi Phillip, This patch is failing to apply on both v4.13-rc4 and linux-next: error: patch failed: drivers/reset/reset-sunxi.c:108 error: drivers/reset/reset-sunxi.c: patch does not apply Patch failed at 0001 reset: add reset-simple to unify socfpga, stm32, sunxi, and zx2967 On 08/11/2017 08:06

Re: [PATCH v2 1/5] reset: add reset-simple to unify socfpga, stm32, sunxi, and zx2967

Hi Phillip, This patch is failing to apply on both v4.13-rc4 and linux-next: error: patch failed: drivers/reset/reset-sunxi.c:108 error: drivers/reset/reset-sunxi.c: patch does not apply Patch failed at 0001 reset: add reset-simple to unify socfpga, stm32, sunxi, and zx2967 On 08/11/2017 08:06

[PATCHv2] clk: socfpga: Fix the smplsel on Arria10 and Stratix10

Signed-off-by: Dinh Nguyen <dingu...@kernel.org> --- v2: Add a Fixes tag --- drivers/clk/socfpga/clk-gate-a10.c | 2 +- drivers/clk/socfpga/clk.h | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/clk/socfpga/clk-gate-a10.c b/drivers/clk/socfpga/clk-gate-a10

[PATCHv2] clk: socfpga: Fix the smplsel on Arria10 and Stratix10

Signed-off-by: Dinh Nguyen --- v2: Add a Fixes tag --- drivers/clk/socfpga/clk-gate-a10.c | 2 +- drivers/clk/socfpga/clk.h | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/clk/socfpga/clk-gate-a10.c b/drivers/clk/socfpga/clk-gate-a10.c index c2d5727..3637

[PATCH] clk: socfpga: Fix the smplsel on Arria10 and Stratix10

The smplsel bits for the SDMMC clock on Arria10 and Stratix10 platforms are offset by 1 additional bit. Add a new macro SYSMGR_SDMMC_CTRL_SET_AS10 for usage on the Arria10 and Stratix10 platforms. Signed-off-by: Dinh Nguyen <dingu...@kernel.org> --- drivers/clk/socfpga/clk-gate-a10

[PATCH] clk: socfpga: Fix the smplsel on Arria10 and Stratix10

The smplsel bits for the SDMMC clock on Arria10 and Stratix10 platforms are offset by 1 additional bit. Add a new macro SYSMGR_SDMMC_CTRL_SET_AS10 for usage on the Arria10 and Stratix10 platforms. Signed-off-by: Dinh Nguyen --- drivers/clk/socfpga/clk-gate-a10.c | 2 +- drivers/clk/socfpga

Re: [PATCH] socfpga_a10: reset CPU1 in socfpga_cpu_kill()

On 05/10/2017 12:13 AM, yanjiang@windriver.com wrote: > From: Yanjiang Jin > > Kexec's second kernel would hang if CPU1 isn't reset. > Can you please be a bit more descriptive on the commit log? Is it because when kexec starts, the SMP on the kexec's kernel

Re: [PATCH] socfpga_a10: reset CPU1 in socfpga_cpu_kill()

On 05/10/2017 12:13 AM, yanjiang@windriver.com wrote: > From: Yanjiang Jin > > Kexec's second kernel would hang if CPU1 isn't reset. > Can you please be a bit more descriptive on the commit log? Is it because when kexec starts, the SMP on the kexec's kernel try to run on CPU1? >

Re: [PATCH v2] ARM: socfpga: updates for socfpga_defconfig

On 03/08/2017 11:49 PM, ho.jia@intel.com wrote: > From: Jia Jie Ho > > This patch enables Altera TSE support in socfpga_defconfig > > Signed-off-by: Jia Jie Ho > --- > v2: > * Adding the TSE support as a module for Arria10 > >

Re: [PATCH v2] ARM: socfpga: updates for socfpga_defconfig

On 03/08/2017 11:49 PM, ho.jia@intel.com wrote: > From: Jia Jie Ho > > This patch enables Altera TSE support in socfpga_defconfig > > Signed-off-by: Jia Jie Ho > --- > v2: > * Adding the TSE support as a module for Arria10 > > arch/arm/configs/socfpga_defconfig |1 + > 1 files

Re: [PATCHv2 5/5] ARM: dts: socfpga: Add Devkit A10-SR Reset Controller

On 02/22/2017 11:10 AM, thor.tha...@linux.intel.com wrote: > From: Thor Thayer <thor.tha...@linux.intel.com> > > Add the Altera Arria10 System Resource Reset Controller to the MFD > > Signed-off-by: Thor Thayer <thor.tha...@linux.intel.com> > Acked-by: Di

Re: [PATCHv2 5/5] ARM: dts: socfpga: Add Devkit A10-SR Reset Controller

On 02/22/2017 11:10 AM, thor.tha...@linux.intel.com wrote: > From: Thor Thayer > > Add the Altera Arria10 System Resource Reset Controller to the MFD > > Signed-off-by: Thor Thayer > Acked-by: Dinh Nguyen > --- > v2 change commit header to ARM: dts: socfpga. > --- Applied. Thanks, Dinh

Re: [PATCH 0/2] ARM: dts: socfpga: Add support for PMU on Arria5/Cyclone5

On 02/28/2017 09:52 AM, Florian Vaussard wrote: > Hi, > > These patches add suport for ARM Performance Monitor Units on Arria5 and > Cyclone5 SoCFPGA. This was tested on a Cyclone 5 SoC DK board. > > Side note: the same change can be probably applied to Arria10 as well, > but we do not have

Re: [PATCH 0/2] ARM: dts: socfpga: Add support for PMU on Arria5/Cyclone5

On 02/28/2017 09:52 AM, Florian Vaussard wrote: > Hi, > > These patches add suport for ARM Performance Monitor Units on Arria5 and > Cyclone5 SoCFPGA. This was tested on a Cyclone 5 SoC DK board. > > Side note: the same change can be probably applied to Arria10 as well, > but we do not have

Re: [PATCH 0/6] ARM: dts: socfpga: Fix dtc warnings

On 02/24/2017 11:54 PM, Florian Vaussard wrote: > We get a bunch of warnings when compiling the SoCFPGA device trees with W=1. > This warnings happens because some nodes have a unit name but no 'reg' > property, > or are missing a unit name while having a 'reg' property. This series enables >

Re: [PATCH 0/6] ARM: dts: socfpga: Fix dtc warnings

On 02/24/2017 11:54 PM, Florian Vaussard wrote: > We get a bunch of warnings when compiling the SoCFPGA device trees with W=1. > This warnings happens because some nodes have a unit name but no 'reg' > property, > or are missing a unit name while having a 'reg' property. This series enables >

Re: [PATCH 3/4] fpga dt: bindings for Altera Partial Reconfiguraion IP.

On Wed, Feb 15, 2017 at 3:10 PM, wrote: > From: Matthew Gerlach > > Device Tree bindings for Altera Partial Reconfiguraion IP? > > Signed-off-by: Matthew Gerlach > --- >

Re: [PATCH 3/4] fpga dt: bindings for Altera Partial Reconfiguraion IP.

On Wed, Feb 15, 2017 at 3:10 PM, wrote: > From: Matthew Gerlach > > Device Tree bindings for Altera Partial Reconfiguraion IP? > > Signed-off-by: Matthew Gerlach > --- > Documentation/devicetree/bindings/fpga/altera-pr-ip.txt | 12 > 1 file changed, 12 insertions(+) > create

Re: [PATCH 5/5] ARM: socfpga: dts: Add Devkit A10-SR Reset Controller

commit header as "ARM: dts: socfpga:" Otherwise, Acked-by: Dinh Nguyen <dingu...@kernel.org> Dinh

Re: [PATCH 5/5] ARM: socfpga: dts: Add Devkit A10-SR Reset Controller

On 02/15/2017 03:50 PM, thor.tha...@linux.intel.com wrote: > From: Thor Thayer > > Add the Altera Arria10 System Resource Reset Controller to the MFD > > Signed-off-by: Thor Thayer Nit: Please have the commit header as "ARM: dts: socfpga:" Otherwise, Acked-by: Dinh Nguyen Dinh

Re: [PATCH] reset-socfpga: Fix nr_resets property

On 02/15/2017 08:57 AM, Philipp Zabel wrote: > [Added Dinh to Cc:] > > On Wed, 2017-02-15 at 14:06 +0100, Rojhalat Ibrahim wrote: >> The SoC-FPGA reset controller driver defines NR_BANKS as 4 and uses that >> define >> for two unrelated purposes. It is used >> 1. as an increment for reset line

Re: [PATCH] reset-socfpga: Fix nr_resets property

On 02/15/2017 08:57 AM, Philipp Zabel wrote: > [Added Dinh to Cc:] > > On Wed, 2017-02-15 at 14:06 +0100, Rojhalat Ibrahim wrote: >> The SoC-FPGA reset controller driver defines NR_BANKS as 4 and uses that >> define >> for two unrelated purposes. It is used >> 1. as an increment for reset line

Re: [PATCHv2] ARM: dts: Add EMAC AXI settings for Arria10

On Thu, Feb 2, 2017 at 4:05 PM, wrote: > From: Thor Thayer > > Add the device tree entries needed to support the EMAC AXI > bus settings on the Arria10 SoCFPGA chip. > > Signed-off-by: Thor Thayer > --- > v2

Re: [PATCHv2] ARM: dts: Add EMAC AXI settings for Arria10

On Thu, Feb 2, 2017 at 4:05 PM, wrote: > From: Thor Thayer > > Add the device tree entries needed to support the EMAC AXI > bus settings on the Arria10 SoCFPGA chip. > > Signed-off-by: Thor Thayer > --- > v2 Add the AXI configuration to the other DW EMACs in the chip. > --- >

Re: [PATCH] ARM: dts: Add EMAC AXI settings for Arria10

On Thu, Feb 2, 2017 at 11:09 AM, wrote: > From: Thor Thayer > > Add the device tree entries needed to support the EMAC AXI > bus settings on the Arria10 SoCFPGA chip. > > Signed-off-by: Thor Thayer > --- >

Re: [PATCH] ARM: dts: Add EMAC AXI settings for Arria10

On Thu, Feb 2, 2017 at 11:09 AM, wrote: > From: Thor Thayer > > Add the device tree entries needed to support the EMAC AXI > bus settings on the Arria10 SoCFPGA chip. > > Signed-off-by: Thor Thayer > --- > arch/arm/boot/dts/socfpga_arria10.dtsi | 7 +++ > 1 file changed, 7 insertions(+) >

Re: [PATCH 39/39] mtd: nand: denali_dt: add compatible strings for UniPhier SoC variants

On 12/05/2016 03:29 PM, Marek Vasut wrote: > On 12/05/2016 09:51 PM, Dinh Nguyen wrote: >> On Sun, Dec 4, 2016 at 10:22 PM, Marek Vasut <marek.va...@gmail.com> wrote: >>> On 12/05/2016 05:10 AM, Masahiro Yamada wrote: >>>> Hi Marek, >>>> >>&g

Re: [PATCH 39/39] mtd: nand: denali_dt: add compatible strings for UniPhier SoC variants

On 12/05/2016 03:29 PM, Marek Vasut wrote: > On 12/05/2016 09:51 PM, Dinh Nguyen wrote: >> On Sun, Dec 4, 2016 at 10:22 PM, Marek Vasut wrote: >>> On 12/05/2016 05:10 AM, Masahiro Yamada wrote: >>>> Hi Marek, >>>> >>>> >>>> 201

Re: [PATCH 39/39] mtd: nand: denali_dt: add compatible strings for UniPhier SoC variants

mada wrote: >>>> Hi Dinh, >>>> >>>> >>>> 2016-12-04 7:08 GMT+09:00 Dinh Nguyen <dinh.li...@gmail.com>: >>>>> Hi, >>>>> >>>>> On Fri, Dec 2, 2016 at 8:49 PM, Marek Vasut <marek.va...@gmail.com&g

Re: [PATCH 39/39] mtd: nand: denali_dt: add compatible strings for UniPhier SoC variants

On Sun, Dec 4, 2016 at 10:22 PM, Marek Vasut wrote: > On 12/05/2016 05:10 AM, Masahiro Yamada wrote: >> Hi Marek, >> >> >> 2016-12-05 12:44 GMT+09:00 Marek Vasut : >>> On 12/05/2016 04:30 AM, Masahiro Yamada wrote: >>>> Hi Dinh, >>>>

Re: [PATCH 39/39] mtd: nand: denali_dt: add compatible strings for UniPhier SoC variants

Hi, On Fri, Dec 2, 2016 at 8:49 PM, Marek Vasut wrote: > On 12/03/2016 03:41 AM, Masahiro Yamada wrote: >> Hi Rob, > > Hi! > >> 2016-12-03 1:26 GMT+09:00 Rob Herring : >> (Plan A) "denali,socfpga-nand" (for Altera SOCFPGA

Re: [PATCH 39/39] mtd: nand: denali_dt: add compatible strings for UniPhier SoC variants

Hi, On Fri, Dec 2, 2016 at 8:49 PM, Marek Vasut wrote: > On 12/03/2016 03:41 AM, Masahiro Yamada wrote: >> Hi Rob, > > Hi! > >> 2016-12-03 1:26 GMT+09:00 Rob Herring : >> (Plan A) "denali,socfpga-nand" (for Altera SOCFPGA variant) "denali,uniphier-nand-v1"

[PATCH] fpga: fix sparse warnings in fpga-mgr and fpga-bridge

Fix up these sparse warnings: drivers/fpga/fpga-mgr.c:189:21: warning: symbol '__fpga_mgr_get' was not declared. Should it be static? drivers/fpga/fpga-bridge.c:30:12: warning: symbol 'bridge_list_lock' was not declared. Should it be static? Signed-off-by: Dinh Nguyen <dingu...@kernel.

[PATCH] fpga: fix sparse warnings in fpga-mgr and fpga-bridge

Fix up these sparse warnings: drivers/fpga/fpga-mgr.c:189:21: warning: symbol '__fpga_mgr_get' was not declared. Should it be static? drivers/fpga/fpga-bridge.c:30:12: warning: symbol 'bridge_list_lock' was not declared. Should it be static? Signed-off-by: Dinh Nguyen --- drivers/fpga/fpga

Re: [PATCH] ARM: socfpga: fix spelling mistake in error message

On Mon, Nov 14, 2016 at 5:04 PM, Colin King wrote: > From: Colin Ian King > > Trivial fix to spelling mistake "Mananger" to "Manager" > in error message > > Signed-off-by: Colin Ian King > --- >

Re: [PATCH] ARM: socfpga: fix spelling mistake in error message

On Mon, Nov 14, 2016 at 5:04 PM, Colin King wrote: > From: Colin Ian King > > Trivial fix to spelling mistake "Mananger" to "Manager" > in error message > > Signed-off-by: Colin Ian King > --- > arch/arm/mach-socfpga/l2_cache.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >

Re: [PATCHv3 4/4] ARM: socfpga: dts: Add Monitor to A10-SR MFD

#gpio-cells = <2>; > }; > + > + monitor { > + compatible = "altr,a10sr-monitor"; > + }; > }; > }; > > Acked-by: Dinh Nguyen <dingu...@opensource.altera.com>

Re: [PATCHv3 4/4] ARM: socfpga: dts: Add Monitor to A10-SR MFD

monitor { > + compatible = "altr,a10sr-monitor"; > + }; > }; > }; > > Acked-by: Dinh Nguyen

Re: [PATCH] ARM: socfpga: updates for socfpga_defconfig

On 11/01/2016 06:54 PM, Alan Tull wrote: > This patch enables the following in the > socfpga_defconfig: > > +CONFIG_OF_OVERLAY=y > Enable support for Device Tree Overlays > > +CONFIG_FPGA_REGION=y > Enable device tree overlay support for FPGA > programming > >

Re: [PATCH] ARM: socfpga: updates for socfpga_defconfig

On 11/01/2016 06:54 PM, Alan Tull wrote: > This patch enables the following in the > socfpga_defconfig: > > +CONFIG_OF_OVERLAY=y > Enable support for Device Tree Overlays > > +CONFIG_FPGA_REGION=y > Enable device tree overlay support for FPGA > programming > >

Re: [RFC RESEND] serial: 8250: fix regression in 8250 uart driver

On 09/07/2016 12:16 PM, Andy Shevchenko wrote: > On Tue, 2016-08-23 at 08:53 -0500, Dinh Nguyen wrote: >> Hi Andy, >> >> On 08/17/2016 06:14 AM, Andy Shevchenko wrote: >>> >>> >>> I sent a v2 of the series for internal review, same you may found

Re: [RFC RESEND] serial: 8250: fix regression in 8250 uart driver

On 09/07/2016 12:16 PM, Andy Shevchenko wrote: > On Tue, 2016-08-23 at 08:53 -0500, Dinh Nguyen wrote: >> Hi Andy, >> >> On 08/17/2016 06:14 AM, Andy Shevchenko wrote: >>> >>> >>> I sent a v2 of the series for internal review, same you may found

Re: [PATCH 06/10] reset: socfpga: add driver Kconfig option

Hi Philipp, just a minor nit: On 08/24/2016 08:28 AM, Philipp Zabel wrote: > Visible only if COMPILE_TEST is enabled, this allows to include the > driver in build tests. > > Cc: Dinh Nguyen <dingu...@opensource.altera.com> > Signed-off-by: Philipp Zabel <p.za...@pengutro

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