08.04.2021 15:40, Thierry Reding пишет:
> On Mon, Mar 29, 2021 at 02:32:55AM +0300, Dmitry Osipenko wrote:
>> All consumer-grade Android and Chromebook devices show a splash screen
>> on boot and then display is left enabled when kernel is booted. This
>> behaviour is unac
08.04.2021 16:26, Thierry Reding пишет:
> On Thu, Apr 08, 2021 at 02:42:42AM -0700, Nicolin Chen wrote:
>> On Mon, Mar 29, 2021 at 02:32:55AM +0300, Dmitry Osipenko wrote:
>>> All consumer-grade Android and Chromebook devices show a splash screen
>>> on boot and then d
08.04.2021 16:06, Thierry Reding пишет:
> On Thu, Apr 08, 2021 at 02:25:19AM +0300, Dmitry Osipenko wrote:
>> 08.04.2021 02:00, Sowjanya Komatineni пишет:
>>>
>>> On 4/7/21 3:57 PM, Sowjanya Komatineni wrote:
>>>>
>>>> On 4/7/21 2:36 PM, Dmit
08.04.2021 19:40, Sowjanya Komatineni пишет:
> This patch adds a check on present of PM domain and calls legacy power
> domain API tegra_powergate_power_off() only when PM domain is not present.
>
> This is a follow-up patch to Tegra186 AHCI support patch series
> https://lore.kernel.org/patchwork
08.04.2021 23:29, Rob Herring пишет:
> On Sun, Apr 04, 2021 at 06:55:01PM +0300, Dmitry Osipenko wrote:
>> Convert Tegra20 External Memory Controller binding to schema.
>>
>> Signed-off-by: Dmitry Osipenko
>> ---
>> .../memory-controllers/nvidia,tegra20-emc.
epare(tegra->sata_clk);
> - tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
> + if (!tegra->pdev->dev.pm_domain)
> + tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
>
> regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
> }
>
Looks good, thank you.
Reviewed-by: Dmitry Osipenko
ctively.
Signed-off-by: Dmitry Osipenko
Fixes: 7232398abc6a (ARM: tegra: Convert PMC to a driver)
Cc: # v3.17+
---
drivers/soc/tegra/pmc.c | 37 +++--
1 file changed, 19 insertions(+), 18 deletions(-)
diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra
Oh, just after sending email, I realized that commit description isn't correct.
I'll send V2.
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Please re
oot CPU's on suspend. Fix it by making PMC driver use
syscore PM ops to ensure correct order of scratch register usage.
Signed-off-by: Dmitry Osipenko
Fixes: 7232398abc6a (ARM: tegra: Convert PMC to a driver)
Cc: # v3.17+
---
v2: changed commit description
dri
I think "ARM: tegra:" is wrong prefix for this patch and "soc: tegra:" should be
used instead to show that it belongs to SoC driver, not arch code.
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More major
22.01.2015 18:22, Dmitry Osipenko пишет:
22.01.2015 10:55, Alexandre Courbot пишет:
On Thu, Jan 22, 2015 at 4:40 PM, Thierry Reding
wrote:
Should this not technically be le32_to_cpu() since the data originates
from the I2C controller?
No, i2c_readl returns value in CPU endianness, so it&#
22.01.2015 19:06, Dmitry Osipenko пишет:
22.01.2015 18:22, Dmitry Osipenko пишет:
22.01.2015 10:55, Alexandre Courbot пишет:
On Thu, Jan 22, 2015 at 4:40 PM, Thierry Reding
wrote:
Should this not technically be le32_to_cpu() since the data originates
from the I2C controller?
No, i2c_readl
Support CPU BE mode by adding endianness conversion for memcpy interactions.
Signed-off-by: Dmitry Osipenko
---
Changelog:
v2: For consistency cpu_to_le32() changed to le32_to_cpu() because
i2c_writel() takes BE value in BE CPU mode and value is in LE format.
drivers/i2c/busses/i2c-tegra.c
23.01.2015 12:45, Thierry Reding пишет:
On Thu, Jan 22, 2015 at 08:18:34PM +0300, Dmitry Osipenko wrote:
22.01.2015 19:06, Dmitry Osipenko пишет:
22.01.2015 18:22, Dmitry Osipenko пишет:
22.01.2015 10:55, Alexandre Courbot пишет:
On Thu, Jan 22, 2015 at 4:40 PM, Thierry Reding
wrote
23.01.2015 16:27, Dmitry Osipenko пишет:
23.01.2015 12:45, Thierry Reding пишет:
On Thu, Jan 22, 2015 at 08:18:34PM +0300, Dmitry Osipenko wrote:
22.01.2015 19:06, Dmitry Osipenko пишет:
22.01.2015 18:22, Dmitry Osipenko пишет:
22.01.2015 10:55, Alexandre Courbot пишет:
On Thu, Jan 22, 2015
26.01.2015 19:03, Wolfram Sang пишет:
Gaahh! I'm sure it wasn't working before! I'll make more testing and send v3
without "val = 0", if all will be fine.
Please either send V3 or explicitly say V2 is OK. No need to hurry, just
saying that I am waiting for updates here...
Sure!
--
Dmitry
-
Support CPU BE mode by adding endianness conversion for memcpy interactions.
Signed-off-by: Dmitry Osipenko
Acked-by: Alexandre Courbot
---
Changelog:
v2: For consistency cpu_to_le32() changed to le32_to_cpu() because
i2c_writel() takes BE value in BE CPU mode and value is in LE format.
v3
Hi, this is third attempt to fix Tegra20 suspend bug. First was to use other
PMC scratch register for tegra_resume() address store and second to use syscore
ops for PMC driver.
Thierry Reding proposed other solution: to use IRAM instead of PMC scratch
register. I prepared two implementation varian
PU's on suspend. Fix it by storing "resettable" status in
IRAM instead of PMC scratch register.
Signed-off-by: Dmitry Osipenko
Fixes: 7232398abc6a (ARM: tegra: Convert PMC to a driver)
Cc: # v3.17+
---
arch/arm/mach-tegra/cpuidle-tegra20.c | 5 ++---
arch/arm/mach-tegra/reset-ha
PU's on suspend. Fix it by storing tegra_resume() physical
address in IRAM instead of PMC scratch register.
Signed-off-by: Dmitry Osipenko
Fixes: 7232398abc6a (ARM: tegra: Convert PMC to a driver)
Cc: # v3.17+
---
arch/arm/mach-tegra/pm.c| 3 +++
arch/arm/mach-tegra/reset-hand
CPU1 "resettable" status is already cleared by final suspend function in case
of suspend abortion and by reset handler in case of completed CPU powergate,
no point to do it again.
Signed-off-by: Dmitry Osipenko
---
arch/arm/mach-tegra/cpuidle-tegra20.c | 2 --
1 file changed, 2
15.01.2015 15:49, Dmitry Osipenko пишет:
CPU1 "resettable" status is already cleared by final suspend function in case
of suspend abortion and by reset handler in case of completed CPU powergate,
no point to do it again.
Signed-off-by: Dmitry Osipenko
---
arch/arm/mach-tegra/cpuid
07.01.2015 17:33, Thierry Reding пишет:
> On Tue, Dec 09, 2014 at 10:36:50PM +, Paul Walmsley wrote:
>>
>> Tegra SoCs with 64-bit ARM support don't currently support deep CPU
>> low-power states in mainline Linux. When this support is added in the
>> future, it will probably look rather differ
07.01.2015 18:24, Dmitry Osipenko пишет:
> For now there is no feedback for my suspend bug patch (other than for V1),
> but,
>
To be more correct, by V1 I meant http://patchwork.ozlabs.org/patch/423224/
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08.01.2015 11:49, Thierry Reding пишет:
> I don't like changing this back to syscore_ops since it makes things
> less easier to follow. I also don't think that using PMC_SCRATCH41 for
> two different purposes is a good thing. There are a couple of
> suggestions in my reply to your original patch. C
08.01.2015 13:58, Thierry Reding пишет:
> On Thu, Jan 08, 2015 at 12:42:47PM +0300, Dmitry Osipenko wrote:
>> 08.01.2015 11:49, Thierry Reding пишет:
>>> I don't like changing this back to syscore_ops since it makes things
>>> less easier to follow. I also don'
hierry Reding wrote:
>>>>> Old Signed by an unknown key
>>>>
>>>> On Mon, Dec 22, 2014 at 11:00:16AM -0700, Stephen Warren wrote:
>>>>> On 12/22/2014 10:27 AM, Dmitry Osipenko wrote:
>>>>>> 22.12.2014 19:17, Stephen Warren п
wrote:
>>>> On Thu, Jan 08, 2015 at 11:57:43AM +0100, Thierry Reding wrote:
>>>>>> Old Signed by an unknown key
>>>>>
>>>>> On Mon, Dec 22, 2014 at 11:00:16AM -0700, Stephen Warren wrote:
>>>>>> On 12/22/2014 10:27
19.01.2015 17:12, Thierry Reding пишет:
On Thu, Jan 15, 2015 at 01:58:57PM +0300, Dmitry Osipenko wrote:
Commit 7232398abc6a ("ARM: tegra: Convert PMC to a driver") changed
tegra_resume()
location storing from late to early and, as a result, broke suspend on Tegra20.
PMC scratch regi
19.01.2015 20:26, Stephen Warren пишет:
Hopefully this works out. I suppose it's unlikely anyone will be running code on
the AVP upstrem, so any potential conflict with AVP's usage of IRAM isn't likely
to occur.
I don't see how it can conflict with AVP code. First KB of IRAM is reserved for
res
19.01.2015 20:45, Stephen Warren пишет:
On 01/19/2015 10:41 AM, Dmitry Osipenko wrote:
19.01.2015 20:26, Stephen Warren пишет:
Hopefully this works out. I suppose it's unlikely anyone will be
running code on
the AVP upstrem, so any potential conflict with AVP's usage of IRAM
isn&#
19.01.2015 21:00, Dmitry Osipenko пишет:
19.01.2015 20:45, Stephen Warren пишет:
On 01/19/2015 10:41 AM, Dmitry Osipenko wrote:
19.01.2015 20:26, Stephen Warren пишет:
Hopefully this works out. I suppose it's unlikely anyone will be
running code on
the AVP upstrem, so any potential con
This patch adds support for big-endian CPU mode to assembler code, which is
required for booting secondary CPU's, cpuidle drivers and machine suspend/resume
functionality with big-endian kernel.
Signed-off-by: Dmitry Osipenko
---
Tested on Tegra 2 and 3.
Changelog:
V2: Cleanup a bit: reor
Convert CPU reset vector address to LE to support big-endian kernel.
Signed-off-by: Dmitry Osipenko
---
arch/arm/firmware/trusted_foundations.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/firmware/trusted_foundations.c
b/arch/arm/firmware/trusted_foundations.c
This patch not tested. I assume that firmware save/restore cp15 context, i.e. it
doesn't require switching to LE before smc call and restore endianness after.
--
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20.03.2015 19:07, Stephen Warren пишет:
On 03/20/2015 09:36 AM, Dmitry Osipenko wrote:
Convert CPU reset vector address to LE to support big-endian kernel.
Naively this sounds a little odd; the value here is in a CPU register all the
time, not in memory, so I'm not sure why endianne
[Re-sending the review I made before of the series RESEND]
> Hello Stefan,
>
> I don't have expertise to review the actual NAND-related driver logic, so I
> only
> reviewed the basics. The driver code looks good to me, though I've couple
> minor
> comments.
>
> On 21.05.2018 03:16, Stefan Agne
On 22.05.2018 15:19, Stefan Agner wrote:
> [review sent to my first patch sent off-ml, moving to ml thread]
>
> On 21.05.2018 16:05, Dmitry Osipenko wrote:
>> Hello Stefan,
>>
>> I don't have expertise to review the actual NAND-related driver logic, so I
>
Tegra20-cpufreq driver missed enabling the CPU clocks. This results in a
clock-enable refcount disbalance on PLL_P <-> PLL_X reparent, causing
PLL_X to get disabled while it shouldn't. Fix this by enabling the clocks
on the driver probe.
Signed-off-by: Dmitry Osipenko
---
CPUFreq
On 23.05.2018 08:58, Viresh Kumar wrote:
> On 23-05-18, 00:14, Dmitry Osipenko wrote:
>> Tegra20-cpufreq driver missed enabling the CPU clocks. This results in a
>> clock-enable refcount disbalance on PLL_P <-> PLL_X reparent, causing
>> PLL_X to get disabled whil
On 23.05.2018 08:58, Viresh Kumar wrote:
> On 23-05-18, 00:14, Dmitry Osipenko wrote:
>> Tegra20-cpufreq driver missed enabling the CPU clocks. This results in a
>> clock-enable refcount disbalance on PLL_P <-> PLL_X reparent, causing
>> PLL_X to get disabled whil
On 23.05.2018 13:44, Dmitry Osipenko wrote:
> On 23.05.2018 08:58, Viresh Kumar wrote:
>> On 23-05-18, 00:14, Dmitry Osipenko wrote:
>>> Tegra20-cpufreq driver missed enabling the CPU clocks. This results in a
>>> clock-enable refcount disbalance on PLL_P <-> PLL
PLL_P is known to be always running at 216MHz, hence there is no need to
query its rate.
Signed-off-by: Dmitry Osipenko
---
drivers/cpufreq/tegra20-cpufreq.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/cpufreq/tegra20-cpufreq.c
b/drivers/cpufreq
PLL_C is running at 600MHz which is significantly higher than the 216MHz
of the PLL_P and it is known that PLL_C is always-ON because AHB BUS is
running on that PLL. Let's use PLL_C as intermediate clock source, making
CPU snappier a tad during of the frequency transition.
Signed-off-by: D
On 24.05.2018 07:30, Viresh Kumar wrote:
> On 23-05-18, 19:00, Dmitry Osipenko wrote:
>> PLL_C is running at 600MHz which is significantly higher than the 216MHz
>> of the PLL_P and it is known that PLL_C is always-ON because AHB BUS is
>> running on that PLL. Let's use P
On 28.02.2018 12:36, Peter De Schrijver wrote:
> On Tue, Feb 27, 2018 at 02:59:11PM +0300, Dmitry Osipenko wrote:
>> On 27.02.2018 02:04, Marcel Ziswiler wrote:
>>> On Mon, 2018-02-26 at 15:42 +0300, Dmitry Osipenko wrote:
>>>> On 23.02.2018 02:04, Marcel Ziswiler
On 28.02.2018 17:14, Peter De Schrijver wrote:
> On Wed, Feb 28, 2018 at 03:00:23PM +0300, Dmitry Osipenko wrote:
>> On 28.02.2018 12:36, Peter De Schrijver wrote:
>>> On Tue, Feb 27, 2018 at 02:59:11PM +0300, Dmitry Osipenko wrote:
>>>> On 27.02.2018 02:04, Marce
On 01.03.2018 10:41, Peter De Schrijver wrote:
> On Wed, Feb 28, 2018 at 08:20:47PM +0300, Dmitry Osipenko wrote:
>> On 28.02.2018 17:14, Peter De Schrijver wrote:
>>> On Wed, Feb 28, 2018 at 03:00:23PM +0300, Dmitry Osipenko wrote:
>>>> On 28.02.2018 12:36, Peter De
On 15.01.2018 13:56, Dmitry Osipenko wrote:
> On 10.01.2018 16:59, Dmitry Osipenko wrote:
>> Machine dies if HCLK, SCLK or EMC is disabled. Hence mark these clocks
>> as critical.
>>
>> Signed-off-by: Dmitry Osipenko
>> Acked-by: Peter De Schrijver
>>
On 01.03.2018 16:19, Dmitry Osipenko wrote:
> On 01.03.2018 10:41, Peter De Schrijver wrote:
>> On Wed, Feb 28, 2018 at 08:20:47PM +0300, Dmitry Osipenko wrote:
>>> On 28.02.2018 17:14, Peter De Schrijver wrote:
>>>> On Wed, Feb 28, 2018 at 03:00:23PM +0300, D
CDEV1/CDEV2 clocks could have corresponding oscillator clock divider as
a parent. Add these dividers in order to be able to provide that parent
option.
Signed-off-by: Dmitry Osipenko
---
drivers/clk/tegra/clk-tegra20.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers
Parents of CDEV1/2 clocks are determined by muxing of the corresponding
pins. Pinctrl driver now provides the CDEV1/2 clock muxes and hence
CDEV1/2 clocks could have correct parents. Set CDEV1/2 parents to the
corresponding muxes to fix the parents.
Signed-off-by: Dmitry Osipenko
---
drivers
Muxing of pins MCLK1/2 determine the muxing of the corresponding clocks.
Make pinctrl driver to provide clock muxes for the CDEV1/2 pingroups, so
that main clk-controller driver could get an actual parent clock for the
CDEV1/2 clocks.
Signed-off-by: Dmitry Osipenko
---
drivers/pinctrl/tegra
one board and broke the
other, now Tegra's clk driver correctly sets parent for the CDEV2 clock
and hence patch could be reverted safely, restoring USB for all of the
boards.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion
er for the
suggestion), and then setting these clock muxes as parents for the CDEV1/2
clocks. In the end Marcel's CDEV2->PLL_P_OUT4 change is reverted since CDEV2
(aka MCLK2) is the actual clock source for "ulpi-link".
Dmitry Osipenko (4):
clk: tegra20: Add DEV1/DEV2 OSC divi
On 27.04.2018 12:34, Thierry Reding wrote:
> On Mon, Apr 09, 2018 at 10:28:31PM +0300, Dmitry Osipenko wrote:
> [...]
>> diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c
> [...]
>> +#define MC_GART_ERROR_REQ 0x30
>> +#define MC_DECERR_EME
On 27.04.2018 13:24, Thierry Reding wrote:
> On Fri, Apr 27, 2018 at 01:13:47PM +0300, Dmitry Osipenko wrote:
>> On 27.04.2018 12:34, Thierry Reding wrote:
>>> On Mon, Apr 09, 2018 at 10:28:31PM +0300, Dmitry Osipenko wrote:
>>> [...]
>>>> diff --git a/dri
On 27.04.2018 13:02, Thierry Reding wrote:
> On Mon, Apr 09, 2018 at 11:07:22PM +0300, Dmitry Osipenko wrote:
>> Currently GART writes one page entry at a time. More optimal would be to
>> aggregate the writes and flush BUS buffer in the end, this gives map/unmap
>> 10-40%
Hi Marcel,
On 27.04.2018 15:33, Ziswiler wrote:
> Hi Dmitry
>
> Isn't the CLK_RST_CONTROLLER_MISC_CLK_ENB_0 the other way around e.g.
> DEV1_OSC_DIV_SEL at bit 23:22 and DEV2_OSC_DIV_SEL at 21:20?
>
> On Fri, 2018-04-27 at 02:58 +0300, Dmitry Osipenko wrote:
>>
On 27.04.2018 12:39, Thierry Reding wrote:
> On Fri, Apr 13, 2018 at 02:33:50PM +0300, Dmitry Osipenko wrote:
>> From: Thierry Reding
>>
>> Define the table of memory controller hot resets for Tegra210.
>>
>> Signed-off-by: Thierry Reding
>> ---
&
On 28.05.2018 00:54, Stefan Agner wrote:
> Add support for the NAND flash controller found on NVIDIA
> Tegra 2 SoCs. This implementation does not make use of the
> command queue feature. Regular operations/data transfers are
> done in PIO mode. Page read/writes with hardware ECC make
> use of the D
On 28.05.2018 16:15, Ville Syrjälä wrote:
> On Sat, May 26, 2018 at 06:56:22PM +0300, Dmitry Osipenko wrote:
>> Color keying is the action of replacing pixels matching a given color
>> (or range of colors) with transparent pixels in an overlay when
>> performing blitting. Depe
On 29.05.2018 02:48, Dmitry Osipenko wrote:
> inversion=true" if mask has form of 0x11000111, though this could be not
For clarity: I meant s/0x11000111/0xFF000FFF/.
On 29.05.2018 15:12, Stefan Agner wrote:
> On 29.05.2018 09:48, Peter De Schrijver wrote:
>> On Mon, May 28, 2018 at 05:53:08PM +0200, Stefan Agner wrote:
>>> On 28.05.2018 09:55, Peter De Schrijver wrote:
On Sun, May 27, 2018 at 11:54:40PM +0200, Stefan Agner wrote:
> From: Lucas Stach
>
Apparently there was an attempt to avoid out-of-bounds accesses when there
is only one memory timing available, but there is a typo in the code that
neglects that attempt.
Signed-off-by: Dmitry Osipenko
---
drivers/clk/tegra/clk-emc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
On 01.06.2018 10:30, Boris Brezillon wrote:
> On Fri, 1 Jun 2018 00:16:34 +0200
> Stefan Agner wrote:
>
>> This adds the devicetree binding for the Tegra 2 NAND flash
>> controller.
>>
>> Signed-off-by: Lucas Stach
>> Signed-off-by: Stefan Agner
>> ---
>> .../bindings/mtd/nvidia-tegra20-nand.
On 06.06.2018 13:45, Thierry Reding wrote:
> On Mon, Jun 04, 2018 at 01:36:49AM +0300, Dmitry Osipenko wrote:
>> Hello,
>>
>> Couple years ago the Tegra20 EMC driver was removed from the kernel
>> due to incompatible changes in the Tegra's clock driver. This patchse
On 06.06.2018 14:02, Thierry Reding wrote:
> On Mon, Jun 04, 2018 at 01:36:54AM +0300, Dmitry Osipenko wrote:
>> Introduce driver for the External Memory Controller (EMC) found on Tegra20
>> chips, which controls the external DRAM on the board. The purpose of this
>> driver
On 14.05.2018 21:18, Robin Murphy wrote:
> On 11/05/18 21:05, Dmitry Osipenko wrote:
>> On 11.05.2018 15:32, Robin Murphy wrote:
>>> On 08/05/18 19:16, Dmitry Osipenko wrote:
>>>> GART aperture is shared by all devices, hence there is a single IOMMU
>>>>
On 16.05.2018 15:23, Linus Walleij wrote:
> On Fri, May 4, 2018 at 12:55 AM, Dmitry Osipenko wrote:
>
>> Muxing of pins MCLK1/2 determine the muxing of the corresponding clocks.
>> Make pinctrl driver to provide clock muxes for the CDEV1/2 pingroups, so
>> that main clk
.html
Tested-by: Robert Yang
Tested-by: Michał Mirosław
Signed-off-by: Michał Mirosław
Signed-off-by: Dmitry Osipenko
---
arch/arm/mach-tegra/reset-handler.S | 23 ---
arch/arm/mach-tegra/reset.c | 3 +++
arch/arm/mach-tegra/reset.h | 9 +++--
arch/arm/mach-
ed-by: Robert Yang
Tested-by: Michał Mirosław
Signed-off-by: Dmitry Osipenko
---
arch/arm/mach-tegra/reset-handler.S | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-tegra/reset-handler.S
b/arch/arm/mach-tegra/reset-handler.S
index 6bea95d165fa..3bf202819534 100644
--- a/arch/arm
: Michał Mirosław
Signed-off-by: Dmitry Osipenko
---
arch/arm/mach-tegra/pm.c| 49 +
arch/arm/mach-tegra/reset-handler.S | 26 +++
arch/arm/mach-tegra/sleep.S | 14 ++---
3 files changed, 84 insertions(+), 5 deletions(-)
diff --git a
lists/arm-kernel/msg594765.html
Tested-by: Robert Yang
Tested-by: Michał Mirosław
Signed-off-by: Michał Mirosław
Signed-off-by: Dmitry Osipenko
---
arch/arm/firmware/trusted_foundations.c| 41 ++
arch/arm/include/asm/trusted_foundations.h | 12 +++
2 files change
esent in device-tree.
Tested-by: Robert Yang
Tested-by: Michał Mirosław
Signed-off-by: Dmitry Osipenko
---
arch/arm/mach-tegra/tegra.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index f9587be48235..1e89cfefbf68 100644
--- a/arc
ratas in insecure mode" patch got some
cleanup, in particular resolved the messiness in
__tegra_cpu_reset_handler_data.
- Added a comment to tf_cache_write_sec(), justifying the warning
message.
Dmitry Osipenko (7):
ARM: trusted_foundations: Support L2 cache
The Trusted Foundations firmware call varies depending on the required
suspend-mode. Make the firmware API to take the mode argument in order
to expose all of the modes to firmware user.
Tested-by: Robert Yang
Tested-by: Michał Mirosław
Signed-off-by: Dmitry Osipenko
---
arch/arm/firmware
Add a helper that provides information about whether Trusted Foundations
firmware operations have been registered.
Tested-by: Robert Yang
Tested-by: Michał Mirosław
Signed-off-by: Dmitry Osipenko
---
arch/arm/firmware/trusted_foundations.c| 5 +
arch/arm/include/asm
28.02.2019 16:27, Russell King - ARM Linux admin пишет:
> On Thu, Feb 28, 2019 at 04:17:01PM +0300, Dmitry Osipenko wrote:
>> +#ifdef CONFIG_CACHE_L2X0
>> +static void tf_cache_write_sec(unsigned long val, unsigned int reg)
>> +{
>> +u32 l2x0_way_mask = 0xf
esent in device-tree.
Tested-by: Robert Yang
Tested-by: Michał Mirosław
Signed-off-by: Dmitry Osipenko
---
arch/arm/mach-tegra/tegra.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index f9587be48235..1e89cfefbf68 100644
--- a/arc
: Michał Mirosław
Signed-off-by: Dmitry Osipenko
---
arch/arm/mach-tegra/pm.c| 49 +
arch/arm/mach-tegra/reset-handler.S | 26 +++
arch/arm/mach-tegra/sleep.S | 14 ++---
3 files changed, 84 insertions(+), 5 deletions(-)
diff --git a
ed-by: Robert Yang
Tested-by: Michał Mirosław
Signed-off-by: Dmitry Osipenko
---
arch/arm/mach-tegra/reset-handler.S | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-tegra/reset-handler.S
b/arch/arm/mach-tegra/reset-handler.S
index 6bea95d165fa..3bf202819534 100644
--- a/arch/arm
The Trusted Foundations firmware call varies depending on the required
suspend-mode. Make the firmware API to take the mode argument in order
to expose all of the modes to firmware user.
Tested-by: Robert Yang
Tested-by: Michał Mirosław
Signed-off-by: Dmitry Osipenko
---
arch/arm/firmware
Add a helper that provides information about whether Trusted Foundations
firmware operations have been registered.
Tested-by: Robert Yang
Tested-by: Michał Mirosław
Signed-off-by: Dmitry Osipenko
---
arch/arm/firmware/trusted_foundations.c| 5 +
arch/arm/include/asm
lists/arm-kernel/msg594765.html
Tested-by: Robert Yang
Tested-by: Michał Mirosław
Signed-off-by: Michał Mirosław
Signed-off-by: Dmitry Osipenko
---
arch/arm/firmware/trusted_foundations.c| 41 ++
arch/arm/include/asm/trusted_foundations.h | 12 +++
2 files change
ess in
__tegra_cpu_reset_handler_data.
- Added a comment to tf_cache_write_sec(), justifying the warning
message.
Dmitry Osipenko (7):
ARM: trusted_foundations: Support L2 cache maintenance
ARM: trusted_foundations: Make prepare_idle call to take mode argument
.html
Tested-by: Robert Yang
Tested-by: Michał Mirosław
Signed-off-by: Michał Mirosław
Signed-off-by: Dmitry Osipenko
---
arch/arm/mach-tegra/reset-handler.S | 23 ---
arch/arm/mach-tegra/reset.c | 3 +++
arch/arm/mach-tegra/reset.h | 9 +++--
arch/arm/mach-
24.02.2019 18:21, Dmitry Osipenko пишет:
> Tegra20/30 drivers do not handle the tick_broadcast_enter() error which
> potentially could happen when CPU timer isn't permitted to be stopped.
> Let's just move out the broadcasting to the CPUIDLE core by setting the
> respective
16.04.2019 4:45, Chanwoo Choi пишет:
> Hi,
>
> I add one minor comment (KHZ -> hz).
Hello Chanwoo,
Thank you very much for the review!
> On 19. 4. 15. 오후 11:54, Dmitry Osipenko wrote:
>> The kHz to Hz is incorrectly converted in a few places in the code,
>> this r
16.04.2019 4:52, Chanwoo Choi пишет:
> Hi,
>
> On 19. 4. 15. 오후 11:54, Dmitry Osipenko wrote:
>> The clk_set_min_rate() could fail and in this case clk_set_rate() sets
>> rate to 0, which may drop EMC rate to minimum and make machine very
>> difficult to use.
>>
16.04.2019 4:59, Chanwoo Choi пишет:
> Hi,
>
> On 19. 4. 15. 오후 11:54, Dmitry Osipenko wrote:
>> There is no real benefit from doing so, hence let's drop that rate setting
>> for consistency.
>>
>> Signed-off-by: Dmitry Osipenko
>> ---
>>
16.04.2019 11:00, Chanwoo Choi пишет:
> Hi,
>
> On 19. 4. 15. 오후 11:54, Dmitry Osipenko wrote:
>> The write memory barrier isn't needed because the BUS buffer is flushed
>> by read after write that happens after the removed wmb(), we will also
>> use readl() i
16.04.2019 5:32, Chanwoo Choi пишет:
> Hi,
>
> patch6/7/8/9 are for handling of exception handling in probe() function.
> Actually, I'm not sure that there are special reason to split out
> the patches. I think that you can squash patch6/7/8/9 to only one patch.
Indeed, I was rebasing and reorder
16.04.2019 8:56, Chanwoo Choi пишет:
> Hi,
>
> It looks good to me to drop the primary interrupt handler
> but I have some comments. Please check it.
>
> On 19. 4. 15. 오후 11:54, Dmitry Osipenko wrote:
>> There is no real need in the primary interrupt handler, hence m
16.04.2019 10:15, Chanwoo Choi пишет:
> Hi,
>
> On 19. 4. 15. 오후 11:54, Dmitry Osipenko wrote:
>> The frequency value potentially could change in-between. It doesn't
>> cause any real problem at all right now, but that could change in the
>> future. Hen
16.04.2019 10:41, Chanwoo Choi пишет:
> Hi,
>
> In this patchset,
> the patch11 adds new 'disable_interrupt' goto statement
> and then patch15 removes 'disable_interrupt' goto statement again.
> Actually, it is inefficient.
>
> If you change the order of patches,
> you could remove this stuff.
O
16.04.2019 10:48, Chanwoo Choi пишет:
> Hi,
>
> On 19. 4. 15. 오후 11:55, Dmitry Osipenko wrote:
>> The devfreq driver can be used on Tegra30 without any code change and
>> it works perfectly fine, the default Tegra124 parameters are good enough
>> for Tegra30.
>>
16.04.2019 10:43, Chanwoo Choi пишет:
> On 19. 4. 15. 오후 11:55, Dmitry Osipenko wrote:
>> The driver's compilation doesn't have any specific dependencies, hence
>> the COMPILE_TEST option can be supported in Kconfig.
>>
>> Signed-off-by: Dmitry Osipenko
&
16.04.2019 11:31, Chanwoo Choi пишет:
> Hi,
>
> On 19. 4. 15. 오후 11:55, Dmitry Osipenko wrote:
>> Add devfreq driver for NVIDIA Tegra20 SoC's. The driver periodically
>> reads out Memory Controller counters and adjusts memory frequency based
>> on the memory clien
17.04.2019 3:26, Chanwoo Choi пишет:
> Hi,
>
> On 19. 4. 17. 오전 1:11, Dmitry Osipenko wrote:
>> 16.04.2019 11:31, Chanwoo Choi пишет:
>>> Hi,
>>>
>>> On 19. 4. 15. 오후 11:55, Dmitry Osipenko wrote:
>>>> Add devfreq driver for NVIDIA Tegra2
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