[RFC PATCH v2 2/2] drm/tegra: plane: Implement generic colorkey property for older Tegra's

a minimal color keying support is implemented, it is enough to provide userspace like Opentegra Xorg driver with ability to support color keying by the XVideo extension. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/gpu/drm/tegra/dc.c| 31 +++ drivers/gpu/drm/tegr

[PATCH v2] media: staging: tegra-vde: Reset memory client

DMA requests must be blocked before resetting VDE HW, otherwise it is possible to get a memory corruption or a machine hang. Use the reset control provided by the Memory Controller to block DMA before resetting the VDE HW. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- Changelo

[RFC PATCH v2 1/2] drm: Add generic colorkey properties

. This patch is based on the initial work done by Laurent Pinchart, most of credits for this patch goes to him. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/gpu/drm/drm_atomic.c | 36 ++ drivers/gpu/drm/drm_blend.c | 229 +++ include/drm/drm_b

[PATCH v1 1/4] dt: bindings: tegra20-emc: Document interrupt property

EMC has a dedicated interrupt that is used to notify about completion of HW operations. Document the interrupt property. Signed-off-by: Dmitry Osipenko --- .../devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt| 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation

[PATCH v1 0/4] Tegra20 External Memory Controller driver

-up. Later we may consider implementing dynamic memory frequency scaling, utilizing functionality provided by this driver. Dmitry Osipenko (4): dt: bindings: tegra20-emc: Document interrupt property ARM: dts: tegra20: Add interrupt to External Memory Controller clk: tegra20: Turn EMC clock

[PATCH v1 4/4] memory: tegra: Introduce Tegra20 EMC driver

Introduce driver for the External Memory Controller (EMC) found on Tegra20 chips, which controls the external DRAM on the board. The purpose of this driver is to program memory timings for external memory on the EMC clock rate change. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra

[PATCH v1 3/4] clk: tegra20: Turn EMC clock gate into divider

Kernel should never gate the EMC clock as it causes immediate lockup, so removing clk-gate functionality doesn't affect anything. Turning EMC clk gate into divider allows to implement glitch-less EMC scaling, avoiding reparenting to a backup clock. Signed-off-by: Dmitry Osipenko --- drivers/clk

[PATCH v1 2/4] ARM: dts: tegra20: Add interrupt to External Memory Controller

Add interrupt entry into the EMC DT node. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra20.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 983dd5c14794..3cd3cb28cfd9 100644 --- a/arch/arm/boot/dts/tegra20

Re: [PATCH v1] i2c: tegra: Remove suspend-resume

On 30.05.2018 23:25, Wolfram Sang wrote: > >> Applied to for-next, thanks! > > I removed the stable tag, though. I am not 100% sure if there are not > any side-effects for other users. If you still think it should go to > stable, please mention this patch to stable@ after it was applied to >

Re: [PATCH v2 4/6] clk: tegra20: init NDFLASH clock to sensible rate

On 29.05.2018 15:12, Stefan Agner wrote: > On 29.05.2018 09:48, Peter De Schrijver wrote: >> On Mon, May 28, 2018 at 05:53:08PM +0200, Stefan Agner wrote: >>> On 28.05.2018 09:55, Peter De Schrijver wrote: On Sun, May 27, 2018 at 11:54:40PM +0200, Stefan Agner wrote: > From: Lucas Stach

[PATCH v2 0/5] Tegra20 External Memory Controller driver

out use_pllm_ud bit checking into a standalone patch for consistency. Dmitry Osipenko (5): dt: bindings: tegra20-emc: Document interrupt property ARM: dts: tegra20: Add interrupt to External Memory Controller clk: tegra20: Turn EMC clock gate into divider clk: tegra20: Check

[PATCH v2 5/5] memory: tegra: Introduce Tegra20 EMC driver

Introduce driver for the External Memory Controller (EMC) found on Tegra20 chips, which controls the external DRAM on the board. The purpose of this driver is to program memory timing for external memory on the EMC clock rate change. Signed-off-by: Dmitry Osipenko --- drivers/memory/tegra

[PATCH v2 2/5] ARM: dts: tegra20: Add interrupt to External Memory Controller

Add interrupt entry into the EMC DT node. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra20.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 983dd5c14794..3cd3cb28cfd9 100644 --- a/arch/arm/boot/dts/tegra20

[PATCH v2 3/5] clk: tegra20: Turn EMC clock gate into divider

Kernel should never gate the EMC clock as it causes immediate lockup, so removing clk-gate functionality doesn't affect anything. Turning EMC clk gate into divider allows to implement glitch-less EMC scaling, avoiding reparenting to a backup clock. Signed-off-by: Dmitry Osipenko --- drivers/clk

[PATCH v2 1/5] dt: bindings: tegra20-emc: Document interrupt property

EMC has a dedicated interrupt that is used to notify about completion of HW operations. Document the interrupt property. Signed-off-by: Dmitry Osipenko --- .../devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt| 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation

[PATCH v2 4/5] clk: tegra20: Check whether direct PLLM sourcing is turned off for EMC

Ensure that direct PLLM sourcing is turned off for EMC as we don't support that configuration in the clk driver. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra20.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra

[PATCH v1] clk: tegra: Mark Memory Controller clock as critical

Memory Controller should be always-on. Currently the sibling EMC clock is marked as critical, let's mark MC clock too for consistency. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-divider.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/clk/tegra

Re: [PATCH v3 4/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

On 01.06.2018 01:16, Stefan Agner wrote: > Add support for the NAND flash controller found on NVIDIA > Tegra 2 SoCs. This implementation does not make use of the > command queue feature. Regular operations/data transfers are > done in PIO mode. Page read/writes with hardware ECC make > use of the

Re: [PATCH v1 3/4] clk: tegra20: Turn EMC clock gate into divider

On 02.06.2018 09:37, Stephen Boyd wrote: > Quoting Dmitry Osipenko (2018-05-30 08:06:45) >> Kernel should never gate the EMC clock as it causes immediate lockup, so >> removing clk-gate functionality doesn't affect anything. Turning EMC clk >> gate into divider allows to impl

[PATCH v1] clk: tegra: emc: Avoid out-of-bounds bug

Apparently there was an attempt to avoid out-of-bounds accesses when there is only one memory timing available, but there is a typo in the code that neglects that attempt. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-emc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff

Re: [PATCH v3 3/6] mtd: rawnand: tegra: add devicetree binding

On 01.06.2018 10:30, Boris Brezillon wrote: > On Fri, 1 Jun 2018 00:16:34 +0200 > Stefan Agner wrote: > >> This adds the devicetree binding for the Tegra 2 NAND flash >> controller. >> >> Signed-off-by: Lucas Stach >> Signed-off-by: Stefan Agner >> --- >>

Re: [PATCH v2 3/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

On 28.05.2018 00:54, Stefan Agner wrote: > Add support for the NAND flash controller found on NVIDIA > Tegra 2 SoCs. This implementation does not make use of the > command queue feature. Regular operations/data transfers are > done in PIO mode. Page read/writes with hardware ECC make > use of the

Re: [PATCH v2 0/5] Initial support of Trusted Foundations on Tegra30

On Friday, 29 June 2018 22:37:02 MSK Peter Geis wrote: > Good Afternoon, > > I have tested these patches on the Ouya T3 device. > They work great to enable the L2 cache controller, however they do not > respect explicitly disabling the L2 cache controller via the kernel > config nor device tree.

[PATCH v1 2/4] pinctrl: tegra20: Provide CDEV1/2 clock muxes

Muxing of pins MCLK1/2 determine the muxing of the corresponding clocks. Make pinctrl driver to provide clock muxes for the CDEV1/2 pingroups, so that main clk-controller driver could get an actual parent clock for the CDEV1/2 clocks. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- d

[PATCH v1 4/4] ARM: dts: tegra20: Revert "Fix ULPI regression on Tegra20"

one board and broke the other, now Tegra's clk driver correctly sets parent for the CDEV2 clock and hence patch could be reverted safely, restoring USB for all of the boards. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- arch/arm/boot/dts/tegra20.dtsi | 2 +- 1 file changed, 1 ins

[PATCH v1 0/4] Restore ULPI USB on Tegra20

suggestion), and then setting these clock muxes as parents for the CDEV1/2 clocks. In the end Marcel's CDEV2->PLL_P_OUT4 change is reverted since CDEV2 (aka MCLK2) is the actual clock source for "ulpi-link". Dmitry Osipenko (4): clk: tegra20: Add DEV1/DEV2 OSC dividers pinctrl:

[PATCH v1 1/4] clk: tegra20: Add DEV1/DEV2 OSC dividers

CDEV1/CDEV2 clocks could have corresponding oscillator clock divider as a parent. Add these dividers in order to be able to provide that parent option. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/clk/tegra/clk-tegra20.c | 12 1 file changed, 12 insertions(+)

[PATCH v1 3/4] clk: tegra20: Set correct parents for CDEV1/2 clocks

Parents of CDEV1/2 clocks are determined by muxing of the corresponding pins. Pinctrl driver now provides the CDEV1/2 clock muxes and hence CDEV1/2 clocks could have correct parents. Set CDEV1/2 parents to the corresponding muxes to fix the parents. Signed-off-by: Dmitry Osipenko <

[PATCH v2 4/4] ARM: dts: tegra20: Revert "Fix ULPI regression on Tegra20"

one board and broke the other, now Tegra's clk driver correctly sets parent for the CDEV2 clock and hence patch could be reverted safely, restoring USB for all of the boards. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> Reviewed-by: Marcel Ziswiler <mar...@ziswiler.com> Tested-by: Ma

[PATCH v2 2/4] clk: tegra20: Correct parents of CDEV1/2 clocks

Parents of CDEV1/2 clocks are determined by muxing of the corresponding pins. Pinctrl driver now provides the CDEV1/2 clock muxes and hence CDEV1/2 clocks could have correct parents. Set CDEV1/2 parents to the corresponding muxes to fix the parents. Signed-off-by: Dmitry Osipenko <

[PATCH v2 0/4] Restore ULPI USB on Tegra20

sted by Linus Walleij. - Addressed v1 review comments: fixed swapped DEV1/2 clk div bits, made DEV1/2 divs read-only, etc minor changes. Dmitry Osipenko (4): clk: tegra20: Add DEV1/DEV2 OSC dividers clk: tegra20: Correct parents of CDEV1/2 clocks clk: tegra: Add quirk f

[PATCH v2] pinctrl: tegra20: Provide CDEV1/2 clock muxes

Muxing of pins MCLK1/2 determine the muxing of the corresponding clocks. Make pinctrl driver to provide clock muxes for the CDEV1/2 pingroups, so that main clk-controller driver could get an actual parent clock for the CDEV1/2 clocks. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> Re

[PATCH v2 1/4] clk: tegra20: Add DEV1/DEV2 OSC dividers

CDEV1/CDEV2 clocks could have corresponding oscillator clock divider as a parent. Add these dividers in order to be able to provide that parent option. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> Reviewed-by: Marcel Ziswiler <mar...@ziswiler.com> Tested-by: Marcel Z

[PATCH v2 3/4] clk: tegra: Add quirk for getting CDEV1/2 clocks

to be enabled by the child, so let's return EPROBE_DEFER until parent clock appear. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/clk/tegra/clk.c | 34 +- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk.c b/d

[PATCH v1 1/5] drm/tegra: dc: Balance IOMMU group refcounting

-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/gpu/drm/tegra/dc.c | 35 +-- drivers/gpu/drm/tegra/dc.h | 2 +- drivers/gpu/drm/tegra/drm.h | 2 +- 3 files changed, 19 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm

[PATCH v1 2/5] drm/tegra: gr2d: Add IOMMU support

Attach GR2D to the display IOMMU group in order to provide GR2D access to BO's IOVA. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/gpu/drm/tegra/gr2d.c | 31 +-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm

[PATCH v1 3/5] drm/tegra: gr3d: Add IOMMU support

Attach GR3D to the displays IOMMU group in order to provide GR3D access to BO's IOVA. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/gpu/drm/tegra/gr3d.c | 27 +++ 1 file changed, 27 insertions(+) diff --git a/drivers/gpu/drm/tegra/gr3d.c b/drivers/g

[PATCH v1 5/5] ARM: dts: tegra114: Add IOMMU nodes to Host1x and its clients

Enable IOMMU support for Host1x and its clients. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- arch/arm/boot/dts/tegra114.dtsi | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 0e4a13295d8a..84c435

[PATCH v1 0/5] Support IOMMU for 2d/3d on Tegra30/114

Hi, This series enables IOMMU support for 2d/3d HW on Tegra30/114, as a result userspace that uses 2d/3d could work with the active IOMMU. Dmitry Osipenko (5): drm/tegra: dc: Balance IOMMU group refcounting drm/tegra: gr2d: Add IOMMU support drm/tegra: gr3d: Add IOMMU support ARM: dts

[PATCH v1 4/5] ARM: dts: tegra30: Add IOMMU nodes to Host1x and its clients

Enable IOMMU support for Host1x and its clients. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- arch/arm/boot/dts/tegra30.dtsi | 14 ++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index a110cf

[PATCH v1 2/3] drm/tegra: plane: Implement zPos plane property for older Tegra's

Older Tegra's do not support planes z position handling in hardware, but HW provides knobs for zPos implementation in software. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/gpu/drm/tegra/dc.c| 134 --- drivers/gpu/drm/tegra/plane.c

[PATCH v1 3/3] drm/tegra: dc: Rename supports_blending to has_legacy_blending

Older Tegra's support blending. Rename SoC info entry supports_blending to has_legacy_blending to eliminate confusion. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/gpu/drm/tegra/dc.c | 20 ++-- drivers/gpu/drm/tegra/dc.h | 2 +- 2 files changed, 11 inse

[PATCH v1 1/3] drm/tegra: dc: Enable plane scaling filters

Currently resized plane produces a "pixelated" image which doesn't look nice, especially in a case of a video overlay. Enable scaling filters that significantly improve image quality of a scaled overlay. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/gpu/drm

[PATCH v1 0/3] Couple more DRM plane features on Tegra

Hi, This series improves DRM plane support by supporting zPos on older Tegra's and enabling plane scaling filters (up to Tegra210). Dmitry Osipenko (3): drm/tegra: dc: Enable plane scaling filters drm/tegra: plane: Implement zPos plane property for older Tegra's drm/tegra: dc: Rename

Re: [PATCH v1 1/4] clk: tegra20: Add DEV1/DEV2 OSC dividers

On 03.05.2018 14:59, Dmitry Osipenko wrote: > On 27.04.2018 16:00, Marcel Ziswiler wrote: >> On Fri, 2018-04-27 at 15:54 +0300, Dmitry Osipenko wrote: >>> Hi Marcel, >>> >>> On 27.04.2018 15:33, Ziswiler wrote: >>>> Hi Dmitry >>>> &g

Re: [PATCH v1 1/4] clk: tegra20: Add DEV1/DEV2 OSC dividers

On 27.04.2018 16:00, Marcel Ziswiler wrote: > On Fri, 2018-04-27 at 15:54 +0300, Dmitry Osipenko wrote: >> Hi Marcel, >> >> On 27.04.2018 15:33, Ziswiler wrote: >>> Hi Dmitry >>> >>> Isn't the CLK_RST_CONTROLLER_MISC_CLK_ENB_0 the other way a

Re: [PATCH v1 1/4] clk: tegra20: Add DEV1/DEV2 OSC dividers

On 03.05.2018 15:30, Marcel Ziswiler wrote: > On Thu, 2018-05-03 at 15:02 +0300, Dmitry Osipenko wrote: >> ... >>> Marcel, you previously mentioned that reverting of your DT patch >>> works for the >>> Colibri now. Does that reverting also work for the 4.17 kern

[PATCH v4 2/5] media: dt: bindings: Add binding for NVIDIA Tegra Video Decoder Engine

Add binding documentation for the Video Decoder Engine which is found on NVIDIA Tegra20/30/114/124/132 SoC's. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- .../devicetree/bindings/media/nvidia,tegra-vde.txt | 55 ++ 1 file changed, 55 insertions(+) create mode

[PATCH v4 1/5] ARM: tegra: Add device tree node to describe IRAM

From: Vladimir Zapolskiy All Tegra SoCs contain 256KiB IRAM, which is used to store CPU resume code and by hardware engines like a video decoder. Signed-off-by: Vladimir Zapolskiy --- arch/arm/boot/dts/tegra114.dtsi | 8 arch/arm/boot/dts/tegra124.dtsi

[PATCH v4 4/5] ARM: dts: tegra20: Add video decoder node

Add Video Decoder Engine device node. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- arch/arm/boot/dts/tegra20.dtsi | 27 +++ 1 file changed, 27 insertions(+) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index aaf32f

[PATCH v4 5/5] ARM: defconfig: tegra: Enable Video Decoder driver

Compile Tegra VDE driver as a module. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- arch/arm/configs/tegra_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index 6678f2929356..c931bd

Re: [PATCH V4 13/45] block: blk-merge: try to make front segments in full size

On 09.01.2018 17:33, Ming Lei wrote: > On Tue, Jan 09, 2018 at 04:18:39PM +0300, Dmitry Osipenko wrote: >> On 09.01.2018 05:34, Ming Lei wrote: >>> On Tue, Jan 09, 2018 at 12:09:27AM +0300, Dmitry Osipenko wrote: >>>> On 18.12.2017 15:22, Ming Lei wrote: >>&g

Re: [PATCH V4 13/45] block: blk-merge: try to make front segments in full size

On 18.12.2017 15:22, Ming Lei wrote: > When merging one bvec into segment, if the bvec is too big > to merge, current policy is to move the whole bvec into another > new segment. > > This patchset changes the policy into trying to maximize size of > front segments, that means in above situation,

Re: [PATCH] media: staging: tegra-vde: select DMA_SHARED_BUFFER

> config TEGRA_VDE > tristate "NVIDIA Tegra Video Decoder Engine driver" > depends on ARCH_TEGRA || COMPILE_TEST > + select DMA_SHARED_BUFFER > select SRAM > help > Say Y here to enable support for the NVIDIA Tegra video decoder > Thanks! Acked-by: Dmitry Osipenko <dig...@gmail.com>

[PATCH v3 3/3] clk: tegra: Specify VDE clock rate

Currently VDE clock rate is determined by clock config left from bootloader, let's not rely on it and explicitly specify the clock rate in the CCF driver. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> Acked-by: Peter De Schrijver <pdeschrij...@nvidia.com> --- Change log: v2:

[PATCH v3 1/3] clk: tegra: Mark HCLK, SCLK and EMC as critical

Machine dies if HCLK, SCLK or EMC is disabled. Hence mark these clocks as critical. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> Acked-by: Peter De Schrijver <pdeschrij...@nvidia.com> --- Change log: v2: Fixed accidentally missed marking EMC as critical on Tegra30 and

[PATCH v3 2/3] clk: tegra20: Correct PLL_C_OUT1 setup

PLL_C_OUT_1 can't produce 216 MHz defined in the init_table. Let's set it to 240 MHz and explicitly specify HCLK rate for consistency. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> Acked-by: Peter De Schrijver <pdeschrij...@nvidia.com> --- Change log: v2: No change. v3:

Re: [PATCH V4 13/45] block: blk-merge: try to make front segments in full size

On 10.01.2018 05:40, Ming Lei wrote: > On Tue, Jan 09, 2018 at 08:02:53PM +0300, Dmitry Osipenko wrote: >> On 09.01.2018 17:33, Ming Lei wrote: >>> On Tue, Jan 09, 2018 at 04:18:39PM +0300, Dmitry Osipenko wrote: >>>> On 09.01.2018 05:34, Ming Lei wrote: >>&g

Re: [PATCH V4 13/45] block: blk-merge: try to make front segments in full size

On 09.01.2018 05:34, Ming Lei wrote: > On Tue, Jan 09, 2018 at 12:09:27AM +0300, Dmitry Osipenko wrote: >> On 18.12.2017 15:22, Ming Lei wrote: >>> When merging one bvec into segment, if the bvec is too big >>> to merge, current policy is to move the whole bvec i

Re: [PATCH v3 1/3] clk: tegra: Mark HCLK, SCLK and EMC as critical

On 10.01.2018 16:59, Dmitry Osipenko wrote: > Machine dies if HCLK, SCLK or EMC is disabled. Hence mark these clocks > as critical. > > Signed-off-by: Dmitry Osipenko <dig...@gmail.com> > Acked-by: Peter De Schrijver <pdeschrij...@nvidia.com> > --- > > Chan

[PATCH v2 2/2] memory: tegra: Introduce memory client hot reset API

/encoder/camera) and graphics (2d/3d). Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/memory/tegra/mc.c | 249 drivers/memory/tegra/tegra114.c | 25 drivers/memory/tegra/tegra124.c | 32 ++ drivers/memory/tegra/tegra20.c

[PATCH v2 0/2] Memory controller hot reset

PI. Since first revision of this patchset haven't got any comment, I'm trying again with a V2 that has one minor correction compared to V1, I've added terga_mc_hotreset_assert()/deassert() functions as in V1 there was only tegra_mc_hot_reset() and turned out it is not enough. Please review, thank

[PATCH v2 1/2] memory: tegra: Squash tegra20-mc into common tegra-mc driver

Tegra30+ has some minor differences in registers / bits layout compared to Tegra20. Let's squash Tegra20 driver into the common tegra-mc driver to reduce code a tad, this also will be useful for the upcoming Tegra's MC reset API. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- d

Re: [PATCH v2 1/2] memory: tegra: Squash tegra20-mc into common tegra-mc driver

On 14.02.2018 14:15, Peter De Schrijver wrote: > On Tue, Feb 13, 2018 at 11:30:39AM +0100, Thierry Reding wrote: >>> } >> >> It's odd that we don't have an MC clock on Tegra2. I wonder if perhaps >> we just never implemented one, or it uses one which is always on by >> default. Cc Peter to see

Re: [PATCH v2 1/2] memory: tegra: Squash tegra20-mc into common tegra-mc driver

On 13.02.2018 13:30, Thierry Reding wrote: > On Mon, Feb 12, 2018 at 08:06:30PM +0300, Dmitry Osipenko wrote: >> Tegra30+ has some minor differences in registers / bits layout compared >> to Tegra20. Let's squash Tegra20 driver into the common tegra-mc driver >> to reduce

[PATCH v2 1/2] ARM: dts: tegra30: Add IRAM node

IRAM is a static RAM that consists of four contiguous 64 KiB blocks, it is currently used to store CPU resume code, utilized by the video decoder engine and could be used as a general-purpose fast memory. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- arch/arm/boot/dts/tegra30.dt

[PATCH v2 0/2] Enable Video Decoder on Tegra30

Färber suggestion. 2) Correctly placed IRAM DT node in the address-ascending order. Dmitry Osipenko (2): ARM: dts: tegra30: Add IRAM node ARM: dts: tegra30: Add video decoder node arch/arm/boot/dts/tegra30.dtsi | 35 +++ 1 file changed, 35 insertions

[PATCH v2 2/2] ARM: dts: tegra30: Add video decoder node

Add device tree node for the Video Decoder Engine found on Tegra30 SoC's. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- arch/arm/boot/dts/tegra30.dtsi | 27 +++ 1 file changed, 27 insertions(+) diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/bo

Re: [PATCH v2 1/2] memory: tegra: Squash tegra20-mc into common tegra-mc driver

On 19.02.2018 05:04, Dmitry Osipenko wrote: > On 13.02.2018 13:30, Thierry Reding wrote: >> On Mon, Feb 12, 2018 at 08:06:30PM +0300, Dmitry Osipenko wrote: >>> Tegra30+ has some minor differences in registers / bits layout compared >>> to Tegra20. Let's squash Tegra20 d

Re: [PATCH v2 2/2] memory: tegra: Introduce memory client hot reset API

On 13.02.2018 14:24, Thierry Reding wrote: > On Mon, Feb 12, 2018 at 08:06:31PM +0300, Dmitry Osipenko wrote: >> In order to reset busy HW properly, memory controller needs to be >> involved, otherwise it possible to get corrupted memory if HW was reset >> during DMA. Introdu

[PATCH v3 08/15] memory: tegra: Remove unused headers inclusions

Tegra210 contains some unused leftover headers, remove them for consistency. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/memory/tegra/tegra210.c | 5 - 1 file changed, 5 deletions(-) diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c

[PATCH v3 11/15] memory: tegra: Add Tegra210 memory controller hot resets

From: Thierry Reding Define the table of memory controller hot resets for Tegra210. Signed-off-by: Thierry Reding --- drivers/memory/tegra/tegra210.c | 45 + 1 file changed, 45 insertions(+) diff --git

[PATCH v3 07/15] memory: tegra: Apply interrupts mask per SoC

faults which may be undesirable by newer generations. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/memory/tegra/mc.c | 21 +++-- drivers/memory/tegra/mc.h | 9 + drivers/memory/tegra/tegra114.c | 2 ++ drivers/memory/tegra/tegra124.

[PATCH v3 04/15] dt-bindings: memory: tegra: Add hot resets definitions

Add definitions for the Tegra20+ memory controller hot resets. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- include/dt-bindings/memory/tegra114-mc.h | 19 +++ include/dt-bindings/memory/tegra124-mc.h | 25 + include/dt-bindings/memory/tegra2

[PATCH v3 02/15] dt-bindings: memory: tegra: Document #reset-cells property of the Tegra30 MC

Memory Controller has a memory client "hot reset" functionality, which resets the DMA interface of a memory client. So MC is a reset controller in addition to IOMMU. Documentation the new property. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- .../devicetree/bindings/me

[PATCH v3 00/15] Memory controller hot reset

send of V1 with some minor changes. Dmitry Osipenko (14): dt-bindings: arm: tegra: Remove duplicated Tegra30+ MC binding dt-bindings: memory: tegra: Document #reset-cells property of the Tegra30 MC dt-bindings: arm: tegra: Document #reset-cells property of the Tegra20 MC dt-bindings: mem

[PATCH v3 06/15] memory: tegra: Setup interrupts mask before requesting IRQ

This avoids unwanted interrupt during MC driver probe. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/memory/tegra/mc.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index d2005b

[PATCH v3 09/15] memory: tegra: Squash tegra20-mc into common tegra-mc driver

Tegra30+ has some minor differences in registers / bits layout compared to Tegra20. Let's squash Tegra20 driver into the common tegra-mc driver in a preparation for the upcoming MC hot reset controls implementation, avoiding code duplication. Signed-off-by: Dmitry Osipenko <dig...@gmail.

[PATCH v3 12/15] memory: tegra: Add Tegra124 memory controller hot resets

Define the table of memory controller hot resets for Tegra124. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/memory/tegra/tegra124.c | 42 + 1 file changed, 42 insertions(+) diff --git a/drivers/memory/tegra/tegra124.c b/drivers/

[PATCH v3 03/15] dt-bindings: arm: tegra: Document #reset-cells property of the Tegra20 MC

Memory Controller has a memory client "hot reset" functionality, which resets the DMA interface of a memory client, so MC is a reset controller. Documentation the new property. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- .../devicetree/bindings/arm/tegra/nvidia,tegra20-

[PATCH v3 01/15] dt-bindings: arm: tegra: Remove duplicated Tegra30+ MC binding

There are two bindings for the same Memory Controller. One of the bindings became obsolete long time ago and probably was left unnoticed, remove it for consistency. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- .../bindings/arm/tegra/nvidia,tegra30-mc.txt

[PATCH v3 05/15] memory: tegra: Do not handle spurious interrupts

-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/memory/tegra/mc.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index a4803ac192bb..d2005b995821 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@

[PATCH v3 13/15] memory: tegra: Add Tegra114 memory controller hot resets

Define the table of memory controller hot resets for Tegra114. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/memory/tegra/tegra114.c | 33 + 1 file changed, 33 insertions(+) diff --git a/drivers/memory/tegra/tegra114.c b/drivers/memory

[PATCH v3 15/15] memory: tegra: Add Tegra20 memory controller hot resets

Define the table of memory controller hot resets for Tegra20 and add specific to Tegra20 hot reset operations. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/memory/tegra/tegra20.c | 118 + 1 file changed, 118 insertions(+) diff

[PATCH v3 10/15] memory: tegra: Introduce memory client hot reset

In order to reset busy HW properly, memory controller needs to be involved, otherwise it is possible to get corrupted memory or hang machine if HW was reset during DMA. Introduce memory client 'hot reset' that will be used for resetting of busy HW. Signed-off-by: Dmitry Osipenko <dig...@gmail.

[PATCH v3 14/15] memory: tegra: Add Tegra30 memory controller hot resets

Define the table of memory controller hot resets for Tegra30. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/memory/tegra/tegra30.c | 33 + 1 file changed, 33 insertions(+) diff --git a/drivers/memory/tegra/tegra30.c b/drivers/memory/tegra/t

Re: [PATCH v2 2/2] memory: tegra: Introduce memory client hot reset API

On 19.02.2018 15:35, Dmitry Osipenko wrote: > On 13.02.2018 14:24, Thierry Reding wrote: >> On Mon, Feb 12, 2018 at 08:06:31PM +0300, Dmitry Osipenko wrote: >>> In order to reset busy HW properly, memory controller needs to be >>> involved, otherwise it possible to

Re: [PATCH V15 06/22] mmc: block: Add blk-mq support

On 22.02.2018 10:42, Adrian Hunter wrote: > On 21/02/18 22:50, Dmitry Osipenko wrote: >> On 29.11.2017 16:41, Adrian Hunter wrote: >>> Define and use a blk-mq queue. Discards and flushes are processed >>> synchronously, but reads and writes asynchronously. In or

Re: [PATCH v2] ARM: tegra: fix ulpi regression on tegra20

backwards compatibility or even make clk driver to read the CDEV2 pinmux config and set the proper parent based on it. CC'ed Peter. Reviewed-by: Dmitry Osipenko <dig...@gmail.com> > --- > > Changes in v2: > - Updated device tree binding documentation as well. > - CCing Dmitry as we

Re: [PATCH V15 06/22] mmc: block: Add blk-mq support

On 29.11.2017 16:41, Adrian Hunter wrote: > Define and use a blk-mq queue. Discards and flushes are processed > synchronously, but reads and writes asynchronously. In order to support > slow DMA unmapping, DMA unmapping is not done until after the next request > is started. That means the request

Re: [PATCH v1 2/2] ARM: dts: tegra30: Add video decoder node

On 18.02.2018 21:03, Andreas Färber wrote: > Am 18.02.2018 um 18:01 schrieb Dmitry Osipenko: >> Add device tree node for the Video Decoder Engine found on Tegra30 SoC's. >> >> Signed-off-by: Dmitry Osipenko <dig...@gmail.com> >> --- >&g

[PATCH v1 2/2] ARM: dts: tegra30: Add video decoder node

Add device tree node for the Video Decoder Engine found on Tegra30 SoC's. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- arch/arm/boot/dts/tegra30.dtsi | 27 +++ 1 file changed, 27 insertions(+) diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/bo

[PATCH v1 0/2] Enable Video Decoder on Tegra30

VDE on Terga30 is compatible with VDE on Tegra20, hence the 'tegra-vde' driver works fine on Terga30. Let's add missing DT nodes to expose Video Decoder Engine on Terga30. Dmitry Osipenko (2): ARM: dts: tegra30: Add IRAM node ARM: dts: tegra30: Add video decoder node arch/arm/boot/dts

[PATCH v1 1/2] ARM: dts: tegra30: Add IRAM node

IRAM is a static RAM that consists of four contiguous 64 KiB blocks, it is currently used to store CPU resume code, utilized by the video decoder engine and could be used as a general-purpose fast memory. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- arch/arm/boot/dts/tegra30.dt

Re: [PATCH v3 2/5] drm/tegra: Restore opaque and drop alpha formats on Tegra20/30

On 20.12.2017 21:01, Thierry Reding wrote: > On Wed, Dec 20, 2017 at 06:46:11PM +0300, Dmitry Osipenko wrote: >> Commit 7772fdaef939 ("drm/tegra: Support ARGB and ABGR formats") broke >> DRM's MODE_ADDFB IOCTL on Tegra20/30, because IOCTL uses XRGB format if >&

Re: [PATCH v3 3/5] drm/tegra: Trade overlay plane for cursor on older Tegra's

On 20.12.2017 23:19, Thierry Reding wrote: > On Wed, Dec 20, 2017 at 06:46:12PM +0300, Dmitry Osipenko wrote: >> Older Tegra's do not support RGBA format for the cursor, but instead >> overlay plane could be used for it. Since there is no much use for the >> overlays on a r

Re: [PATCH v3 2/5] drm/tegra: Restore opaque and drop alpha formats on Tegra20/30

On 21.12.2017 17:10, Thierry Reding wrote: > On Thu, Dec 21, 2017 at 01:38:31AM +0300, Dmitry Osipenko wrote: >> On 21.12.2017 01:23, Dmitry Osipenko wrote: >>> On 21.12.2017 01:02, Thierry Reding wrote: >>>> On Thu, Dec 21, 2017 at 12:05:40AM +0300, Dmitry Osipenko

Re: [PATCH v3 2/5] drm/tegra: Restore opaque and drop alpha formats on Tegra20/30

On 21.12.2017 01:02, Thierry Reding wrote: > On Thu, Dec 21, 2017 at 12:05:40AM +0300, Dmitry Osipenko wrote: >> On 20.12.2017 23:16, Thierry Reding wrote: >>> On Wed, Dec 20, 2017 at 11:01:49PM +0300, Dmitry Osipenko wrote: >>>> On 20.12.2017 21:01, Thierry Redi

Re: [PATCH v3 2/5] drm/tegra: Restore opaque and drop alpha formats on Tegra20/30

On 21.12.2017 01:23, Dmitry Osipenko wrote: > On 21.12.2017 01:02, Thierry Reding wrote: >> On Thu, Dec 21, 2017 at 12:05:40AM +0300, Dmitry Osipenko wrote: >>> On 20.12.2017 23:16, Thierry Reding wrote: >>>> On Wed, Dec 20, 2017 at 11:01:49PM +0300, Dmitry Osipenko

Re: [PATCH v3 2/5] drm/tegra: Restore opaque and drop alpha formats on Tegra20/30

On 20.12.2017 23:16, Thierry Reding wrote: > On Wed, Dec 20, 2017 at 11:01:49PM +0300, Dmitry Osipenko wrote: >> On 20.12.2017 21:01, Thierry Reding wrote: >>> On Wed, Dec 20, 2017 at 06:46:11PM +0300, Dmitry Osipenko wrote: >>>> Commit 7772fdaef939 ("drm/t

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