On 10/22/18 6:33 PM, Stephen Warren wrote:
> On 10/21/18 2:54 PM, Dmitry Osipenko wrote:
>> Set min/max regulators voltage and add CPU node that hooks up CPU with
>> voltage regulators.
>
>> diff --git a/arch/arm/boot/dts/tegra20-harmony.dts
>> b/arch/ar
On 10/19/18 3:17 PM, Jon Hunter wrote:
>
> On 15/10/2018 14:52, Dmitry Osipenko wrote:
>> On 10/15/18 3:52 PM, Jon Hunter wrote:
>>>
>>> On 30/08/18 19:36, Dmitry Osipenko wrote:
>>>> This fixes splats like the one below if CONFIG_DEBUG_ATOMIC_SLEEP=y
&g
Add clock entry into the EMC DT node.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 526f623f201a..dcad6d6128cf 100644
--- a/arch/arm/boot/dts/tegra20
Move tegra20-emc binding to the memory-controllers directory for
consistency with the other Tegra memory bindings.
Signed-off-by: Dmitry Osipenko
Acked-by: Rob Herring
---
.../{arm/tegra => memory-controllers}/nvidia,tegra20-emc.txt | 0
1 file changed, 0 insertions(+), 0 deleti
Kernel should never gate the EMC clock as it causes immediate lockup, so
removing clk-gate functionality doesn't affect anything. Turning EMC clk
gate into divider allows to implement glitch-less EMC scaling, avoiding
reparenting to a backup clock.
Signed-off-by: Dmitry Osipenko
Acked-by: Peter
cleanups and fixes in the drivers code.
v2:
- Minor code cleanups like consistent use of writel_relaxed instead
of non-relaxed version, reworded error messages, etc.
- Factored out use_pllm_ud bit checking into a standalone patch for
consistency.
Dmitry Osipe
Ensure that direct PLLM sourcing is turned off for EMC as we don't support
that configuration in the clk driver.
Signed-off-by: Dmitry Osipenko
Acked-by: Peter De Schrijver
Acked-by: Stephen Boyd
---
drivers/clk/tegra/clk-tegra20.c | 10 ++
1 file changed, 10 insertions(+)
diff --git
Introduce driver for the External Memory Controller (EMC) found on Tegra20
chips, which controls the external DRAM on the board. The purpose of this
driver is to program memory timing for external memory on the EMC clock
rate change.
Signed-off-by: Dmitry Osipenko
Acked-by: Peter De Schrijver
Add interrupt entry into the EMC DT node.
Signed-off-by: Dmitry Osipenko
Acked-by: Peter De Schrijver
---
arch/arm/boot/dts/tegra20.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 20869757d32f..526f623f201a 100644
Embedded memory controller has a corresponding clock, document the clock
property.
Signed-off-by: Dmitry Osipenko
Acked-by: Rob Herring
---
.../devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt| 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings
EMC has a dedicated interrupt that is used to notify about completion of
HW operations. Document the interrupt property.
Signed-off-by: Dmitry Osipenko
Acked-by: Rob Herring
Acked-by: Peter De Schrijver
---
.../devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt| 2 ++
1 file changed
[] (call_cpuidle+0x30/0x48)
[] (call_cpuidle) from [] (do_idle+0x238/0x28c)
[] (do_idle) from [] (cpu_startup_entry+0x28/0x2c)
[] (cpu_startup_entry) from [] (rest_init+0xd8/0xdc)
[] (rest_init) from [] (start_kernel+0x41c/0x430)
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/pmc.c | 2 --
1
;
-
-put_pll_p:
- clk_put(cpufreq->pll_p_clk);
-put_pll_x:
- clk_put(cpufreq->pll_x_clk);
-put_cpu:
- clk_put(cpufreq->cpu_clk);
-
- return err;
}
-static int tegra20_cpufreq_remove(struct platform_device *pdev)
+static int tegra_cpufreq_remove(struct platform_device *pdev)
{
- struct tegra20_cpufreq *cpufreq = platform_get_drvdata(pdev);
+ struct tegra_cpufreq *cpufreq = platform_get_drvdata(pdev);
cpufreq_unregister_driver(>driver);
- clk_put(cpufreq->pll_p_clk);
- clk_put(cpufreq->pll_x_clk);
- clk_put(cpufreq->cpu_clk);
-
return 0;
}
-static struct platform_driver tegra20_cpufreq_driver = {
- .probe = tegra20_cpufreq_probe,
- .remove = tegra20_cpufreq_remove,
+static struct platform_driver tegra_cpufreq_driver = {
+ .probe = tegra_cpufreq_probe,
+ .remove = tegra_cpufreq_remove,
.driver = {
.name = "tegra20-cpufreq",
},
};
-module_platform_driver(tegra20_cpufreq_driver);
+module_platform_driver(tegra_cpufreq_driver);
+
+module_param(voltage_drop_interval_ms, uint, 0644);
MODULE_ALIAS("platform:tegra20-cpufreq");
MODULE_AUTHOR("Colin Cross ");
+MODULE_AUTHOR("Dmitry Osipenko ");
MODULE_DESCRIPTION("NVIDIA Tegra20 cpufreq driver");
MODULE_LICENSE("GPL");
--
2.19.0
Set min/max regulators voltage and add CPU node that hooks up CPU with
voltage regulators.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20-paz00.dts | 31 -
1 file changed, 22 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20-paz00
Set min/max regulators voltage and add CPU node that hooks up CPU with
voltage regulators.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra30-apalis.dtsi | 19 ---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi
b
Set min/max regulators voltage and add CPU node that hooks up CPU with
voltage regulators.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20-tamonten.dtsi | 31 ++---
1 file changed, 22 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20
Add CPU's Operating Performance Points to the device tree, they are used
by the CPUFreq driver and allow to setup thermal throttling for the boards
by linking the cooling device (CPU) with thermal sensors via thermal-zones
description.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts
Add device-tree binding that describes CPU frequency-scaling hardware
found on NVIDIA Tegra20/30 SoC's.
Signed-off-by: Dmitry Osipenko
---
.../cpufreq/nvidia,tegra20-cpufreq.txt| 96 +++
1 file changed, 96 insertions(+)
create mode 100644
Documentation/devicetree
]
https://nv-tegra.nvidia.com/gitweb/?p=linux-2.6.git;a=blob;f=arch/arm/mach-tegra/tegra2_dvfs.c;hb=l4t/l4t-r16-r2
[3]
https://nv-tegra.nvidia.com/gitweb/?p=linux-2.6.git;a=blob;f=arch/arm/mach-tegra/tegra3_dvfs.c;hb=l4t/l4t-r16-r2
Dmitry Osipenko (17):
OPP: Allow to request stub voltage regula
Set min/max regulators voltage and add CPU node that hooks up CPU with
voltage regulators.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20-harmony.dts | 31 +++
1 file changed, 22 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20
Set min/max regulators voltage and add CPU node that hooks up CPU with
voltage regulators.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20-ventana.dts | 31 +++
1 file changed, 22 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20
Add CPU's Operating Performance Points to the device tree, they are used
by the CPUFreq driver and allow to setup thermal throttling for the boards
by linking the cooling device (CPU) with thermal sensors via thermal-zones
description.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts
Set min/max regulators voltage and add CPU node that hooks up CPU with
voltage regulators.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra30-colibri.dtsi | 19 ---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi
b
Set min/max regulators voltage and add CPU node that hooks up CPU with
voltage regulators.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra30-beaver.dts | 19 ---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts
b
Set min/max regulators voltage and add CPU node that hooks up CPU with
voltage regulators.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20-seaboard.dts | 27 +++---
1 file changed, 20 insertions(+), 7 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20
Set min/max regulators voltage and add CPU node that hooks up CPU with
voltage regulators.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra30-cardhu.dtsi | 19 ---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi
b
Set min/max regulators voltage and add CPU node that hooks up CPU with
voltage regulators.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20-colibri.dtsi | 31 ++
1 file changed, 22 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20
Voltage regulators may be not available on some variations of HW, allow to
request stub voltage regulators by OPP core in a such case to reduce code
churning within drivers.
Signed-off-by: Dmitry Osipenko
---
drivers/cpufreq/cpufreq-dt.c | 2 +-
drivers/cpufreq/ti-cpufreq.c | 3 ++-
drivers/opp
This function is used by tegra20-cpufreq driver which can be built as a
kernel module.
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/fuse/tegra-apbmisc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/tegra/fuse/tegra-apbmisc.c
b/drivers/soc/tegra/fuse/tegra-apbmisc.c
Tegra20-cpufreq driver require a platform device in order to be loaded,
instantiate a simple platform device for the driver during of the machines
late initialization. Driver now supports Tegra30 SoC's, hence create the
device on Tegra30 machines.
Signed-off-by: Dmitry Osipenko
---
arch/arm
On 10/21/18 11:54 PM, Dmitry Osipenko wrote:
> This function is used by tegra20-cpufreq driver which can be built as a
> kernel module.
>
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/soc/tegra/fuse/tegra-apbmisc.c | 1 +
> 1 file changed, 1 insertion(+)
>
> dif
On 10/17/18 10:29 PM, Jon Hunter wrote:
>
> On 17/10/2018 15:43, Dmitry Osipenko wrote:
>> On 10/17/18 5:14 PM, Jon Hunter wrote:
>>>
>>> On 17/10/2018 14:46, Dmitry Osipenko wrote:
>>>> On 10/17/18 4:34 PM, Jon Hunter wrote:
>>>>>
>>
On 10/17/18 10:41 PM, Jon Hunter wrote:
>
> On 17/10/2018 15:30, Dmitry Osipenko wrote:
>> On 10/17/18 4:59 PM, Jon Hunter wrote:
>>>
>>> On 13/05/2018 22:13, Dmitry Osipenko wrote:
>>>> Nothing prevents I2C clients to access I2C while Tegra's dr
On 10/17/18 12:54 PM, Jon Hunter wrote:
>
> On 17/10/2018 09:49, Jon Hunter wrote:
>>
>> On 30/08/2018 20:43, Dmitry Osipenko wrote:
>>> Tegra20-cpufreq driver require a platform device in order to be loaded,
>>> instantiate a simple platform device for the dr
On 10/17/18 1:59 PM, Marcel Ziswiler wrote:
> On Fri, 2018-08-31 at 12:29 +0300, Peter De Schrijver wrote:
>> On Thu, Aug 30, 2018 at 09:42:10PM +0300, Dmitry Osipenko wrote:
>>> Currently all PLL's on Tegra20 use a hardcoded delay despite of
>>> having
>>>
On 8/31/18 12:45 PM, Dmitry Osipenko wrote:
> On 8/31/18 12:29 PM, Peter De Schrijver wrote:
>> On Thu, Aug 30, 2018 at 09:42:10PM +0300, Dmitry Osipenko wrote:
>>> Currently all PLL's on Tegra20 use a hardcoded delay despite of having
>>> a lock-status bit. The lock-sta
On 10/17/18 11:59 AM, Jon Hunter wrote:
>
> On 30/08/2018 20:20, Dmitry Osipenko wrote:
>> Add more predefined rates to the PLLX table, allowing to lower the rate
>> down to 312MHz. This gives more variations of frequency selection to the
>> CPUFREQ driver.
>
> I
On 10/17/18 11:53 AM, Jon Hunter wrote:
>
> On 30/08/2018 20:20, Dmitry Osipenko wrote:
>> Some of the CCLKG parents aren't accessible via device tree because they
>> are created as non-DT clocks. Apparently there is no reason to define
>> these clocks in that manner,
On 10/17/18 4:34 PM, Jon Hunter wrote:
>
> On 17/10/2018 14:07, Dmitry Osipenko wrote:
>> On 10/17/18 3:59 PM, Jon Hunter wrote:
>>>
>>> On 17/10/2018 13:37, Dmitry Osipenko wrote:
>>>> On 10/17/18 11:40 AM, Jon Hunter wrote:
>>>>>
>
On 10/17/18 11:40 AM, Jon Hunter wrote:
>
> On 30/08/2018 20:43, Dmitry Osipenko wrote:
>> Add device-tree binding that describes CPU frequency-scaling hardware
>> found on NVIDIA Tegra20/30 SoC's.
>>
>> Signed-off-by: Dmitry Osipenko
>> ---
>> .../cpuf
On 10/17/18 3:37 PM, Dmitry Osipenko wrote:
> On 10/17/18 11:40 AM, Jon Hunter wrote:
>>
>> On 30/08/2018 20:43, Dmitry Osipenko wrote:
>>> Add device-tree binding that describes CPU frequency-scaling hardware
>>> found on NVIDIA Tegra20/30 SoC's.
>&
On 10/17/18 4:25 PM, Rob Herring wrote:
> On Fri, Oct 05, 2018 at 06:36:32PM +0300, Dmitry Osipenko wrote:
>> Redefine binding for regulator-coupled-max-spread property in a way that
>> max-spread values are defined per regulator couple instead of defining
>> single max-sprea
On 10/17/18 3:59 PM, Jon Hunter wrote:
>
> On 17/10/2018 13:37, Dmitry Osipenko wrote:
>> On 10/17/18 11:40 AM, Jon Hunter wrote:
>>>
>>> On 30/08/2018 20:43, Dmitry Osipenko wrote:
>>>> Add device-tree binding that describes CPU frequency-scaling hard
On 10/17/18 4:33 PM, Rob Herring wrote:
> On Wed, Oct 17, 2018 at 8:32 AM Dmitry Osipenko wrote:
>>
>> On 10/17/18 4:25 PM, Rob Herring wrote:
>>> On Fri, Oct 05, 2018 at 06:36:32PM +0300, Dmitry Osipenko wrote:
>>>> Redefine binding for regulator-
On 10/17/18 4:59 PM, Jon Hunter wrote:
>
> On 13/05/2018 22:13, Dmitry Osipenko wrote:
>> Nothing prevents I2C clients to access I2C while Tegra's driver is being
>> suspended, this results in -EBUSY error returned to the clients and that
>> may have unfortunate con
On 10/17/18 5:14 PM, Jon Hunter wrote:
>
> On 17/10/2018 14:46, Dmitry Osipenko wrote:
>> On 10/17/18 4:34 PM, Jon Hunter wrote:
>>>
>>> On 17/10/2018 14:07, Dmitry Osipenko wrote:
>>>> On 10/17/18 3:59 PM, Jon Hunter wrote:
>>>>>
>>
On 10/24/18 1:20 PM, Jon Hunter wrote:
>
> On 21/10/2018 19:36, Dmitry Osipenko wrote:
>> This fixes splats like the one below if CONFIG_DEBUG_ATOMIC_SLEEP=y
>> and machine (Tegra30) booted with SMP=n or all secondary CPU's are put
>> offline. Locking isn't needed be
On 10/24/18 1:49 PM, Jon Hunter wrote:
>
> On 22/10/2018 12:19, Dmitry Osipenko wrote:
>> On 10/22/18 12:52 PM, Thierry Reding wrote:
>>> On Fri, Oct 19, 2018 at 02:22:53PM +0100, Jon Hunter wrote:
>>>> From: Jonathan Hunter
>>>>
>>>> T
On 10/24/18 9:41 AM, Viresh Kumar wrote:
> On 22-10-18, 15:12, Dmitry Osipenko wrote:
>> Because there is one Tegra20 board (tegra20-trimslice) that doesn't declare
>> necessary regulators, but we want to have CPU frequency scaling. I couldn't
>> find board schematics and
On 10/26/18 6:37 PM, Lucas Stach wrote:
> Am Freitag, den 26.10.2018, 15:03 +0300 schrieb Dmitry Osipenko:
> [...]
>>> On the other hand, the tegra20 cpufreq driver is common across a lot of
>>> boards.
>>> What will happen if the DT for some of th
On 10/29/18 9:53 AM, Viresh Kumar wrote:
> On 26-10-18, 15:03, Dmitry Osipenko wrote:
>> On 10/24/18 9:41 AM, Viresh Kumar wrote:
>>> On 22-10-18, 15:12, Dmitry Osipenko wrote:
>>>> Because there is one Tegra20 board (tegra20-trimslice) that doesn't declare
>>
On 10/24/18 5:19 PM, Jon Hunter wrote:
>
> On 24/10/2018 13:44, Dmitry Osipenko wrote:
>> On 10/24/18 1:49 PM, Jon Hunter wrote:
>>>
>>> On 22/10/2018 12:19, Dmitry Osipenko wrote:
>>>> On 10/22/18 12:52 PM, Thierry Reding wrote:
>>>>> O
On 10/25/18 5:38 PM, Thierry Reding wrote:
> On Sun, Oct 21, 2018 at 09:30:52PM +0300, Dmitry Osipenko wrote:
>> Introduce driver for the External Memory Controller (EMC) found on Tegra20
>> chips, which controls the external DRAM on the board. The purpose of this
>> driver
gt; Prevent the tps6586x interrupt handler from executing on exiting suspend
> before the i2c controller has been resumed by disabling the tps6586x
> interrupt on entering suspend and re-enabling it on resuming from
> suspend.
>
> Cc: sta...@vger.kernel.org
>
> Signed-off-by: Jon
On 06.11.2018 9:31, Sasha Levin wrote:
> On Mon, Nov 05, 2018 at 02:05:49PM +, Marcel Ziswiler wrote:
>> On Fri, 2018-11-02 at 22:02 -0400, Sasha Levin wrote:
>>> On Fri, Nov 02, 2018 at 07:56:57PM +, Sudip Mukherjee wrote:
>>> > Hi Greg,
>>> >
>>> > On Fri, Nov 2, 2018 at 6:53 PM Greg
On 06.11.2018 0:30, Rob Herring wrote:
> On Sun, Oct 21, 2018 at 11:54:47PM +0300, Dmitry Osipenko wrote:
>> Add device-tree binding that describes CPU frequency-scaling hardware
>> found on NVIDIA Tegra20/30 SoC's.
>>
>> Signed-off-by: Dmitry Osipenko
>> -
On 08.11.2018 16:07, Mark Brown wrote:
> On Fri, Oct 05, 2018 at 06:36:37PM +0300, Dmitry Osipenko wrote:
>
>> Wait/wound mutex shall be used in order to avoid lockups on locking of
>> coupled regulators.
>
> This breaks the build due to a few of the drivers (wm8350 and d
eturn -EPROBE_DEFER
> till parent clock appears.
>
> Signed-off-by: Dmitry Osipenko
> Acked-by: Peter De Schrijver
> Signed-off-by: Thierry Reding
> Signed-off-by: Sasha Levin
> ---
[snip]
Hello Greg,
You should either pick up c59487075659 in addition or don't backport an
On 10/8/18 8:58 PM, Tony Lindgren wrote:
> * Dmitry Osipenko [181005 15:43]:
>> 1. Re-worked the original "Add voltage balancing mechanism" patch from
>>Maciej by:
>> 1) Fixing infinite loop within regulator_balance_voltage().
>>
On 9/29/18 1:41 AM, Tony Lindgren wrote:
> * Dmitry Osipenko [180928 22:31]:
>> On 9/28/18 11:22 PM, Tony Lindgren wrote:
>>> * Dmitry Osipenko [180928 20:13]:
>>>> Tony, could you please give a try to the patch below?
>>>>
>>&
On 9/28/18 11:22 PM, Tony Lindgren wrote:
> * Dmitry Osipenko [180928 20:13]:
>> Tony, could you please give a try to the patch below?
>>
>> Do the following:
>>
>> 1) git cherry-pick 696861761a58d8c93605b5663824929fb6540f16
>> 2) git cherry-pick 456e7c
On 9/29/18 2:17 AM, Dmitry Osipenko wrote:
> On 9/29/18 1:41 AM, Tony Lindgren wrote:
>> * Dmitry Osipenko [180928 22:31]:
>>> On 9/28/18 11:22 PM, Tony Lindgren wrote:
>>>> * Dmitry Osipenko [180928 20:13]:
>>>>> Tony, could you please give a try to
On 9/29/18 3:27 AM, Tony Lindgren wrote:
> * Dmitry Osipenko [180928 23:55]:
>> On 9/29/18 2:17 AM, Dmitry Osipenko wrote:
>>> On 9/29/18 1:41 AM, Tony Lindgren wrote:
>>>> I'm still getting these errors after init:
>>>
>>> Thank you very muc
desired".
Tony, could you please give a try to the patch below?
Do the following:
1) git cherry-pick 696861761a58d8c93605b5663824929fb6540f16
2) git cherry-pick 456e7cdf3b1a14e2606b8b687385ab2e3f23a49a
3) Apply this patch:
>From 7928aecb3af9d367dd3c085972349aaa16318c1b Mon Sep 17 00:
On 9/28/18 11:22 PM, Tony Lindgren wrote:
> * Dmitry Osipenko [180928 20:13]:
>> Tony, could you please give a try to the patch below?
>>
>> Do the following:
>>
>> 1) git cherry-pick 696861761a58d8c93605b5663824929fb6540f16
>> 2) git cherry-pick 456e7c
On 10/1/18 10:25 AM, Maciej Purski wrote:
> Hi all,
> unfortunately, I don't work at kernel anymore. That would be great, if you
> could take over those patches and finish the
> work.
Hello Maciej,
I'll take care of the patches and try to push them forward, thank you.
On Monday 03 September 2018 11:01:11 Peter De Schrijver wrote:
> On Fri, Aug 31, 2018 at 12:45:17PM +0300, Dmitry Osipenko wrote:
> > On 8/31/18 12:29 PM, Peter De Schrijver wrote:
> > > On Thu, Aug 30, 2018 at 09:42:10PM +0300, Dmitry Osipenko wrote:
> > >> Curr
On 9/24/18 1:02 PM, Thierry Reding wrote:
On Mon, Sep 24, 2018 at 03:41:42AM +0300, Dmitry Osipenko wrote:
The tegra20-mc device-tree binding has been changed, GART has been
squashed into Memory Controller and now the clock property is mandatory
for Tegra20, the DT compatible has been changed
On 9/22/18 1:01 AM, ryang wrote:
> The current behavior is that clk_round_rate would return the same clock
> rate passed to it for valid PLL configurations. This change will return
> the exact rate the PLL will provide in accordance with clk API.
>
> Signed-off-by: ryang
A minor comment.. [0]
On 9/25/18 10:36 PM, Rob Herring wrote:
> On Tue, Sep 25, 2018 at 12:29 PM Dmitry Osipenko wrote:
>>
>> On 9/25/18 7:58 PM, Rob Herring wrote:
>>> On Thu, Aug 30, 2018 at 10:43:52PM +0300, Dmitry Osipenko wrote:
>>>> Add device-tree binding that describes CPU f
On 4/23/18 5:33 PM, Maciej Purski wrote:
> Hi all,
>
> this patchset adds a new mechanism to the framework - regulators' coupling.
>
> On Odroid XU3/4 and other Exynos5422 based boards there is a case, that
> different devices on the board are supplied by different regulators
> with non-fixed
On 9/25/18 7:58 PM, Rob Herring wrote:
> On Thu, Aug 30, 2018 at 10:43:52PM +0300, Dmitry Osipenko wrote:
>> Add device-tree binding that describes CPU frequency-scaling hardware
>> found on NVIDIA Tegra20/30 SoC's.
>>
>> Signed-off-by: Dmitry Osipenko
>> -
On 9/25/18 1:00 PM, Thierry Reding wrote:
> On Mon, Sep 24, 2018 at 09:39:43PM +0300, Dmitry Osipenko wrote:
>> On 9/24/18 1:13 PM, Thierry Reding wrote:
>>> On Mon, Sep 24, 2018 at 03:41:44AM +0300, Dmitry Osipenko wrote:
>>>> There is no need to match device with th
Wait/wound mutex shall be used in order to avoid lockups on locking of
coupled regulators.
Signed-off-by: Dmitry Osipenko
Suggested-by: Lucas Stach
---
drivers/regulator/core.c | 403 +++---
drivers/regulator/da9210-regulator.c | 4 +-
drivers/regulator
It's unlikely that regulators may disappear/appear while regulators
debug-summary is being prepared, but let's be consistent and avoid that
situation.
Signed-off-by: Dmitry Osipenko
---
drivers/regulator/core.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers
= < >;
regulator-coupled-max-spread = <30 20>;
};
Note that the regulator-coupled-max-spread property does not have any
users yet, hence it's okay to change the binding.
Signed-off-by: Dmitry Osipenko
---
v2: Added note to the commit description, saying that the
any users yet. That was requested by Rob Herring
in the review comment to v1.
[0] https://patchwork.ozlabs.org/project/linux-tegra/list/?series=69250
Dmitry Osipenko (3):
regulator: core: Use ww_mutex for regulators locking
regulator: core: Properly handle case where supply is the couple
regu
Check whether supply regulator is the couple to avoid infinite recursion
during of locking.
Signed-off-by: Dmitry Osipenko
---
drivers/regulator/core.c | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
On 30.08.2018 21:54, Dmitry Osipenko wrote:
> Hello,
>
> This patch series fixes couple bugs in the memory self-refresh code.
> The EMC / MC state is properly restored after patches being applied,
> please review.
>
> Dmitry Osipenko (4):
> ARM: tegra: Fix misse
On 23.11.2018 17:24, Philippe Schenker wrote:
> From: Philippe Schenker
>
> Activate the stmpe-adc driver as found on Apalis/Colibri iMX6/T30 modules
>
> Signed-off-by: Philippe Schenker
Hello Philippe,
Just a very minor comment.. device trees are not for drivers, but for HW
description. It
On 20.11.2018 1:09, Dmitry Osipenko wrote:
> On 20.11.2018 0:34, Jon Hunter wrote:
>>
>> On 30/08/2018 19:54, Dmitry Osipenko wrote:
>>> The DRAM refresh-interval is getting erroneously set to "1" on exiting
>>> from memory self-refreshing mode. The
rdev_err(rdev,
> - "Supply disable failed: %d\n", ret);
> - }
> - }
> - }
> }
>
> /**
>
Good catch!
Reviewed-by: Dmitry Osipenko
This fixes compiling regulator drivers that use these function when
these drivers are built as kernel modules.
Fixes: f8702f9e4aa7 ("regulator: core: Use ww_mutex for regulators locking")
Signed-off-by: Dmitry Osipenko
---
drivers/regulator/core.c | 2 ++
1 file changed, 2 insertion
On 20.11.2018 3:49, Stephen Rothwell wrote:
> Hi all,
>
> After merging the regulator tree, today's linux-next build (x86_64
> allmodconfig) failed like this:
>
> ERROR: "regulator_lock" [drivers/regulator/wm8350-regulator.ko] undefined!
> ERROR: "regulator_unlock"
On 20.11.2018 0:26, Jon Hunter wrote:
>
> On 19/11/2018 17:05, Dmitry Osipenko wrote:
>> On 19.11.2018 18:42, Jon Hunter wrote:
>>>
>>> On 18/11/2018 22:06, Dmitry Osipenko wrote:
>>>> On 30.08.2018 21:54, Dmitry Osipenko wrote:
>>>>&g
On 20.11.2018 0:34, Jon Hunter wrote:
>
> On 30/08/2018 19:54, Dmitry Osipenko wrote:
>> The DRAM refresh-interval is getting erroneously set to "1" on exiting
>> from memory self-refreshing mode. The clobbered interval causes the
>> "refresh request overflo
On 20.11.2018 1:00, Jon Hunter wrote:
>
> On 30/08/2018 19:54, Dmitry Osipenko wrote:
>> Two interrupts are raised on resume from LP1 on Tegra30+: first is the
>> clock change completed interrupt which is set after updating timing
>> configuration, second is DLL alarm int
On 20.11.2018 3:26, Douglas Anderson wrote:
> In regulator_force_disable() there was a strange loop that looked like:
>
> while (rdev->open_count--)
> regulator_disable(rdev->supply);
>
> I'm not totally sure what the goal was for this loop, but it seems
> wrong to me. If anything I think
n accordance with clk API.
>>
>> Signed-off-by: Robert Yang
>> ---
>
> I'm waiting for someone from Nvidia/Tegra background to review this
> change.
>
Apparently Peter is taking a pause. I think Thierry's ACK to V1 should be still
valid here.
Also, if this help
; complete(_dev->msg_complete);
> done:
> - spin_unlock_irqrestore(_dev->xfer_lock, flags);
> + spin_unlock(_dev->xfer_lock);
> return IRQ_HANDLED;
> }
>
>
Reviewed-by: Dmitry Osipenko
On 20.11.2018 13:27, Jon Hunter wrote:
>
> On 19/11/2018 22:35, Dmitry Osipenko wrote:
>> On 20.11.2018 1:00, Jon Hunter wrote:
>>>
>>> On 30/08/2018 19:54, Dmitry Osipenko wrote:
>>>> Two interrupts are raised on resume from LP1 on Tegra30+: first is
On 20.11.2018 13:26, Jon Hunter wrote:
>
> On 19/11/2018 22:32, Dmitry Osipenko wrote:
>> On 20.11.2018 1:09, Dmitry Osipenko wrote:
>>> On 20.11.2018 0:34, Jon Hunter wrote:
>>>>
>>>> On 30/08/2018 19:54, Dmitry Osipenko wrote:
>>>>>
On 19.11.2018 18:42, Jon Hunter wrote:
>
> On 18/11/2018 22:06, Dmitry Osipenko wrote:
>> On 30.08.2018 21:54, Dmitry Osipenko wrote:
>>> Hello,
>>>
>>> This patch series fixes couple bugs in the memory self-refresh code.
>>> The EMC / MC state
Trace points are much more efficient than debug messages for intensive
tracing and could be conveniently enabled / disabled dynamically, hence
let's replace debug messages with the trace points. This also makes
code a bit cleaner.
Signed-off-by: Dmitry Osipenko
---
Changelog:
v3
On 9/11/18 11:27 AM, Marcel Ziswiler wrote:
On Fri, 2018-09-07 at 19:59 +0300, Dmitry Osipenko wrote:
- snip -
- With "cpufreq-info -f" I could only observe like the top 3-4 OPPs
while it does not to go further down even when idling. Why could
that
be resp. what could cause th
Use device_init_wakeup() instead of device_set_wakeup_capable() and move it
before rtc dev registering. This fixes issue with alarmtimer that checks wakeup
capability with device_may_wakeup() on device add.
Signed-off-by: Dmitry Osipenko
---
drivers/rtc/rtc-tps6586x.c | 3 ++-
1 file changed, 2
Add guard to check whether RGB output is already enabled in the way it's
done for HDMI output. Fixes possible hang on trying to disable output twice
(first time during driver probe and second on fb registering).
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/rgb.c | 11 +++
1
11.02.2014 23:13, Erik Faye-Lund пишет:
> On Tue, Feb 11, 2014 at 6:12 PM, Dmitry Osipenko wrote:
>> Add guard to check whether RGB output is already enabled in the way it's
>> done for HDMI output. Fixes possible hang on trying to disable output twice
>> (first tim
Use device_init_wakeup() instead of device_set_wakeup_capable() and move it
before rtc dev registering. This fixes alarmtimer not registered when tps6586x
rtc is the only wakeup compatible rtc in the system.
Signed-off-by: Dmitry Osipenko
---
V2: changed description
drivers/rtc/rtc-tps6586x.c
23.05.2013 02:22, Andrew Morton пишет:
> On Sun, 12 May 2013 18:25:06 +0400 Dmitry Osipenko wrote:
>
>> Use device_init_wakeup() instead of device_set_wakeup_capable() and move it
>> before rtc dev registering. This fixes issue with alarmtimer that checks
>&
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