On 18/09/2013 12:01, Maxime COQUELIN wrote:
> This patch adds support to SSC (Synchronous Serial Controller)
> I2C driver. This IP also supports SPI protocol, but this is not
> the aim of this driver.
>
> This IP is embedded in all ST SoCs for Set-top box platorms, and
> supports I2C Standard and F
From: Gabriel Fernandez
Theses patches enable ccu8540 pintctrl DT for uart and i2c
Modifications from first version:
- supress &pinctrl_dbx500 phandle.
- add pintctrl { compatible = "stericsson,db8540-pinctrl"; ...
- cosmetics.
Gabriel Fernandez (2):
A
From: Gabriel Fernandez
This patch adds pinctrl device tree settings for uart0 and uart2
for ccu8540 board.
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/ccu8540-pinctrl.dtsi | 81 +
arch/arm/boot/dts/ccu8540.dts | 11
arch/arm/boot/dts
From: Gabriel Fernandez
This patch configures pin map in device tree of i2c0,
1,2,4 & 5 for ccu8540 board.
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/ccu8540-pinctrl.dtsi | 115 +
arch/arm/boot/dts/ccu8540.dts | 34 ++
2 f
From: Gabriel Fernandez
This patch set introduces a new board for u8540 platform: ccu8540-uib-v3.
Gabriel Fernandez (4):
ARM: ux540: Add ccu8540-uib-v3 Device Tree Machine
ARM: u8540: Add device tree support for lp5521 leds
ARM: u8540: Add device tree support for bh1780
ARM: u8540
From: Gabriel Fernandez
This patch adds DT probing of lp5521 leds for u8540.
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/ccu8540-uib-v3.dts | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/boot/dts/ccu8540-uib-v3.dts
b/arch/arm/boot/dts/ccu8540
From: Gabriel Fernandez
This patch adds DT probing of the light sensor bh1780
for u8540.
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/ccu8540-uib-v3.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/ccu8540-uib-v3.dts
b/arch/arm/boot/dts/ccu8540-uib-v3
From: Gabriel Fernandez
Here we ensure the SFH7741 Proximity Sensor is registered through
gpio-keys when booting with Device Tree enabled.
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/ccu8540-uib-v3.dts | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm
From: Gabriel Fernandez
This board includes the U8540 platform and specifies only the
ST-Ericsson UIB version 3.
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/ccu8540-uib-v3.dts | 16
2 files changed, 17 insertions(+)
create mode 100644 arch/arm/boot/dts
On 29 May 2013 17:50, Lee Jones wrote:
> On Wed, 29 May 2013, Gabriel Fernandez wrote:
>
>> From: Gabriel Fernandez
>>
>> This board includes the U8540 platform and specifies only the
>> ST-Ericsson UIB version 3.
>
> I'm confused by this.
>
> Is it
From: Gabriel Fernandez
This patch adds pinctrl device tree settings for uart0 and uart2
for ccu8540 board.
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/ccu8540-pinctrl.dtsi | 77
arch/arm/boot/dts/ccu8540.dts | 7 +++
arch/arm/boot/dts
From: Gabriel Fernandez
Theses patches enable ccu8540 pintctrl DT for uart and i2c
Gabriel Fernandez (3):
ARM: ux500: use #include syntax to include *.dtsi.
ARM: u8540: Add Pinctrl Device Tree settings for uart0, uart2
ARM: u8540: DT: Set pinctrl mapping to i2c0,1,2,4 & 5
arch/arm/
From: Gabriel Fernandez
This patch prepares the use of '#define' into dts files.
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/ccu8540.dts | 2 +-
arch/arm/boot/dts/ccu9540.dts | 2 +-
arch/arm/boot/dts/dbx5x0.dtsi | 2 +-
arch/arm/boot/dts/href.dtsi |
From: Gabriel Fernandez
This patch configures pin map in device tree of i2c0,
1,2,4 & 5 for ccu8540 board.
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/ccu8540-pinctrl.dtsi | 115 +
arch/arm/boot/dts/ccu8540.dts | 30 +
2 f
On 28 May 2013 12:09, Lee Jones wrote:
> On Mon, 27 May 2013, Gabriel Fernandez wrote:
>
>> From: Gabriel Fernandez
>>
>> This patch adds pinctrl device tree settings for uart0 and uart2
>> for ccu8540 board.
>>
>> Signed-off-by: Gabriel Ferna
On 28 May 2013 12:12, Lee Jones wrote:
> On Mon, 27 May 2013, Gabriel Fernandez wrote:
>
>> From: Gabriel Fernandez
>>
>> This patch configures pin map in device tree of i2c0,
>> 1,2,4 & 5 for ccu8540 board.
>>
>> Signed-off-by: Gabriel F
On 27 May 2013 15:30, Gabriel Fernandez wrote:
> From: Gabriel Fernandez
>
> This patch adds pinctrl device tree settings for uart0 and uart2
> for ccu8540 board.
>
> Signed-off-by: Gabriel Fernandez
> ---
> arch/arm/boot/dts/ccu8540-pinctrl.dtsi | 77
: Maxime Coquelin
Signed-off-by: Gabriel Fernandez
---
drivers/reset/Makefile | 1 +
drivers/reset/reset-stm32.c | 113
2 files changed, 114 insertions(+)
create mode 100644 drivers/reset/reset-stm32.c
diff --git a/drivers/reset/Makefile b
Hi Rob,
On 19 June 2016 at 17:04, Rob Herring wrote:
> On Thu, Jun 16, 2016 at 11:20:22AM +0200, Gabriel Fernandez wrote:
>> This patch reworks the clock binding to avoid too much detail in DT.
>> Now we have only compatible string per type of clock
>> (remark from Rob https
On 09/14/2016 08:36 PM, Stephen Boyd wrote:
On 08/29, gabriel.fernan...@st.com wrote:
From: Gabriel Fernandez
v3:
- Rebase to v4.8-rc1
- Tipo fix in st,clkgen-pll.txt
- Add Ack of Peter for the series
- Add missed patch: "ARM: DT: STiH4xx: Simplify clock binding of ST
On 08/25/2016 02:11 AM, Michael Turquette wrote:
Quoting Gabriel Fernandez (2016-08-22 09:06:20)
Hi Mike,
you forgot me ?
Best Regards
Gabriel
On 07/11/2016 08:58 AM, Gabriel Fernandez wrote:
On 07/08/2016 06:08 PM, Michael Turquette wrote:
Quoting Gabriel Fernandez (2016-07-08 02:12
controller.
It's based on designware PCIe driver.
Gabriel Fernandez (3):
ARM: STi: Kconfig update for PCIe support
PCI: st: Add Device Tree bindings for sti pcie
PCI: st: Provide support for the sti PCIe controller
Documentation/devicetree/bindings/pci/st-p
Update Kconfig:
- MIGHT_HAVE_PCI
- PCI_DOMAINS
Signed-off-by: Fabrice Gasnier
---
arch/arm/mach-sti/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig
index 125865d..5f99e93 100644
--- a/arch/arm/mach-sti/Kconfig
+++ b/arch/arm/mac
sti pcie is built around a Synopsis Designware PCIe IP.
Signed-off-by: Fabrice Gasnier
Signed-off-by: Gabriel Fernandez
Reviewed-by: Pratyush Anand
---
MAINTAINERS | 1 +
drivers/pci/host/Kconfig | 9 +
drivers/pci/host/Makefile | 1 +
drivers/pci/host/pci-st.c | 587
sti pcie is built around a Synopsis Designware PCIe IP.
Signed-off-by: Fabrice Gasnier
Signed-off-by: Gabriel Fernandez
---
Documentation/devicetree/bindings/pci/st-pcie.txt | 56 +++
1 file changed, 56 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci
Hi Stephen,
No there is no reason. I will fix it.
Thanks for review.
Best regards
Gabriel
On 6 October 2015 at 20:06, Stephen Boyd wrote:
> On 10/05, Gabriel Fernandez wrote:
>> @@ -452,7 +651,7 @@ static const struct clk_ops st_pll1200c32_ops = {
>> static stru
Add support for new PLL-type for stih418 A9-PLL.
Currently the 407_A9_PLL type being used, it is corrected with this patch
4600c28 PLL allows to reach higher frequencies
so its programming algorithm is extended.
Signed-off-by: Pankaj Dev
Signed-off-by: Gabriel Fernandez
---
.../devicetree
Change A9 PLL rate, as per requirement from the cpufreq framework,
for DVFS. For rate change, the A9 clock needs to be temporarily sourced
from PLL external to A9 and then sourced back to A9-PLL
Signed-off-by: Pankaj Dev
Signed-off-by: Gabriel Fernandez
---
drivers/clk/st/clkgen-mux.c | 3
- Add patch to enable stih418 A9 pll via DT.
This patchset is based on '[PATCH 0/2] ST PLL fixes for 4.3'
Gabriel Fernandez (4):
drivers: clk: st: Support for enable/disable in Clockgen PLLs
drivers: clk: st: PLL rate change implementation for DVFS
drivers: clk: st: Correct the pl
Add support for new PLL-type for stih418 A9-PLL.
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/stih418-clock.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi
b/arch/arm/boot/dts/stih418-clock.dtsi
index 148e177..ae6d997
The patch adds support for enable/disable of the Clockgen PLLs.
clkgen_pll_enable/clkgen_pll_disable added as generic function for all PLLs.
Signed-off-by: Pankaj Dev
Signed-off-by: Gabriel Fernandez
---
drivers/clk/st/clkgen-pll.c | 60 -
1 file
Hi Russell
no problem, i will fix it
Thanks for review.
BR
Gabriel
On 6 October 2015 at 21:01, Russell King - ARM Linux
wrote:
> On Tue, Oct 06, 2015 at 09:56:06AM +0200, Gabriel Fernandez wrote:
>> Update Kconfig:
>> - MIGHT_HAVE_PCI
>> - PCI_DOMAINS
>>
>&g
On 6 October 2015 at 23:01, Arnd Bergmann wrote:
> On Tuesday 06 October 2015 09:56:08 Gabriel Fernandez wrote:
>> +
>> +/*
>> + * On ARM platforms, we actually get a bus error returned when the PCIe IP
>> + * returns a UR or CRS instead of an OK.
>> + */
>
Add support for new PLL-type for stih418 A9-PLL.
Currently the 407_A9_PLL type being used, it is corrected with this patch
4600c28 PLL allows to reach higher frequencies
so its programming algorithm is extended.
Signed-off-by: Pankaj Dev
Signed-off-by: Gabriel Fernandez
---
.../devicetree
r 4.3'
Gabriel Fernandez (4):
drivers: clk: st: Support for enable/disable in Clockgen PLLs
drivers: clk: st: PLL rate change implementation for DVFS
drivers: clk: st: Correct the pll-type for A9 for stih418
ARM: STi: DT: Add support for stih418 A9 pll
.../devicetree/bindings/clock/st
Add support for new PLL-type for stih418 A9-PLL.
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/stih418-clock.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi
b/arch/arm/boot/dts/stih418-clock.dtsi
index 148e177..ae6d997
Change A9 PLL rate, as per requirement from the cpufreq framework,
for DVFS. For rate change, the A9 clock needs to be temporarily sourced
from PLL external to A9 and then sourced back to A9-PLL
Signed-off-by: Pankaj Dev
Signed-off-by: Gabriel Fernandez
---
drivers/clk/st/clkgen-mux.c | 3
The patch adds support for enable/disable of the Clockgen PLLs.
clkgen_pll_enable/clkgen_pll_disable added as generic function for all PLLs.
Signed-off-by: Pankaj Dev
Signed-off-by: Gabriel Fernandez
---
drivers/clk/st/clkgen-pll.c | 60 -
1 file
Hi Rob,
Thanks for reviewing.
On 01/29/2018 07:56 PM, Rob Herring wrote:
> On Thu, Jan 18, 2018 at 03:49:40PM +0100, gabriel.fernan...@st.com wrote:
>> From: Gabriel Fernandez
>>
>> This patch adds DSI clock for STM32F469 board
>>
>> Signed-off-by: Gabriel F
Hi Benjamin,
Just remove the extra blanck line.
Otherwise you can addmy
Acked-by: Gabriel Fernandez
Best regards
Gabriel
On 01/15/2018 03:21 PM, Benjamin Gaignard wrote:
> Add two configuration flags to be able to not compile all the time
> stm32f and stm32h7 drivers when ARCH_STM32
Many Thanks Mike !
Best Regards
Gabriel.
On 03/11/2018 11:42 PM, Michael Turquette wrote:
> Excerpts from gabriel.fernan...@st.com's message of March 8, 2018 8:53
> am:
>> From: Gabriel Fernandez
>>
>> v2:
>> - Don't use MFD, use existing binding of
Thanks Rob !
Best Regards
Gabriel
On 03/10/2018 12:53 AM, Rob Herring wrote:
> On Thu, Mar 08, 2018 at 05:53:54PM +0100, gabriel.fernan...@st.com wrote:
>> From: Gabriel Fernandez
>>
>> The RCC block is responsible of the management of the clock and reset
>>
Thanks Stephen !
Best Regards
Gabriel
On 03/19/2018 09:45 PM, Stephen Boyd wrote:
> Quoting gabriel.fernan...@st.com (2018-03-08 22:57:31)
>> From: Gabriel Fernandez
>>
>> This patch adds DSI clock for STM32F469 board
>>
>> Signed-off-by: Gabriel Fernandez
>> ---
> Applied to clk-next
>
Hi Philipp,
Okay, i too support the idea to add custom reset driver.
Many Thanks Philipp.
Best regards
Gabriel
On 03/14/2018 10:12 AM, Philipp Zabel wrote:
> Hi Gabriel,
>
> On Tue, 2018-03-13 at 17:34 +0100, gabriel.fernan...@st.com wrote:
>> From: Gabriel Fernandez
>&
Hi Christophe,
Many thanks !
Acked-by: Gabriel Fernandez
On 05/13/2018 01:17 PM, Christophe Jaillet wrote:
> We allocate some memory which is neither used, nor referenced by anything.
> So axe it.
>
> Signed-off-by: Christophe JAILLET
> ---
> This patch as not been compi
The MiPHY28lp is a Generic PHY which can serve various SATA, PCIe or
USB3 devices. The two first ports can be use for either; both SATA, both
PCIe or one of each in any configuration.
The Third port is only for USB3.
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/stih407-family.dtsi
p phy driver same way as Peter's implementation.
Gabriel Fernandez (3):
phy: miphy28lp: Pass sysconfig register offsets via syscfg dt
property.
ARM: DT: STi: STiH407: Add DT node for MiPHY28lp
ARM: multi_v7_defconfig: Enable MiPHY28lp - ST's Generic (SATA, PCIe &
USB3) P
Signed-off-by: Gabriel Fernandez
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig
b/arch/arm/configs/multi_v7_defconfig
index 4b87fd1..88dfa7e 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs
aligns us to how other
platforms such as keystone and bcm7445 pass there syscon offsets via DT.
I have updated the miphy28lp phy driver same way as Peter's implementation.
Signed-off-by: Gabriel Fernandez
---
.../devicetree/bindings/phy/phy-miphy28lp.txt | 43 ++-
drivers/ph
This patch adds the DRM/KMS dt nodes.
Signed-off-by: Benjamin Gaignard
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/stih410.dtsi | 138 +
1 file changed, 138 insertions(+)
diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410
This patch adds the DRM/KMS dt nodes.
This node can't be in stih407-family.dtsi file because in the future we
will integrate a new stih418-b2199 board. It's a stih407 family board
with different drm/kms dt nodes.
That is why i created the stih407.dtsi file.
Signed-off-by: Gabriel
This patch-set Enable DRM/KMS support for STiH407-b2120 and STiH410-b2120
boards.
This patch-set replace the previous one (PATCH 0/2] Enable DRM/KMS support for
STiH407 Family boards)
Gabriel Fernandez (2):
ARM: DT: STiH407: Add DRM dt nodes
ARM: DT: STiH410: Add DRM dt nodes
arch/arm
Hi Arnd,
Thanks for reviewing
On 17 December 2014 at 23:01, Arnd Bergmann wrote:
> On Wednesday 17 December 2014 11:34:43 Gabriel FERNANDEZ wrote:
>> sti pcie is built around a Synopsis Designware PCIe IP.
>>
>> Signed-off-by: Fabrice Gasnier
>> Signe
Hi Jingoo,
Thanks for reviewing
On 18 December 2014 at 07:03, Jingoo Han wrote:
> On Wednesday, December 17, 2014 7:35 PM, Gabriel FERNANDEZ wrote:
>>
>> sti pcie is built around a Synopsis Designware PCIe IP.
>>
>> Signed-off-by: Fabrice Gasnier
>>
Hi Arnd,
On 17 December 2014 at 23:14, Arnd Bergmann wrote:
> On Wednesday 17 December 2014 11:34:44 Gabriel FERNANDEZ wrote:
>> sti pcie is built around a Synopsis Designware PCIe IP.
>>
>> Signed-off-by: Fabrice Gasnier
>> Signed-off-by: Gabriel Fernandez
>>
Hi Arnd, Jingoo,
On 18 December 2014 at 05:58, Jingoo Han wrote:
> On Thursday, December 18, 2014 7:16 AM, Arnd Bergmann wrote:
>> On Wednesday 17 December 2014 11:34:45 Gabriel FERNANDEZ wrote:
>> > ST sti SoCs PCIe IPs are built around DesignWare IP Core.
>> > But in
Hi Peter, Lee,
With these series as they are, we need 'clk_ignore_unused' on
sthi407-b2120.dts and stih418-b2199.dts.
We have to modificate stih407-clock.dtsi and stih418-clock.dtsi in same way.
BR
Gabriel
On 2 April 2015 at 10:12, Peter Griffin wrote:
> Hi Lee,
>
> On Fri, 27 Feb 2015, Lee
Hi Liviu,
You're right, i removed configuration space from the ranges.
Thanks for reviewing.
Gabriel
On 17 March 2015 at 12:42, Liviu Dudau wrote:
> Hi Gabriel,
>
> On Mon, Mar 16, 2015 at 02:20:32PM +, Gabriel FERNANDEZ wrote:
>> sti pcie is built around a Synopsi
Hi Kishon,
I tested with my internal 3.10 ST Kernel but not on the 4.0.
I think i'll implement it when i'm able to test it fully.
Thanks
On 17 March 2015 at 11:35, Kishon Vijay Abraham I wrote:
> Hi,
>
>
> On Monday 16 March 2015 07:50 PM, Gabriel FERNANDEZ wrote:
>>
Hi Bjorn,
pci-st.c driver could be modular with modification of pcie-designware
core driver. But as Fabrice said it should be another patchset.
What do you prefer ?
drop all the module related macros as mentioned by Paul ?
or
keep macros like other vendors do ?
Thanks
Gabriel
On 18 March 201
Hi
Thanks for reviewing.
On 11 April 2015 at 16:55, Arnd Bergmann wrote:
> On Saturday 11 April 2015 12:17:57 Paul Bolle wrote:
>> Something I didn't spot in my first look at this patch.
>>
>> On Fri, 2015-04-10 at 11:12 +0200, Gabriel FERNANDEZ wrote:
>>
This first patch-set contains various clock fixes for ST SoC.
Gabriel Fernandez (7):
drivers: clk: st: Incorrect clocks status
drivers: clk: st: Incorrect register offset used for lock_status
drivers: clk: st: Remove unused code
drivers: clk: st: Fix FSYN channel values
drivers: clk: st
This patch fixes the mux bit-setting for ClockgenA9.
Signed-off-by: Gabriel Fernandez
---
drivers/clk/st/clkgen-mux.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/st/clkgen-mux.c b/drivers/clk/st/clkgen-mux.c
index 3919a67..ecb492e 100644
--- a/drivers/clk/st
Use a generic name for this kind of PLL
Signed-off-by: Gabriel Fernandez
---
Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt | 4 ++--
arch/arm/boot/dts/stih407-clock.dtsi | 4 ++--
arch/arm/boot/dts/stih410-clock.dtsi | 4 ++--
arch
Remove this duplicated code due to a bad copy / paste.
Signed-off-by: Gabriel Fernandez
---
drivers/clk/st/clkgen-fsyn.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index e6d7073..e7e6782 100644
--- a/drivers/clk/st/clkgen
This patch fixes the value for disabling the FSYN channel clock.
The 'is_enabled' returned value is also fixed.
Signed-off-by: Pankaj Dev
Signed-off-by: Gabriel Fernandez
---
drivers/clk/st/clkgen-fsyn.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/driv
From: Pankaj Dev
Add the CLK_GET_RATE_NOCACHE flag to all the clocks with recalc ops,
so that they reflect Hw rate after CPS wake-up when a clk_get_rate()
is called
Signed-off-by: Pankaj Dev
Signed-off-by: Gabriel Fernandez
---
drivers/clk/st/clk-flexgen.c | 2 +-
drivers/clk/st/clkgen
Incorrect register offset used for sthi407 clockgenC
Signed-off-by: Pankaj Dev
---
drivers/clk/st/clkgen-fsyn.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index e94197f..e6d7073 100644
--- a/drivers/clk/st/clkge
In the clk_summary output, the h/w status of DivMux is incorrect
(Parent and Enable status), since the clk_mux_ops.get_parent()
returns -ERRCODE when clock is OFF.
Signed-off-by: Pankaj Dev
Signed-off-by: Gabriel Fernandez
---
drivers/clk/st/clkgen-mux.c | 15 +--
1 file changed, 9
) from [] (time_init+0x20/0x30)
[] (time_init+0x20/0x30) from [] (start_kernel+0x20c/0x2e8)
[] (start_kernel+0x20c/0x2e8) from [<40008074>] (0x40008074)
Signed-off-by: Giuseppe Cavallaro
Signed-off-by: Gabriel Fernandez
---
drivers/clk/st/clk-flexgen.c | 2 ++
1 file changed, 2 insertions(+)
Use a generic name for this kind of PLL
Signed-off-by: Gabriel Fernandez
---
drivers/clk/st/clkgen-fsyn.c | 8
drivers/clk/st/clkgen-pll.c | 12 ++--
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
Hi Stephen,
Thanks for reviewing
On 24 June 2015 at 22:02, Stephen Boyd wrote:
> On 06/23/2015 07:09 AM, Gabriel Fernandez wrote:
>> In the clk_summary output, the h/w status of DivMux is incorrect
>> (Parent and Enable status), since the clk_mux_ops.get_parent()
>> return
Hi
Tested-by Gabriel Fernandez
Best Regards.
On 06/10/2015 11:49 PM, dingu...@opensource.altera.com wrote:
From: Dinh Nguyen
Use of_clk_parent_fill to fill in the parent clock names' array.
Signed-off-by: Dinh Nguyen
Cc: Peter Griffin
Cc: Gabriel FERNANDEZ
---
drivers/clk/s
Hi Stephen,
This patch is not a critical fix for this merge window.
Thanks
Gabriel
On 05/02/2018 12:10 AM, Stephen Boyd wrote:
> Quoting gabriel.fernan...@st.com (2018-04-24 00:58:43)
>> From: Gabriel Fernandez
>>
>> Don't disable the dbg clock if was set by bootl
Thanks Stephen
On 05/15/2018 08:23 PM, Stephen Boyd wrote:
> Quoting gabriel.fernan...@st.com (2018-04-24 00:58:43)
>> From: Gabriel Fernandez
>>
>> Don't disable the dbg clock if was set by bootloader.
>>
>> Signed-off-by: Gabriel Fernandez
>> ---
> Applied to clk-next
>
Condorelli
Signed-off-by: Gabriel Fernandez
Are you sure these are in the correct order?
ok i change the order
+- linux,keymap: The keymap for keys as described in the binding document
+ devicetree/bindings/input/matrix-keymap.txt.
+
+- keypad,num-rows: Number of row lines connected to the keypad
Add keyscan support for stih416.
It is disabled by default given that it is not enabled on all boards.
Also there are PIOs conflict with already claimed lines.
Signed-off-by: Giuseppe Condorelli
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/stih416-pinctrl.dtsi | 16
This patch adds ST Keyscan driver to use the keypad hw a subset
of ST boards provide. Specific board setup will be put in the
given dt.
Signed-off-by: Giuseppe Condorelli
Signed-off-by: Gabriel Fernandez
---
.../devicetree/bindings/input/st-keypad.txt| 50
drivers/input/keyboard
This patch adds KEYBOARD_ST_KEYSCAN config
Signed-off-by: Gabriel Fernandez
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig
b/arch/arm/configs/multi_v7_defconfig
index ee69829..5e926981 100644
--- a/arch/arm
Add keyscan setup for stih415/h416 b2000.
Both have same raw/column lines number, debounce time and keymap.
Signed-off-by: Giuseppe Condorelli
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/stih41x-b2000.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm
From: Giuseppe CONDORELLI
Add keyscan support for stih415.
It is put disabled by default because it is not enabled on all boards
Also there are PIOs conflict with already claimed lines.
Signed-off-by: Giuseppe Condorelli
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/stih415
The goal of this series is to add ST Keyscan support to ST SoCs.
The DT definition is added for STiH415 and STiH416 SoCs on
B2000 board.
Gabriel Fernandez (4):
drivers: input: keyboard: st-keyscan: add keyscan driver
ARM: STi: DT: add keyscan for stih416
ARM: STi: DT: add keyscan for
Signed-off-by: Gabriel Fernandez
---
.../devicetree/bindings/clock/st/st,clkgen-pll.txt | 48 ++
1 file changed, 48 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
diff --git a/Documentation/devicetree/bindings/clock/st/st
required.
Signed-off-by: Pankaj Dev
Signed-off-by: Gabriel Fernandez
---
drivers/clk/st/clkgen-pll.c | 139
1 file changed, 139 insertions(+)
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index c6b38b0..bca0a0b 100644
--- a/drivers
The goal of this series is to add Clocks support to ST SoCs.
The DT definition is added for STiH415 and STiH416 SoCs on
B2000 and B2020 boards.
The series has been tested working on STiH416-B2020 board.
It applies on top of v3.14-rc3.
Gabriel Fernandez (15):
drivers: clk: st: Support for
The patch supports the A9-mux clocks used by ClockGenA9
A9-mux clock : Multiplexer inside ClockGenA9. A9 clock can be driven by
either PLL or External clock (with an optional divide-by-2). This is
implemented as 3-parent clock : PLL, Ext-clk OR Ext-clk/2
Signed-off-by: Pankaj Dev
---
drivers/cl
Patch adds DT entries for clockgen A9/DDR/GPU
Signed-off-by: Pankaj Dev
---
arch/arm/boot/dts/stih416-clock.dtsi | 79
1 file changed, 70 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/stih416-clock.dtsi
b/arch/arm/boot/dts/stih416-clock.dtsi
Patch adds DT entries for clockgen A0/1/10/11/12
Signed-off-by: Pankaj Dev
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/stih416-clks.h | 11 +
arch/arm/boot/dts/stih416-clock.dtsi | 478 ++-
arch/arm/boot/dts/stih416.dtsi | 6 +-
3 files
Signed-off-by: Gabriel Fernandez
---
.../devicetree/bindings/clock/st/st,quadfs.txt | 45 ++
1 file changed, 45 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/st/st,quadfs.txt
diff --git a/Documentation/devicetree/bindings/clock/st/st
Signed-off-by: Gabriel Fernandez
---
.../bindings/clock/st/st,clkgen-divmux.txt | 49 +
.../bindings/clock/st/st,clkgen-prediv.txt | 36 ++
.../devicetree/bindings/clock/st/st,clkgen.txt | 83 ++
3 files changed, 168 insertions
.
QuadFS have 4 outputs : chan0 chan1 chan2 chan3
Signed-off-by: Pankaj Dev
Signed-off-by: Gabriel Fernandez
---
drivers/clk/st/Makefile |2 +-
drivers/clk/st/clkgen-fsyn.c | 1039 ++
2 files changed, 1040 insertions(+), 1 deletion(-)
create mode
clocks implemented in the kernel clk_divider, clk_mux,
clk_gate and clk_composite (to combine all)
MUX clock : 2-parent clock used inside ClockGenC/F. The clock is implemented
using generic clocks implemented in the kernel clk_mux.
Signed-off-by: Pankaj Dev
Signed-off-by: Gabriel Fernandez
have 1-4 outputs : ODFx
Signed-off-by: Pankaj Dev
Signed-off-by: Gabriel Fernandez
---
drivers/clk/st/Makefile | 2 +-
drivers/clk/st/clkgen-pll.c | 559
drivers/clk/st/clkgen.h | 48
3 files changed, 608 insertions(+), 1 deletion
Patch adds DT entries for clockgen B/C/D/E/F
Signed-off-by: Pankaj Dev
---
arch/arm/boot/dts/stih416-clock.dtsi | 170 +++
1 file changed, 170 insertions(+)
diff --git a/arch/arm/boot/dts/stih416-clock.dtsi
b/arch/arm/boot/dts/stih416-clock.dtsi
index f63b0a1..6
Signed-off-by: Gabriel Fernandez
---
.../devicetree/bindings/clock/st/st,clkgen-mux.txt | 36 +++
.../devicetree/bindings/clock/st/st,clkgen-vcc.txt | 53 ++
2 files changed, 89 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/st/st,clkgen
Patch adds DT entries for clockgen A9
Signed-off-by: Pankaj Dev
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/stih415-clock.dtsi | 67 +++-
1 file changed, 58 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/stih415-clock.dtsi
b/arch/arm
clocks implemented in the kernel
clk_divider and clk_mux.
PreDiv clock : Fixed Divider Clock used inside ClockGenA(s) to divide
the oscillator clock by factor-of-16. The clock is implemented using
generic clocks implemented in the kernel clk_divider.
Signed-off-by: Pankaj Dev
Signed-off-by: Gabriel
Patch adds DT entries for clockgen A0/1/10/11/12
Signed-off-by: Pankaj Dev
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/stih415-clks.h | 11 +
arch/arm/boot/dts/stih415-clock.dtsi | 475 ++-
arch/arm/boot/dts/stih415.dtsi | 6 +-
3 files
Signed-off-by: Gabriel Fernandez
Are you sure these are in the correct order?
ok i change the order
I'm not saying they are in the wrong order, I'm just asking. Who wrote
the patch? Has it changed since?
Sorry...
I wrote the patch, then Guiseppe has changed and tested, and I re-modifiedit
Add keyscan support for stih416.
It is disabled by default given that it is not enabled on all boards.
Also there are PIOs conflict with already claimed lines.
Signed-off-by: Giuseppe Condorelli
Signed-off-by: Gabriel Fernandez
---
arch/arm/boot/dts/stih416-pinctrl.dtsi | 16
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