From: Hanjun Guo
With the platform msi domain created, we can set up the msi domain
for a platform device when it's probed.
This patch introduces acpi_configure_msi_domain(), which retrieves
the domain from iort and set it to platform device.
As some platform devices such as an irqchip
Hi Marc,
Thanks for your review, reply inline.
On 09/14/2016 11:45 PM, Marc Zyngier wrote:
On 14/09/16 15:21, Hanjun Guo wrote:
From: Hanjun Guo
With the platform msi domain created, we can set up the msi domain
for a platform device when it's probed.
This patch intro
From: Hanjun Guo
Introduce its_pmsi_init_one() to refactor the code to isolate
ACPI&DT common code to prepare for ACPI later.
Signed-off-by: Hanjun Guo
---
drivers/irqchip/irq-gic-v3-its-platform-msi.c | 45 ---
1 file changed, 27 insertions(+), 18 deletions(-)
From: Hanjun Guo
For devices connecting to ITS, it needs dev id to identify
itself, and this dev id is represented in the IORT table in
named componant node [1] for platform devices, so in this
patch we will scan the IORT to retrieve device's dev id.
Introduce iort_pmsi_get_dev_id()
From: Hanjun Guo
With platform msi support landed in the kernel, and the introduction
of IORT for GICv3 ITS (PCI MSI) [1], the framework for platform msi
is ready, this patch set add few patches to enable the ACPI platform
msi support.
For platform device connecting to ITS on arm platform, we
From: Hanjun Guo
With the introduction of its_pmsi_init_one(), we can add some code
on top for ACPI support of platform MSI.
We are scanning the MADT table to get the ITS entry(ies), then use
the information to create the platform msi domain for devices connect
to it, just like the PCI MSI for
From: Hanjun Guo
Adding ACPI support for platform MSI, we need to retrieve the
dev id in ACPI way instead of device tree, we already have
a well formed function its_pmsi_prepare() to get the dev id
but it's OF dependent, so collect OF related code and put them
into a single function to
From: Hanjun Guo
With the platform msi domain created, we can set up the msi domain
for a platform device when it's probed.
This patch introduces acpi_configure_msi_domain(), which retrieves
the domain from iort and set it to platform device.
As some platform devices such as an irqchip
From: Kefeng Wang
Module owner will be set by driver core, so drop it.
Signed-off-by: Kefeng Wang
Signed-off-by: Hanjun Guo
---
drivers/irqchip/irq-mbigen.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/irqchip/irq-mbigen.c b/drivers/irqchip/irq-mbigen.c
index 03b79b0..c01ab41
From: Kefeng Wang
Introduce mbigen_of_create_domain() to consolidate OF related
code and prepare for ACPI later.
Signed-off-by: Kefeng Wang
Signed-off-by: Hanjun Guo
---
drivers/irqchip/irq-mbigen.c | 42 +++---
1 file changed, 27 insertions(+), 15
From: Hanjun Guo
With the platform msi domain created for ITS, irqchip such as
mbi-gen connecting ITS, which needs ctreate its own irqdomain.
Fortunately with the platform msi support upstreamed by Marc,
we just need to add minor code to make it run properly.
platform_msi_create_device_domain
From: Hanjun Guo
With the preparation of platform msi support and interrupt producer
in DSDT, we can add mbigen ACPI support now.
We are using _PRS methd to indicate number of irq pins instead
of num_pins in DT.
For mbi-gen,
Device(MBI0) {
Name(_HID, "HISI0152")
From: Hanjun Guo
In ACPI 6.1 spec, section 19.6.62, Interrupt Resource Descriptor Macro,
Interrupt (ResourceUsage, EdgeLevel, ActiveLevel, Shared,
ResourceSourceIndex, ResourceSource, DescriptorName)
{ InterruptList } => Buffer
For the arguement ResourceUsage and DescriptorName, which me
On 10/07/2015 02:01 AM, Bjorn Helgaas wrote:
On Mon, Sep 14, 2015 at 04:07:35PM +0800, Jiang Liu wrote:
Use common interface to simplify ACPI PCI host bridge implementation.
Signed-off-by: Jiang Liu
Reviewed-by: Hanjun Guo
Is there a corresponding ia64 patch? If we're really consolid
On 08/30/2015 02:12 AM, Marc Zyngier wrote:
On 2015-08-29 16:12, Jiang Liu wrote:
On 2015/8/29 21:00, Yang Yingliang wrote:
From: Yang Yingliang
When cpu is disabled, all irqs will be migratged to another cpu.
In some cases, a new affinity is different, it needed to be coppied
to irq's affini
On 10/12/2015 05:44 PM, Sudeep Holla wrote:
On 12/10/15 08:04, Hanjun Guo wrote:
On 10/12/2015 11:58 AM, Pat Erley wrote:
On 10/11/2015 08:49 PM, Hanjun Guo wrote:
On 10/12/2015 11:08 AM, Pat Erley wrote:
On 10/05/2015 10:12 AM, Al Stone wrote:
On 10/05/2015 07:39 AM, Rafael J. Wysocki
On 10/13/2015 03:21 AM, Rafael J. Wysocki wrote:
On Monday, October 12, 2015 03:04:30 PM Hanjun Guo wrote:
On 10/12/2015 11:58 AM, Pat Erley wrote:
On 10/11/2015 08:49 PM, Hanjun Guo wrote:
On 10/12/2015 11:08 AM, Pat Erley wrote:
On 10/05/2015 10:12 AM, Al Stone wrote:
On 10/05/2015 07:39
chip/gic: Kill the xlate method
acpi/gsi: Cleanup acpi_register_gsi
irqdomain: Introduce irq_domain_create_hierarchy
irqdomain/msi: Use fwnode instead of of_node
irqdomain: Documentation updates
For this patch series,
Reviewed-by: Hanjun Guo
For patch 1 to patch14,
Tested-by: Hanjun G
On 10/13/2015 09:49 PM, Hanjun Guo wrote:
On 10/13/2015 07:51 PM, Marc Zyngier wrote:
[This patch series used to be called "Making the generic ACPI GSI
layer irqdomain aware", but as I've radically changed my approach to
this problem, I've decided to reset the counters...]
On 09/08/2015 05:57 PM, Marc Zyngier wrote:
On 07/09/15 22:29, Rafael J. Wysocki wrote:
On Friday, September 04, 2015 06:06:48 PM Marc Zyngier wrote:
IRQ controllers and timers are the two types of device the kernel
requires before being able to use the device driver model.
ACPI so far lacks a
Hi Marc,
Sorry for the late response for quite a while...
On 09/05/2015 01:06 AM, Marc Zyngier wrote:
IRQ controllers and timers are the two types of device the kernel
requires before being able to use the device driver model.
ACPI so far lacks a proper probing infrastructure similar to the on
On 09/07/2015 04:45 PM, Lorenzo Pieralisi wrote:
On Mon, Sep 07, 2015 at 05:14:22AM +0100, Ganapatrao Kulkarni wrote:
Hi Hanjun,
On Wed, May 27, 2015 at 1:51 PM, Hanjun Guo wrote:
Hi Liviu,
On 2015???05???27??? 01:20, Jiang Liu wrote:
On 2015/5/27 0:58, Liviu Dudau wrote:
On Tue, May 26
On 10/16/2015 03:15 AM, Jon Masters wrote:
Hi Hanjun,
Thanks for your hard work on ARM64 PCI host bridge/root complex so far!
On 05/26/2015 08:49 AM, Hanjun Guo wrote:
This patch set is introducing ARM64 PCI hostbridge init based on ACPI,
which based on Jiang Liu's patch set "Consol
On 2015/10/21 5:26, Brijesh Singh wrote:
> Hi Hanjun,
>
> Thanks for review.
>
> -Brijesh
> On 10/19/2015 09:21 PM, Hanjun Guo wrote:
>> Hi Brijesh,
>>
>> On 2015/10/20 3:23, Brijesh Singh wrote:
[...]
>> The codes above are common for all A57 architect
On 2015/10/21 1:25, Mark Rutland wrote:
> On Tue, Oct 20, 2015 at 11:44:46AM -0500, Brijesh Singh wrote:
>> Hi Mark,
>>
>> Thanks for review.
>>
>> -Brijesh
>>
>> On 10/19/2015 03:52 PM, Mark Rutland wrote:
>>> Hi,
>>>
>>> Please Cc the devicetree list (devicet...@vger.kernel.org) when sending
>>>
Hi Boris, Mark,
On 2015/10/21 1:36, Borislav Petkov wrote:
> On Tue, Oct 20, 2015 at 06:26:55PM +0100, Mark Rutland wrote:
>>> Btw, how much of this is implementing generic A57 functionality?
>> The driver is entirely A57 generic.
>>
>>> If a lot, can we make this a generic a57_edac driver so that
Hi Brijesh,
On 2015/10/20 3:23, Brijesh Singh wrote:
> Add support for the AMD Seattle SoC EDAC driver.
>
> Signed-off-by: Brijesh Singh
> ---
> .../devicetree/bindings/edac/amd-seattle-edac.txt | 15 +
> drivers/edac/Kconfig | 6 +
> drivers/edac/Makefile
On 2015/10/21 17:35, Borislav Petkov wrote:
> On Wed, Oct 21, 2015 at 09:55:43AM +0800, Hanjun Guo wrote:
>> So I think the meaning of those error register is the same, but the way
>> of handle it may different from SoCs, for single bit error:
>>
>> - SoC may trigger
Hi Brijesh,
On 2015/10/22 22:46, Brijesh Singh wrote:
> Hi Andre,
>
> On 10/21/2015 06:52 PM, Andre Przywara wrote:
>> On 21/10/15 21:41, Brijesh Singh wrote:
>>> Add support for Cortex A57 and A53 EDAC driver.
>> Hi Brijesh,
>>
>> thanks for the quick update! Some comments below.
>>
>>> Signed-of
On 2015/10/24 1:58, Brijesh Singh wrote:
>> So I checked the x86 code: the driver is always loaded as soon as the
>> hardware is there (looking at PCI device IDs from the on-chip
>> northbridge, for instance). The trick here is to have the Kconfig option
>> defaulting to "=n", so a kernel builder w
Hi Suravee,
Some minor comments below:
On 2015/10/21 23:52, Suravee Suthikulpanit wrote:
[...]
> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> index eea8b42..09264f8 100644
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -6,12 +6,14 @@
> #include
> #include
> #includ
On 2015/10/21 23:52, Suravee Suthikulpanit wrote:
> This patch adds support for setting up PCI device DMA coherency from
> ACPI _CCA object that should normally be specified in the DSDT node
> of its PCI host bridge.
>
> Signed-off-by: Suravee Suthikulpanit
> CC: Bjorn Helgaas
> CC: Catalin Marin
ing DMA Attribute APIs for Generic Devices
> device property: acpi: Make use of the new DMA Attribute APIs
> device property: acpi: Remove unused DMA APIs
> PCI: OF: Move of_pci_dma_configure() to pci_dma_configure()
> PCI: ACPI: Add support for PCI device DMA coherency
If the
On 2015/10/15 22:05, Tomasz Nowicki wrote:
> After refactoring DT code, we let ACPI to build ITS PCI MSI domain
> and do requester ID to device ID translation using IORT table.
>
> We have now full PCI MSI domain stack, thus we can enable ITS initialization
> from GICv3 core driver for ACPI scenari
On 2018/6/20 19:51, Punit Agrawal wrote:
> Xie XiuQi writes:
>
>> Hi Lorenzo, Punit,
>>
>>
>> On 2018/6/20 0:32, Lorenzo Pieralisi wrote:
>>> On Tue, Jun 19, 2018 at 04:35:40PM +0100, Punit Agrawal wrote:
Michal Hocko writes:
> On Tue 19-06-18 15:54:26, Punit Agrawal wrote:
> [
From: Hanjun Guo
platform_get_resource() may return NULL, add proper
check to avoid potential NULL dereferencing.
Signed-off-by: Hanjun Guo
---
drivers/irqchip/irq-mbigen.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/irqchip/irq-mbigen.c b/drivers/irqchip/irq-mbigen.c
index
"irqchip/mbigen: Implement the mbigen irq chip operation
functions")
Signed-off-by: MaJun
Signed-off-by: Hanjun Guo
---
drivers/irqchip/irq-mbigen.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/irqchip/irq-mbigen.c b/drivers/irqchip/irq-mbigen.c
index 2fa1
From: Hanjun Guo
Some mbigens share memory regions, and devm_ioremap_resource
does not allow to share resources which will break the probe
of mbigen, in opposition to devm_ioremap.
This patch restores back usage of devm_ioremap function, but
with proper error handling and logging.
Fixes
From: Hanjun Guo
Here are 3 bugfixes for mbigen:
Patch 1 is a critical bugfix which to fix the mbigen probe failure,
commit 216646e4d82e ("irqchip/mbigen: Fix return value check in
mbigen_device_probe()") introduced this breakage;
Patch 2 fixes a potential NULL dereferencing;
Patch
Hi Shunyong,
On 2018/1/30 9:44, Yang, Shunyong wrote:
> Hi, Rafael
>
> Could you please help to review this patch? This is a small change to
> add ACPI_SIG_IORT to table_sigs[].
> Loading IORT table from initrd is very useful to debug SMMU node/device
> probe, MSI allocation, stream id translati
Hi Marc,
On 2018/1/30 1:45, Marc Zyngier wrote:
> static int enable_psci_bp_hardening(void *data)
> {
> const struct arm64_cpu_capabilities *entry = data;
>
> - if (psci_ops.get_version)
> + if (psci_ops.get_version) {
> + if (check_smccc_arch_workaround_1(entry))
> +
On 2018/1/31 23:05, Marc Zyngier wrote:
> On 31/01/18 14:38, Ard Biesheuvel wrote:
>> On 31 January 2018 at 14:35, Ard Biesheuvel
>> wrote:
>>> On 31 January 2018 at 14:11, Marc Zyngier wrote:
>>>> On 31/01/18 13:56, Hanjun Guo wrote:
>>>>> H
On 2018/2/1 10:40, Hanjun Guo wrote:
> On 2018/1/31 23:05, Marc Zyngier wrote:
>> On 31/01/18 14:38, Ard Biesheuvel wrote:
>>> On 31 January 2018 at 14:35, Ard Biesheuvel
>>> wrote:
>>>> On 31 January 2018 at 14:11, Marc Zyngier wrote:
>>>>&g
Hi Jiri,
Thanks for the fix, comments inline.
On 2018/1/6 2:19, Jiri Kosina wrote:
>
> [ adding Hugh ]
>
> On Thu, 4 Jan 2018, Dave Hansen wrote:
>
>>> BTW, we have just reported a bug caused by kaiser[1], which looks like
>>> caused by SMEP. Could you please help to have a look?
>>>
>>> [1] h
Hi Dave,
Thank you very much for the quick response! Minor comments inline.
On 2018/1/6 14:06, Dave Hansen wrote:
> On 01/05/2018 08:54 PM, Hanjun Guo wrote:
>> Do you mean NX bit will be brought back later? I'm asking this because
>> I tested this patch which it fixed the
On 2018/1/6 14:28, Hanjun Guo wrote:
> Hi Dave,
>
> Thank you very much for the quick response! Minor comments inline.
>
> On 2018/1/6 14:06, Dave Hansen wrote:
>> On 01/05/2018 08:54 PM, Hanjun Guo wrote:
>>> Do you mean NX bit will be brought back later? I'
On 2018/1/6 15:55, Dave Hansen wrote:
> On 01/05/2018 10:53 PM, Hanjun Guo wrote:
>>> + /*
>>> + * PTI poisons low addresses in the kernel page tables in the
>>> + * name of making them unusable for userspace. To execute
>>> + * code at such a
On 2018/1/6 6:15, Kani, Toshi wrote:
> On Thu, 2017-12-28 at 19:24 +0800, Hanjun Guo wrote:
>> From: Hanjun Guo
>>
>> When we using iounmap() to free the 4K mapping, it just clear the PTEs
>> but leave P4D/PUD/PMD unchanged, also will not free the memory of page
>&
On 2018/1/10 10:04, Laura Abbott wrote:
> On 01/05/2018 05:10 PM, Dan Williams wrote:
>> From: Mark Rutland
>>
>> This patch implements nospec_ptr() for arm, following the recommended
>> architectural sequences for the arm and thumb instruction sets.
>>
> Fedora picked up the series and it fails o
Hi Xiuqi,
On 2018/5/31 20:14, Xie XiuQi wrote:
> A numa system may return node which is not online.
> For example, a numa node:
> 1) without memory
> 2) NR_CPUS is very small, and the cpus on the node are not brought up
I think adding detail info will be easy to be understood:
- NUMA node will b
Hi Punit,
On 2018/6/14 1:39, Punit Agrawal wrote:
> Punit Agrawal writes:
>
>
> [...]
>
>>
>> CONFIG_HAVE_MEMORYLESS node is not enabled on arm64 which means we end
>> up returning the original node in the fallback path.
>>
>> Xie, does the below patch help? I can submit a proper patch if this
Hi Sinan,
On 2018/12/15 9:02, Sinan Kaya wrote:
> Remove PCI dependent code out of iort.c when CONFIG_PCI is not defined.
>
> Signed-off-by: Sinan Kaya
> ---
> drivers/acpi/arm64/iort.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/io
On 2018/12/18 10:56, Sinan Kaya wrote:
> Remove PCI dependent code out of iort.c when CONFIG_PCI is not defined.
> A quick search reveals the following functions:
> 1. pci_request_acs()
> 2. pci_domain_nr()
> 3. pci_is_root_bus()
> 4. to_pci_dev()
>
> Both pci_domain_nr() and pci_is_root_bus() are
Signed-off-by: Joerg Roedel
> ---
> drivers/acpi/arm64/iort.c | 19 ++-
> 1 file changed, 10 insertions(+), 9 deletions(-)
Acked-by: Hanjun Guo
Thanks
Hanjun
On 2018/12/11 21:43, Joerg Roedel wrote:
> From: Joerg Roedel
>
> Replace the iommu-check with a proper and readable function
> call.
>
> Cc: Lorenzo Pieralisi
> Acked-by: Robin Murphy
> Signed-off-by: Joerg Roedel
Acked-by: Hanjun Guo
Thanks
Hanjun
tions(-)
Robin and Lorenzo know this better than me, but it's
pretty straight forward to me,
Acked-by: Hanjun Guo
Thanks
Hanjun
uct device
> *dev)
> { return NULL; }
> static inline int iort_add_device_replay(const struct iommu_ops *ops,
>struct device *dev)
Acked-by: Hanjun Guo
Lorenzo, I think this is 4.21-rc1 material if it's OK for you.
Thanks
Hanjun
Hi Marc,
>>> Now, the biggest question of them all: how does it work with ACPI? Last
>>> time I checked, there was no DT support for platforms using the MBIGEN.
>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/hisilicon/hip07.dtsi
>> This DT descr
On 2018/10/18 19:56, Marc Zyngier wrote:
> Hi Hanjun,
>
> On 18/10/18 12:20, Hanjun Guo wrote:
>> Hi Marc,
>>
>>>>>>
>>>>> Now, the biggest question of them all: how does it work with ACPI? Last
>>>>> time I checke
Hi Graeme,
On 2015年01月02日 04:04, Graeme Gregory wrote:
On Wed, Dec 31, 2014 at 04:34:46PM +0800, Hanjun Guo wrote:
On 2014年12月31日 04:13, ashw...@codeaurora.org wrote:
Hi Hanjun,
Overall the document looks good to us. Some minor clarifications below.
-- Forwarded message
On 2014年12月25日 01:18, Catalin Marinas wrote:
[...]
In addition to the above and _DSD requirements/banning, I would also add
some clear statements around:
_OSC: only global/published capabilities are allowed. For
device-specific _OSC we need a process or maybe we can ban them entirely
and rely o
From: Hanjun Guo
apic_id in MADT table is the CPU hardware id which identify
it self in the system for x86 and ia64, OSPM will use it for
SMP init to map APIC ID to logical cpu number in the early
boot, when the DSDT/SSDT (ACPI namespace) is scanned later, the
ACPI processor driver is probed and
From: Hanjun Guo
acpi_map_lsapic() will allocate a logical CPU number and map it to
physical CPU id (such as APIC id) for the hot-added CPU, it will also
do some mapping for NUMA node id and etc, acpi_unmap_lsapic() will
do the reverse.
We can see that the name of the function is a little bit
ly-by: Amit Daniel Kachhap
Tested-by: Suravee Suthikulpanit
Signed-off-by: Hanjun Guo
---
arch/arm64/kernel/acpi.c | 73
drivers/acpi/bus.c | 3 ++
include/linux/acpi.h | 1 +
3 files changed, 77 insertions(+)
diff --git a/arch/arm64/k
-off-by: Graeme Gregory
Signed-off-by: Tomasz Nowicki
Signed-off-by: Hanjun Guo
---
drivers/acpi/Makefile| 4
drivers/acpi/sleep-arm.c | 28
2 files changed, 32 insertions(+)
create mode 100644 drivers/acpi/sleep-arm.c
diff --git a/drivers/acpi/Makefile b
.
NOTE: This commit allow to initialize GICv1/2 basic functionality.
GICv2 vitalization extension, GICv3/4 and ITS are considered as next
steps.
Tested-by: Suravee Suthikulpanit
Signed-off-by: Tomasz Nowicki
Signed-off-by: Hanjun Guo
---
arch/arm64/kernel/acpi.c | 26 +
drivers
protocol is ready.
Tested-by: Suravee Suthikulpanit
Signed-off-by: Hanjun Guo
Signed-off-by: Tomasz Nowicki
---
arch/arm64/include/asm/acpi.h| 2 +
arch/arm64/include/asm/cpu_ops.h | 1 +
arch/arm64/include/asm/smp.h | 5 +-
arch/arm64/kernel/acpi.c | 150
paging_init(), so we should
use eary_memremap() mechanism here to get the RSDP and all the table
pointers.
Tested-by: Suravee Suthikulpanit
Signed-off-by: Al Stone
Signed-off-by: Graeme Gregory
Signed-off-by: Tomasz Nowicki
Signed-off-by: Hanjun Guo
---
arch/arm64/include/asm/acenv.h | 18
: Hanjun Guo
---
arch/arm64/include/asm/acpi.h | 29 +
arch/arm64/kernel/acpi.c | 1 -
drivers/acpi/processor_core.c | 37 +
3 files changed, 66 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64
; if people want use ACPI on ARM64. This ensures DT be
the prefer one if ACPI table and DT both are provided at this moment.
Tested-by: Suravee Suthikulpanit
Signed-off-by: Al Stone
Signed-off-by: Graeme Gregory
Signed-off-by: Hanjun Guo
---
Documentation/kernel-parameters.txt | 3 ++-
] enabled)
These information will be very helpful to bring up early systems to
see if acpi_id and MPIDR are matched or not as spec defined.
Tested-by: Suravee Suthikulpanit
Signed-off-by: Hanjun Guo
Signed-off-by: Tomasz Nowicki
---
drivers/acpi/tables.c | 43
: Hanjun Guo
---
arch/arm64/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index b1f9a20..c19ae5d 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -1,5 +1,6 @@
config ARM64
def_bool y
+ select ACPI_REDUCED_HARDWARE_ONLY
From: Graeme Gregory
Add documentation for the guidelines of how to use ACPI
on ARM64.
Reviewed-by: Suravee Suthikulpanit
Signed-off-by: Graeme Gregory
Signed-off-by: Al Stone
Signed-off-by: Hanjun Guo
---
Documentation/arm64/arm-acpi.txt | 327 +++
1
Using the information presented by GTDT to initialize the arch
timer (not memory-mapped).
Originally-by: Amit Daniel Kachhap
Tested-by: Suravee Suthikulpanit
Signed-off-by: Hanjun Guo
---
arch/arm64/kernel/time.c | 7 ++
drivers/clocksource/arm_arch_timer.c | 132
Signed-off-by: Graeme Gregory
Signed-off-by: Al Stone
Signed-off-by: Hanjun Guo
---
arch/arm64/Kconfig | 2 ++
drivers/acpi/Kconfig | 6 +++---
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index c19ae5d..915aa16 100644
--- a/arch/arm64
: Hanjun Guo
---
arch/arm64/kernel/setup.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
index 22e6895..2534de3 100644
--- a/arch/arm64/kernel/setup.c
+++ b/arch/arm64/kernel/setup.c
@@ -410,7 +410,8 @@ void __init
Suravee Suthikulpanit
Signed-off-by: Hanjun Guo
Signed-off-by: Graeme Gregory
Signed-off-by: Tomasz Nowicki
---
arch/arm64/include/asm/acpi.h | 14
arch/arm64/include/asm/psci.h | 3 +-
arch/arm64/kernel/acpi.c | 31 -
arch/arm64/kernel/psci.c
functions here and
implement it later.
Since ACPI on X86 and IA64 depends on PCI and this patch only makes
PCI optional for ARM64, it will not break anything on X86 and IA64.
Tested-by: Suravee Suthikulpanit
Signed-off-by: Hanjun Guo
---
arch/arm64/include/asm/pci.h | 6 ++
arch/arm64
Hi,
This is the sixth version of ACPI core patches for ARM64 based on ACPI
5.1.
updates from v5:
- fix the NULL pointer reference in cpu_get_ops() if PSCI is absent
and NULL will passed, which found by Suravee when he was testing
those patches on Seattle platform. I added his Tested-by
On 2015年01月05日 15:55, Suthikulpanit, Suravee wrote:
On 1/4/15, 04:55, "Hanjun Guo" wrote:
Using the information presented by GTDT to initialize the arch
timer (not memory-mapped).
Originally-by: Amit Daniel Kachhap
Tested-by: Suravee Suthikulpanit
Signed-off-by: Hanjun Guo
---
On 2015年01月05日 19:05, Catalin Marinas wrote:
On Sun, Jan 04, 2015 at 09:39:24AM +, Hanjun Guo wrote:
On 2014年12月25日 01:18, Catalin Marinas wrote:
[...]
In addition to the above and _DSD requirements/banning, I would also add
some clear statements around:
_OSC: only global/published
On 2015年01月06日 15:05, Yijing Wang wrote:
On 2015/1/4 18:55, Hanjun Guo wrote:
Hi,
Hello Hanjun,
We tested your v5 patch set (and added some GICv3 patches) on Hisilicon ARM64
SoC hardware,
from your change log for v6, there is only one functional change to fix the
NULL pointer, I think
the
Hi Yi,
On 2015年01月06日 17:52, liyi 00215672 wrote:
In traditional telecom market, what confused us(Huawei) was our software and
hardware coupling together oftentimes. So if we change some hardware then we
MUST modify our software, which was not our customer’s expectation. In x86
world,
we have U
On 2015年01月06日 19:29, Catalin Marinas wrote:
On Tue, Jan 06, 2015 at 11:11:07AM +, Hanjun Guo wrote:
On 2015年01月05日 19:05, Catalin Marinas wrote:
On Sun, Jan 04, 2015 at 09:39:24AM +, Hanjun Guo wrote:
On 2014年12月25日 01:18, Catalin Marinas wrote:
[...]
In addition to the above and
On 2015年01月06日 21:54, G Gregory wrote:
On 6 January 2015 at 13:50, Hanjun Guo wrote:
On 2015年01月06日 19:29, Catalin Marinas wrote:
On Tue, Jan 06, 2015 at 11:11:07AM +, Hanjun Guo wrote:
On 2015年01月05日 19:05, Catalin Marinas wrote:
On Sun, Jan 04, 2015 at 09:39:24AM +, Hanjun Guo
Hi,
On 2014年12月25日 01:18, Catalin Marinas wrote:
Hi,
Some thoughts before the end of the year. I won't be able to follow up
until around 5th of January though.
On Fri, Oct 17, 2014 at 02:37:14PM +0100, Hanjun Guo wrote:
--- /dev/null
+++ b/Documentation/arm64/arm-acpi.txt
@@ -0,0 +
Gregory
Signed-off-by: Al Stone
Signed-off-by: Hanjun Guo
---
Documentation/arm64/arm-acpi.txt | 323
++
1 file changed, 323 insertions(+)
create mode 100644 Documentation/arm64/arm-acpi.txt
[..]
+Relationship with Device Tree
On 2015年01月22日 22:46, Marc Zyngier wrote:
Hi Hanjun,
On 22/01/15 12:46, Hanjun Guo wrote:
Hi Marc,
We (Tomasz, Suravee and me) are working on supporting stacked domain on
ACPI, and rework GIC ACPI related patch, before we going further, we
need your guidance to see if we are going the right
Hi Mark,
On 2015年01月13日 03:09, Mark Salter wrote:
On Mon, 2015-01-12 at 17:25 +, Will Deacon wrote:
On Mon, Jan 12, 2015 at 04:55:11PM +, Mark Salter wrote:
Commit 0e63ea48b4d8 (arm64/efi: add missing call to early_ioremap_reset())
added a missing call to early_ioremap_reset(). This tr
Hi,
This is the v7 of ACPI core patches for ARM64 based on ACPI 5.1
updates from v6:
- Rebased on top of 3.19-rc4, add Mack Salter's patch to use
the early_ioremap after paging_init() for ACPI table mappings;
- Two patches about converting apic_id to phys_id to make it arch
agnostic
: Yijing Wang
Signed-off-by: Graeme Gregory
Signed-off-by: Tomasz Nowicki
Signed-off-by: Hanjun Guo
---
drivers/acpi/Makefile| 4
drivers/acpi/sleep-arm.c | 28
2 files changed, 32 insertions(+)
create mode 100644 drivers/acpi/sleep-arm.c
diff --git a
; if people want use ACPI on ARM64. This ensures DT be
the prefer one if ACPI table and DT both are provided at this moment.
Tested-by: Suravee Suthikulpanit
Tested-by: Yijing Wang
Signed-off-by: Al Stone
Signed-off-by: Graeme Gregory
Signed-off-by: Hanjun Guo
---
Documentation/kernel-paramet
ed-by: Suravee Suthikulpanit
Tested-by: Yijing Wang
Signed-off-by: Graeme Gregory
Signed-off-by: Tomasz Nowicki
Signed-off-by: Hanjun Guo
---
arch/arm64/include/asm/acpi.h | 14
arch/arm64/include/asm/psci.h | 3 +-
arch/arm64/kernel/psci.c
] enabled)
These information will be very helpful to bring up early systems to
see if acpi_id and MPIDR are matched or not as spec defined.
Tested-by: Suravee Suthikulpanit
Tested-by: Yijing Wang
Signed-off-by: Hanjun Guo
Signed-off-by: Tomasz Nowicki
---
drivers/acpi/tables.c | 43
protocol is ready.
Tested-by: Suravee Suthikulpanit
Tested-by: Yijing Wang
Signed-off-by: Hanjun Guo
Signed-off-by: Tomasz Nowicki
---
arch/arm64/include/asm/acpi.h| 2 +
arch/arm64/include/asm/cpu_ops.h | 1 +
arch/arm64/include/asm/smp.h | 5 +-
arch/arm64/kernel/acpi.c
ly-by: Amit Daniel Kachhap
Tested-by: Suravee Suthikulpanit
Tested-by: Yijing Wang
Signed-off-by: Hanjun Guo
---
arch/arm64/kernel/acpi.c | 73
drivers/acpi/bus.c | 3 ++
include/linux/acpi.h | 1 +
3 files changed, 77 insertions(+)
: Yijing Wang
Signed-off-by: Hanjun Guo
---
arch/arm64/include/asm/acpi.h | 29 +
arch/arm64/kernel/acpi.c | 1 -
drivers/acpi/processor_core.c | 37 +
3 files changed, 66 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include
.
NOTE: This commit allow to initialize GICv1/2 basic functionality.
GICv2 vitalization extension, GICv3/4 and ITS are considered as next
steps.
Tested-by: Suravee Suthikulpanit
Tested-by: Yijing Wang
Signed-off-by: Tomasz Nowicki
Signed-off-by: Hanjun Guo
---
arch/arm64/kernel/acpi.c
Using the information presented by GTDT to initialize the arch
timer (not memory-mapped).
Originally-by: Amit Daniel Kachhap
Tested-by: Suravee Suthikulpanit
Tested-by: Yijing Wang
Signed-off-by: Hanjun Guo
---
arch/arm64/kernel/time.c | 7 ++
drivers/clocksource
: Al Stone
Signed-off-by: Hanjun Guo
---
arch/arm64/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index b1f9a20..c19ae5d 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -1,5 +1,6 @@
config ARM64
def_bool y
+ select
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