On Wed, Oct 31, 2012 at 08:43:35AM +, Michal Simek wrote:
-Original Message-
From: Arnd Bergmann [mailto:a...@arndb.de]
Sent: Tuesday, October 30, 2012 11:22 PM
To: Michal Simek
Cc: Josh Cartwright; a...@kernel.org; linux-kernel@vger.kernel.org;
linux-arm-
ker
On Wed, Oct 31, 2012 at 08:48:38AM +, Michal Simek wrote:
From: Arnd Bergmann [mailto:a...@arndb.de]
On Tuesday 30 October 2012, Michal Simek wrote:
On 10/29/2012 07:56 PM, Josh Cartwright wrote:
[..]
delete mode 100644 arch/arm/mach-zynq/common.h
delete mode 100644 arch
The zynq-7000 has an additional UART at 0xE0001000. Describe it in the
device tree.
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
---
arch/arm/boot/dts/zynq-ep107.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/zynq-ep107.dts b/arch/arm/boot/dts/zynq
Add support for retrieving TTC configuration from device tree. This
includes the ability to pull information about the driving clocks from
the of_clk bindings.
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
---
arch/arm/boot/dts/zynq-7000.dtsi | 53
arch/arm/boot/dts/zynq-zc702
The Zynq platform requires the use of CONFIG_OF. Remove the #ifdef
conditionals in the uartps driver.
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
---
drivers/tty/serial/xilinx_uartps.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/drivers/tty/serial/xilinx_uartps.c
b
Suggested cleanup by Arnd Bergmann. Move the ttc timer.c code to
drivers/clocksource, and out of the mach-zynq directory.
The common.h (which only held the timer declaration) was renamed to
xilinx_ttc.h and moved into include/linux.
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
Cc: Arnd
a handle to parent's consumed clock (due to clock-ranges)? I
could make this work using of_clk_get_by_name(node_b, my_clock), but I
was somewhat surprised the former didn't work.
Thanks (and sorry for the novel),
Josh
---
Josh Cartwright (8):
ARM: zynq: move arm-specific sys_timer out of ttc
Add support for COMMON_CLK, and provide simplified models for the
necessary clocks on the zynq-7000. Currently, the PLLs, the CPU clock
network, and the basic peripheral clock networks (for SDIO, SMC, SPI,
QSPI, UART) are modelled.
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
Add support for specifying clock information for the uart clk via the
device tree. This eliminates the need to hardcode rates in the device
tree.
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
---
arch/arm/boot/dts/zynq-7000.dtsi | 4 ++--
drivers/tty/serial/xilinx_uartps.c | 30
Move the sys_timer definition out of ttc driver and make it part of the
common zynq code. This is preparation for renaming and COMMON_CLK
support.
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
---
arch/arm/mach-zynq/common.c | 13 +
arch/arm/mach-zynq/common.h | 4
with the 'dtbs' target.
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
---
arch/arm/boot/dts/Makefile | 1 +
.../boot/dts/{zynq-ep107.dts = zynq-7000.dtsi}| 19 +++---
arch/arm/boot/dts/zynq-zc702.dts | 30 ++
arch
On Wed, Oct 31, 2012 at 01:56:14PM -0600, Josh Cartwright wrote:
Add support for retrieving TTC configuration from device tree. This
includes the ability to pull information about the driving clocks from
the of_clk bindings.
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
---
diff
Thanks for the review.
On Fri, Nov 02, 2012 at 10:33:44AM +0100, Lars-Peter Clausen wrote:
On 10/31/2012 07:58 PM, Josh Cartwright wrote:
[...]
+#define PERIPH_CLK_CTRL_SRC(x) (periph_clk_parent_map[((x)3)4])
+#define PERIPH_CLK_CTRL_DIV(x) (((x)0x3F00)8)
A few more spaces
On Fri, Nov 02, 2012 at 10:20:33AM +0100, Lars-Peter Clausen wrote:
On 10/31/2012 08:28 PM, Josh Cartwright wrote:
Add support for specifying clock information for the uart clk via the
device tree. This eliminates the need to hardcode rates in the device
tree.
Signed-off-by: Josh
On Fri, Nov 02, 2012 at 04:12:21PM +0100, Lars-Peter Clausen wrote:
On 11/02/2012 02:38 PM, Josh Cartwright wrote:
On Fri, Nov 02, 2012 at 10:33:44AM +0100, Lars-Peter Clausen wrote:
On 10/31/2012 07:58 PM, Josh Cartwright wrote:
[...]
+static void __init zynq_periph_clk_setup(struct
On Sat, Oct 27, 2012 at 03:20:59PM +, Michal Simek wrote:
On Saturday, October 27, 2012 4:43 PM, Josh Cartwright wrote:
On Sat, Oct 27, 2012 at 02:06:45PM +, Michal Simek wrote:
[...]
I am not big fan to use dtsi solution because dts can be simple
generated directly From Xilinx
The Zynq platform requires the use of CONFIG_OF. Remove the #ifdef
conditionals in the uartps driver. Make dependency explicit in Kconfig.
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
---
Michal-
Here's a version of this patch outside of my COMMON_CLK patchset as you
requested ontop
On Mon, Nov 05, 2012 at 12:22:55PM +0100, Michal Simek wrote:
2012/10/29 Josh Cartwright josh.cartwri...@ni.com:
Suggested cleanup by Arnd Bergmann. Move the ttc timer.c code to
drivers/clocksource, and out of the mach-zynq directory.
The common.h (which only held the timer declaration
on this board.
For consistency's sake, add a choice entry for UART0 even though it is
the the default if UART1 is not selected.
Signed-off-by: Nick Bowler nbow...@elliptictech.com
Tested-by: Josh Cartwright josh.cartwri...@ni.com
---
Sorry all for the phenominal delay in sending this out
On Wed, Nov 07, 2012 at 01:05:57PM +0100, Michal Simek wrote:
2012/11/5 Josh Cartwright josh.cartwri...@ni.com:
[..]
Our usecase may admittedly be a bit weird, because what logic is in the
PL is ultimately determined (and even implemented) by the end user and
is loaded at runtime
Add support for retrieving TTC configuration from device tree. This
includes the ability to pull information about the driving clocks from
the of_clk bindings.
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
---
arch/arm/boot/dts/zynq-7000.dtsi | 53
arch/arm/boot/dts/zynq-zc702
Add support for specifying clock information for the uart clk via the
device tree. This eliminates the need to hardcode rates in the device
tree.
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
---
arch/arm/boot/dts/zynq-7000.dtsi | 4 ++--
drivers/tty/serial/xilinx_uartps.c | 30
Provide simplified models for the necessary clocks on the zynq-7000
platform. Currently, the PLLs, the CPU clock network, and the basic
peripheral clock networks (for SDIO, SMC, SPI, QSPI, UART) are modelled.
OF bindings are also provided and documented.
Signed-off-by: Josh Cartwright
://lists.infradead.org/pipermail/linux-arm-kernel/2012-October/129295.html
[2]: git://git.xilinx.com/linux-xlnx.git#arm-next
[3]: git://gi.teric.us/linux-zynq.git#of_clk_v2
---
Josh Cartwright (5):
ARM: zynq: dts: split up device tree
clk: Add support for fundamental zynq clks
ARM: zynq: use zynq clk bindings
with the 'dtbs' target.
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
---
arch/arm/boot/dts/Makefile | 1 +
.../boot/dts/{zynq-ep107.dts = zynq-7000.dtsi}| 19 +++---
arch/arm/boot/dts/zynq-zc702.dts | 30 ++
arch
Make the Zynq platform use the newly created zynq clk bindings.
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
---
arch/arm/Kconfig | 1 +
arch/arm/boot/dts/zynq-7000.dtsi | 56
arch/arm/boot/dts/zynq-zc702.dts | 4 +++
arch/arm
The Zynq support in mainline does not (yet) make use of any of the
generic clk or clk lookup functionality. Remove what is upstream for
now, until the out-of-tree implementation is in suitable form for
merging.
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
---
arch/arm/Kconfig
The Zynq uses the cortex-a9-gic. This eliminates the need to hardcode
register addresses.
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
---
arch/arm/boot/dts/zynq-ep107.dts | 8 +---
arch/arm/mach-zynq/common.c| 7 ++-
arch/arm/mach-zynq/include/mach
ioremap().
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
---
arch/arm/mach-zynq/common.c| 8 +++
arch/arm/mach-zynq/include/mach/zynq_soc.h | 34 +-
2 files changed, 23 insertions(+), 19 deletions(-)
diff --git a/arch/arm/mach-zynq/common.c b
This makes the definition of VMALLOC_END suitable for use within
assembly code. This is necessary to allow the use of VMALLOC_END in
defining where the early uart is mapped for use with DEBUG_LL.
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
---
arch/arm/include/asm/pgtable.h | 2 +-
1
] Error 2
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
---
arch/arm/Kconfig | 1 -
arch/arm/mach-zynq/common.c | 1 -
arch/arm/mach-zynq/include/mach/clkdev.h | 32
3 files changed, 34 deletions(-)
delete mode 100644 arch
a...@kernel.org was included
- Rebased on arm-soc/for-next
- Added a cover letter
- Elaborated a bit on why I removed CLKDEV_LOOKUP
---
Josh Cartwright (4):
ARM: annotate VMALLOC_END definition with _AC
zynq: move static peripheral mappings
zynq: use GIC device tree bindings
zynq: remove use
This makes the definition of VMALLOC_END suitable for use within
assembly code. This is necessary to allow the use of VMALLOC_END in
defining where the early uart is mapped for use with DEBUG_LL.
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
---
arch/arm/include/asm/pgtable.h | 2 +-
1
ioremap().
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
---
arch/arm/mach-zynq/common.c| 8 +++
arch/arm/mach-zynq/include/mach/zynq_soc.h | 38 +-
2 files changed, 25 insertions(+), 21 deletions(-)
diff --git a/arch/arm/mach-zynq/common.c b
The Zynq uses the cortex-a9-gic. This eliminates the need to hardcode
register addresses.
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
---
arch/arm/boot/dts/zynq-ep107.dts | 8 +---
arch/arm/mach-zynq/common.c| 7 ++-
arch/arm/mach-zynq/include/mach
Hey Arnd-
Thanks for the review/suggestions.
On Tue, Oct 23, 2012 at 02:50:11PM +, Arnd Bergmann wrote:
On Monday 22 October 2012, Josh Cartwright wrote:
Shifting them up into the vmalloc region prevents the following warning,
when booting a zynq qemu target with more than 512mb of RAM
On Tue, Oct 23, 2012 at 03:09:23PM -0500, Rob Herring wrote:
On 10/23/2012 09:50 AM, Arnd Bergmann wrote:
On Monday 22 October 2012, Josh Cartwright wrote:
-#define SCU_PERIPH_PHYS 0xF8F0
-#define SCU_PERIPH_VIRT SCU_PERIPH_PHYS
+#define
On Tue, Oct 23, 2012 at 05:17:42PM -0400, Nick Bowler wrote:
On 2012-10-23 15:53 -0500, Josh Cartwright wrote:
On Tue, Oct 23, 2012 at 03:09:23PM -0500, Rob Herring wrote:
On 10/23/2012 09:50 AM, Arnd Bergmann wrote:
On Monday 22 October 2012, Josh Cartwright wrote:
-#define
On Tue, Oct 23, 2012 at 04:27:03PM -0400, Nick Bowler wrote:
Just FYI, I sent a patch to fix the same bug a while back
https://patchwork.kernel.org/patch/1156361/
together with other patches to fix early printk on the ZC702 serial
console. Admittedly, I dropped the ball on these as other
---
Josh Cartwright (5):
zynq: use GIC device tree bindings
zynq: use pl310 device tree bindings
zynq: remove use of CLKDEV_LOOKUP
ARM: annotate VMALLOC_END definition with _AC
zynq: move static peripheral mappings
arch/arm/Kconfig | 1 -
arch/arm/boot/dts/zynq
The Zynq uses the cortex-a9-gic. This eliminates the need to hardcode
register addresses.
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
Cc: John Linn john.l...@xilinx.com
---
arch/arm/boot/dts/zynq-ep107.dts | 8 +---
arch/arm/mach-zynq/common.c| 7
The Zynq has a PL310 L2 cache controller. Convert in-tree uses to using
the device tree.
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
Cc: John Linn john.l...@xilinx.com
---
arch/arm/boot/dts/zynq-ep107.dts | 9 +
arch/arm/mach-zynq/common.c| 9
] Error 2
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
Cc: John Linn john.l...@xilinx.com
---
arch/arm/Kconfig | 1 -
arch/arm/mach-zynq/common.c | 1 -
arch/arm/mach-zynq/include/mach/clkdev.h | 32
3 files changed, 34
This makes the definition of VMALLOC_END suitable for use within
assembly code. This is necessary to allow the use of VMALLOC_END in
defining where the early uart is mapped for use with DEBUG_LL.
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
---
arch/arm/include/asm/pgtable.h | 2 +-
1
ioremap().
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
Cc: John Linn john.l...@xilinx.com
---
arch/arm/mach-zynq/common.c| 6 +++---
arch/arm/mach-zynq/include/mach/zynq_soc.h | 23 +--
2 files changed, 16 insertions(+), 13 deletions(-)
diff --git
The list of attributes above details the use of the 'filter-ranges'
property, but the example improperly used 'filter-latency'. Make these
consistent by fixing up the example.
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
---
Documentation/devicetree/bindings/arm/l2cc.txt | 2 +-
1 file
On Wed, Oct 24, 2012 at 09:32:32AM -0400, Nick Bowler wrote:
On 2012-10-23 19:34 -0500, Josh Cartwright wrote:
The Zynq support in mainline does not (yet) make use of any of the
generic clk or clk lookup functionality. Remove what is upstream for
now, until the out-of-tree implementation
---
Josh Cartwright (5):
zynq: use GIC device tree bindings
zynq: use pl310 device tree bindings
zynq: remove use of CLKDEV_LOOKUP
ARM: annotate VMALLOC_END definition with _AC
zynq: move static peripheral mappings
arch/arm/Kconfig | 1 -
arch/arm/Makefile
The Zynq uses the cortex-a9-gic. This eliminates the need to hardcode
register addresses.
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
Cc: John Linn john.l...@xilinx.com
Acked-by: Arnd Bergmann a...@arndb.de
---
arch/arm/boot/dts/zynq-ep107.dts | 8 +---
arch/arm/mach
The Zynq has a PL310 L2 cache controller. Convert in-tree uses to using
the device tree.
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
Cc: John Linn john.l...@xilinx.com
Acked-by: Arnd Bergmann a...@arndb.de
---
arch/arm/boot/dts/zynq-ep107.dts | 9 +
arch/arm/mach
by removing this line from arch/arm/Makefile:
plat-$(CONFIG_ARCH_ZYNQ) += versatile
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
Cc: John Linn john.l...@xilinx.com
Acked-by: Arnd Bergmann a...@arndb.de
---
arch/arm/Kconfig | 1 -
arch/arm/Makefile
This makes the definition of VMALLOC_END suitable for use within
assembly code. This is necessary to allow the use of VMALLOC_END in
defining where the early uart is mapped for use with DEBUG_LL.
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
Acked-by: Arnd Bergmann a...@arndb.de
ioremap().
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
Cc: John Linn john.l...@xilinx.com
Acked-by: Arnd Bergmann a...@arndb.de
---
arch/arm/mach-zynq/common.c| 6 +++---
arch/arm/mach-zynq/include/mach/zynq_soc.h | 23 +--
2 files changed, 16 insertions
On Thu, Oct 25, 2012 at 04:17:01PM -0400, Nick Bowler wrote:
Hi Josh,
On 2012-10-24 15:04 -0500, Josh Cartwright wrote:
Shifting them up into the vmalloc region prevents the following warning,
when booting a zynq qemu target with more than 512mb of RAM:
[...]
-/* For now, all mappings
On Thu, Oct 25, 2012 at 06:41:08PM -0400, Nick Bowler wrote:
On 2012-10-25 16:29 -0500, Josh Cartwright wrote:
On Thu, Oct 25, 2012 at 04:17:01PM -0400, Nick Bowler wrote:
Did you test this on any real hardware? I can't get the ZC702 to work
with the UART mapped at this address
On Sat, Oct 27, 2012 at 01:39:00PM +, Michal Simek wrote:
Hi Josh,
-Original Message-
From: Josh Cartwright [mailto:josh.cartwri...@ni.com]
Sent: Wednesday, October 24, 2012 10:03 PM
To: a...@kernel.org; Arnd Bergmann
Cc: linux-kernel@vger.kernel.org; linux-arm-ker
On Sat, Oct 27, 2012 at 02:06:45PM +, Michal Simek wrote:
[...]
I am not big fan to use dtsi solution because dts can be simple generated
directly
From Xilinx design tool based on your hw design. That's why I can't see any
benefit
To have dtsi file.
Can I ask you to reconsider? We,
This makes the definition of VMALLOC_END suitable for use within
assembly code. This is necessary to allow the use of VMALLOC_END in
defining where the early uart is mapped for use with DEBUG_LL.
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
Acked-by: Arnd Bergmann a...@arndb.de
The Zynq uses the cortex-a9-gic. This eliminates the need to hardcode
register addresses.
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
Cc: John Linn john.l...@xilinx.com
Acked-by: Arnd Bergmann a...@arndb.de
---
arch/arm/boot/dts/zynq-ep107.dts | 10 ++
arch/arm/mach
the secret use of
plat-versatile by removing this line from arch/arm/Makefile:
plat-$(CONFIG_ARCH_ZYNQ) += versatile
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
Cc: John Linn john.l...@xilinx.com
Acked-by: Arnd Bergmann a...@arndb.de
Tested-by: Michal Simek michal.si
The Zynq has a PL310 L2 cache controller. Convert in-tree uses to using
the device tree.
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
Cc: John Linn john.l...@xilinx.com
Acked-by: Arnd Bergmann a...@arndb.de
Acked-by: Michal Simek michal.si...@xilinx.com
---
arch/arm/boot/dts/zynq-ep107
- Added a cover letter
- Elaborated a bit on why I removed CLKDEV_LOOKUP
---
Josh Cartwright (5):
zynq: use GIC device tree bindings
zynq: use pl310 device tree bindings
zynq: remove use of CLKDEV_LOOKUP
ARM: annotate VMALLOC_END definition with _AC
zynq: move static peripheral mappings
ioremap().
There are currently unknown issues with the early uart mapping. For
now, the uart will be mapped to a known working address.
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
Cc: John Linn john.l...@xilinx.com
Acked-by: Arnd Bergmann a...@arndb.de
---
arch/arm/mach-zynq/common.c
On Sun, Oct 28, 2012 at 05:26:05PM -0600, Josh Cartwright wrote:
Michal-
Ugh, sorry everyone, I fatfingered the subject line. This is indeed v5.
Josh
pgpQ4dxD3axJl.pgp
Description: PGP signature
On Mon, Oct 29, 2012 at 07:24:16AM +, Michal Simek wrote:
Hi Josh,
Michal-
Here is a v5 of the zynq cleanup patchset that addresses your
feedback. I've intentionally left patches 4 and 5 in the set until
we figure out the appropriate way to get them in tree (feel free to
just
Kernel: arch/arm/boot/Image is ready
LD arch/arm/boot/compressed/vmlinux
OBJCOPY arch/arm/boot/zImage
Kernel: arch/arm/boot/zImage is ready
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
---
arch/arm/boot/Makefile | 10 +-
arch/arm/tools/Makefile | 2 +-
2 files changed, 6
...@elliptictech.com
Tested-by: Josh Cartwright josh.cartwri...@ni.com
Now that v5 of the initial zynq cleanup patchset is queued up for
merging (with a workaround for the uart mapping problem), what would it
take for you to sign off on this patch?
There is some trivial merging that has to be done
Suggested cleanup by Arnd Bergmann. Move the ttc timer.c code to
drivers/clocksource, and out of the mach-zynq directory.
The common.h (which only held the timer declaration) was renamed to
xilinx_ttc.h and moved into include/linux.
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
Cc: Arnd
On Thu, Nov 08, 2012 at 03:28:07PM -0800, Soren Brinkmann wrote:
One note below:
On Wed, Oct 31, 2012 at 12:58:52PM -0600, Josh Cartwright wrote:
[..]
--- /dev/null
+++ b/drivers/clk/clk-zynq.c
[..]
+struct zynq_periph_clk {
+ struct clk_hw hw;
+ struct clk_onecell_data
Provide simplified models for the necessary clocks on the zynq-7000
platform. Currently, the PLLs, the CPU clock network, and the basic
peripheral clock networks (for SDIO, SMC, SPI, QSPI, UART) are modelled.
OF bindings are also provided and documented.
Signed-off-by: Josh Cartwright
CC arch/arm/mach-sunxi/sunxi.o
./arch/arm/mach-sunxi/sunxi.c: In function 'sunxi_restart':
./arch/arm/mach-sunxi/sunxi.c:55:3: error: implicit declaration of function
'mdelay' [-Werror=implicit-function-declaration]
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
---
Fixes
On Sat, Dec 01, 2012 at 11:30:55AM -0800, Philip Balister wrote:
On 12/01/2012 08:56 AM, Greg KH wrote:
On Fri, Nov 30, 2012 at 07:19:16PM -0800, Philip Balister wrote:
[..]
I've been engaged in design discussions today with my customer. Our
target is the Xilinx Zynq hardware. The first pass
On Wed, Jan 09, 2013 at 07:12:00PM +0100, Lars-Peter Clausen wrote:
This driver adds support for the AXI clkgen pcore to the common clock
framework.
The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer
commonly found in Xilinx FPGAs.
The AXI clkgen pcore is used in
On Mon, Nov 19, 2012 at 05:27:17PM -0700, Stephen Warren wrote:
From: Stephen Warren swar...@nvidia.com
Move arch/arm/mach-tegra/timer.c to drivers/clocksource/tegra20_timer.c
so that the code is co-located with other clocksource drivers, and to
reduce the size of the mach-tegra directory.
On Tue, Nov 20, 2012 at 02:23:37PM +0100, Michal Simek wrote:
Remove empty unused mach/hardware.h.
mach/irqs.h is unused because SPARSE_IRQ are ON by default.
mach/timex.h is unused because of CONFIG_ARCH_MULTIPLATFORM.
Signed-off-by: Michal Simek michal.si...@xilinx.com
Tested-by: Josh
On Tue, Nov 20, 2012 at 12:20:05PM -0700, Stephen Warren wrote:
From: Stephen Warren swar...@nvidia.com
It is desirable to move all clocksource drivers to drivers/clocksource,
yet each requires its own initialization function. We'd rather not
pollute linux/ with a header for each function.
On Tue, Dec 18, 2012 at 04:16:33PM -0800, Soren Brinkmann wrote:
The acronym PSS is deprecated by Xilinx. The correct term, which is
also used in Xilinx documentation is PS (processing system).
This is just a search and replace:
- s/PSS/PS/g
- s/pss/ps/g
Signed-off-by: Soren Brinkmann
On Tue, Dec 18, 2012 at 04:16:32PM -0800, Soren Brinkmann wrote:
I started to put some effort on syncing the Xilinx Linux tree with mainline
and
the timer driver is my first victim.
Most commits are fixing style issues or clean up. Functionality is touched
only
in patches #2 and #7.
...@codeaurora.org
Cc: Josh Cartwright josh.cartwri...@ni.com
Cc: Soren Brinkmann soren.brinkm...@xilinx.com
---
drivers/clk/clk-zynq.c | 28 +---
1 file changed, 9 insertions(+), 19 deletions(-)
Stephen-
Is there a particular tree I should be testing this against? Booting this set
On Wed, Dec 19, 2012 at 10:20:30AM -0800, Stephen Boyd wrote:
On 12/19/12 09:26, Josh Cartwright wrote:
On Mon, Dec 17, 2012 at 01:02:15PM -0800, Stephen Boyd wrote:
[..]
Can you show the code at those line numbers? There are quite a few
WARN_ONs in that code and it's possible the WARN_ON
to add my:
Tested-by: Josh Cartwright josh.cartwri...@ni.com
Thanks,
Josh
pgpFKslWItlFz.pgp
Description: PGP signature
On Wed, Dec 19, 2012 at 12:30:21PM -0800, Stephen Boyd wrote:
On 12/19/12 11:22, Soren Brinkmann wrote:
[..]
A probably unique thing I do is, I set the status of uart0 to disabled.
This way
I can reuse my rootfs which does not run getty on ttyPS1. And this worked
fine
before.
On Fri, Dec 21, 2012 at 03:28:10PM +, Michal Simek wrote:
-Original Message-
From: Josh Cartwright [mailto:josh.cartwri...@ni.com]
Sent: Wednesday, December 19, 2012 9:54 PM
To: Stephen Boyd; Michal Simek
Cc: Soren Brinkmann; Mike Turquette; linux-kernel@vger.kernel.org
-off-by: Josh Cartwright josh.cartwri...@ni.com
---
arch/arm/mach-zynq/common.c| 5 -
arch/arm/mach-zynq/include/mach/zynq_soc.h | 6 +-
arch/arm/mach-zynq/timer.c | 1 -
3 files changed, 1 insertion(+), 11 deletions(-)
diff --git a/arch/arm/mach-zynq
Convert low-level debugging routines to make use of debug_ll_io_init().
This is part of the preparation for ARCH_MULTIPLATFORM support for Zynq.
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
---
arch/arm/Kconfig.debug | 1 +
.../mach/debug-macro.S = include
zynq_soc.h:
- Move SCU address definitions into common.c.
- Other #defines, such as PERIPHERAL_CLOCK_RATE, TTC0_BASE, etc, are
unused and can be dropped
Signed-off-by: Josh Cartwright josh.cartwri...@ni.com
---
arch/arm/Kconfig | 14 ++--
arch/arm
w/ CONFIG_ARCH_MULTIPLATFORM.
Thanks,
Josh
---
Josh Cartwright (3):
ARM: zynq: remove TTC early mapping
ARM: zynq: make use of debug_ll_io_init()
ARM: zynq: add support for ARCH_MULTIPLATFORM
arch/arm/Kconfig | 14 +-
arch/arm/Kconfig.debug
/clocksource by Stephen Warren.
Signed-off-by: Prashant Gaikwad pgaik...@nvidia.com
---
Prashant-
Sorry for the late response, but I finally got a chance to give this
patchset a spin on Zynq. For patches 1 and 6:
Reviewed-by: Josh Cartwright josh.cartwri...@ni.com
Tested-by: Josh Cartwright
On Mon, Jan 14, 2013 at 10:18:46PM +0100, Cong Ding wrote:
the variable ttccs allocated isn't freed when error occurs, so we call kfree
before return.
Signed-off-by: Cong Ding ding...@gmail.com
---
arch/arm/mach-zynq/timer.c | 25 -
1 file changed, 16
On Thu, Aug 22, 2013 at 04:10:54PM -0700, Greg Kroah-Hartman wrote:
On Fri, Aug 09, 2013 at 01:37:09PM -0700, Josh Cartwright wrote:
+static char dbgfs_help[] =
+ SPMI Debug-FS support\n
+ \n
+ Hierarchy schema:\n
+ /sys/kernel/debug/spmi\n
+ /help
Hey Stephen-
Thanks for the comments.
On Fri, Aug 23, 2013 at 03:58:36PM -0600, Stephen Warren wrote:
On 08/22/2013 01:59 PM, Josh Cartwright wrote:
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
I'm introducing this as an RFC, because there are set of assumptions
made
On Tue, Aug 27, 2013 at 03:55:19PM -0600, Stephen Warren wrote:
On 08/27/2013 11:01 AM, Josh Cartwright wrote:
...
If we want to ensure for the generic bindings that we are fulling
characterizing/describing the SPMI bus, then we'll additionally need to
tackle an additional identified
From: Sylwester Nawrocki s.nawro...@samsung.com
Add this empty macro definition so users can be compiled without
excluding this macro call with preprocessor directives when CONFIG_OF
is disabled.
Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com
Signed-off-by: Kyungmin Park
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
I'm introducing this as an RFC, because there are set of assumptions
made in this binding spec, that currently hold true for the supported
controller/addressing scheme for the Snapdragon 800 series, but don't
necessarily hold true for SPMI
command sequences on the SPMI bus. The status register is
read to determine when the command sequence has completed and whether
or not it completed successfully.
Signed-off-by: Kenneth Heitke khei...@codeaurora.org
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
drivers/spmi/Kconfig
Signed-off-by: Josh Cartwright jo...@codeaurora.org
---
.../bindings/spmi/qcom,spmi-pmic-arb.txt | 36 ++
1 file changed, 36 insertions(+)
create mode 100644
Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt
diff --git a/Documentation/devicetree
://www.mipi.org/specifications/system-power-management-interface
[2]: http://thread.gmane.org/gmane.linux.ports.arm.msm/4886
Josh Cartwright (2):
spmi: add generic SPMI controller binding documentation
spmi: document the PMIC arbiter SPMI bindings
Kenneth Heitke (2):
spmi: Linux driver framework
master
devices and up to 16 logical slaves.
The framework supports message APIs, multiple busses (1 controller
per bus) and multiple clients/slave devices per controller.
Signed-off-by: Kenneth Heitke khei...@codeaurora.org
Signed-off-by: Michael Bohan mbo...@codeaurora.org
Signed-off-by: Josh
On Wed, Aug 14, 2013 at 03:59:42PM +0300, Ivan T. Ivanov wrote:
From: Ivan T. Ivanov iiva...@mm-sol.com
These drivers handles control and configuration of the HS
and SS USB PHY transceivers. They are part of the driver
which manage Synopsys DesignWare USB3 controller stack
inside Qualcomm
On Thu, Aug 15, 2013 at 10:44:03AM -0700, Hanumant Singh wrote:
On 8/14/2013 12:29 PM, Linus Walleij wrote:
On Tue, Jul 30, 2013 at 1:39 AM, Bjorn Andersson bj...@kryo.se wrote:
On Wed, Jul 24, 2013 at 1:41 PM, Hanumant Singh hanum...@codeaurora.org
wrote:
As a general note on the patch,
1 - 100 of 806 matches
Mail list logo
