-schwarz.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/arm/mach-zynq/common.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 39c1c7d43522..af36dc2545c1 100644
--- a/arch/arm/mach-zynq
On 05/12/2015 08:31 AM, Dirk Behme wrote:
On 12.05.2015 08:22, Michal Simek wrote:
From: Thomas Betker thomas.bet...@rohde-schwarz.com
This patch is based on the
commit 1a8e41cd672f (ARM: 6395/1: VExpress: Set bit 22 in the PL310
(cache controller) AuxCtlr register)
I've been under
On 05/11/2015 06:10 PM, Joe Perches wrote:
On Mon, 2015-05-11 at 17:44 +0200, Michal Simek wrote:
On 05/11/2015 05:39 PM, Joe Perches wrote:
On Mon, 2015-05-11 at 17:26 +0200, Michal Simek wrote:
On 05/11/2015 04:42 PM, Joe Perches wrote:
On Mon, 2015-05-11 at 16:05 +0200, Michal Simek wrote
an
earlier one
include/asm-generic/io.h:584:16: originally declared here
The same patch was already applied to arm32 as
ARM: 7118/1: rename temp variable in read*_relaxed()
(sha1: b0c1264f534a1cb3c52036a23a04d238434a0df6)
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/arm64/include
On 04/15/2015 01:08 PM, Peter Hurley wrote:
On 04/14/2015 06:03 AM, Michal Simek wrote:
Do not probe all serial drivers by of_serial.c which are using
device_type = serial; property. Only drivers which have valid
compatible strings listed in the driver should be probed.
When PORT_UNKNOWN
Do not probe all serial drivers by of_serial.c which are using
device_type = serial; property. Only drivers which have valid
compatible strings listed in the driver should be probed.
When PORT_UNKNOWN probe will fail anyway.
Signed-off-by: Michal Simek michal.si...@xilinx.com
CC: sta
platform_get_irq() instead of platform_get_resource()
which is doing irq_desc allocation and driver itself can request IRQ.
Fix both xilinx serial drivers in the tree.
Signed-off-by: Michal Simek michal.si...@xilinx.com
CC: sta...@vger.kernel.org
---
drivers/tty/serial/uartlite.c | 11
Also check MMC OF properties. The controller supports MMC too.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/mmc/host/sdhci-of-arasan.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-arasan.c
b/drivers/mmc/host/sdhci
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
http://www.ceva-dsp.com/Company-Overview
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
b/Documentation/devicetree
:6: warning: symbol
'temac_adjust_link' was not declared. Should it be static?
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/net/ethernet/xilinx/ll_temac_main.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/xilinx
-1v84;
+ reg = 0xfd0c 0x200;
+ interrupt-parent = gic;
+ interrupts = 0 133 4;
+ clocks = clkc SATA_CLK_ID;
+ ceva,broken-gen2;
+ };
--
2.1.2
Acked-by: Michal Simek michal.si...@xilinx.com
FYI: Adding ceva prefix to vendor
Warnings found by sparse:
arch/microblaze/kernel/dma.c:157:5: warning: symbol
'dma_direct_mmap_coherent' was not declared. Should it be static?
arch/microblaze/kernel/kgdb.c:35:14: warning: symbol 'pvr' was not
declared. Should it be static?
Signed-off-by: Michal Simek michal.si...@xilinx.com
(ceva_ahci_driver);
+
+MODULE_DESCRIPTION(CEVA AHCI SATA platform driver);
+MODULE_AUTHOR(Xilinx Inc.);
+MODULE_LICENSE(GPL v2);
--
2.1.2
Tested-by: Michal Simek michal.si...@xilinx.com
Thanks,
Michal
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w: www.monstr.eu p: +42-0-721842854
Maintainer
On 06/09/2015 10:15 AM, Paul Bolle wrote:
On Tue, 2015-06-09 at 09:09 +0200, Michal Simek wrote:
On 06/09/2015 08:10 AM, Julia Lawall wrote:
On Tue, 9 Jun 2015, Michal Simek wrote:
Also sort of checking for this will be great. Julia?
If this requires checking the contents of comment
in the
MODULE_LICENSE() macro needs to change.
This is not just the problem with this driver but with others too.
Have you sent any patch to add GPL v2+ to license.h?
Also sort of checking for this will be great. Julia?
Thanks,
Michal
--
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w
On 06/09/2015 08:10 AM, Julia Lawall wrote:
On Tue, 9 Jun 2015, Michal Simek wrote:
Hi Paul,
On 05/22/2015 12:30 PM, Paul Bolle wrote:
Again, just a nit: a license mismatch.
On Thu, 2015-05-21 at 22:37 +0530, Kedareswara rao Appana wrote:
+ * This program is free software: you can
On 06/09/2015 09:21 AM, Paul Bolle wrote:
On Tue, 2015-06-09 at 08:03 +0200, Michal Simek wrote:
Have you sent any patch to add GPL v2+ to license.h?
GPL already means GPL v2 or later (see include/linux/module.h).
ok. I see.
Thanks,
Michal
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{
compatible = arasan,sdhci-8.9a;
status = disabled;
--
2.1.2
Reviewed-by: Michal Simek michal.si...@xilinx.com
Thanks,
Michal
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More
On 06/09/2015 01:59 PM, Paul Bolle wrote:
On Tue, 2015-06-09 at 12:41 +0200, Michal Simek wrote:
On 06/09/2015 10:15 AM, Paul Bolle wrote:
Mistakes I've seen made since I started checking this stuff (a few
months ago):
- typos in the license ident, say GPLv2, GPL V2, or BSD: generates
to keep it - if someone has used Proprietary then
they meant to do so, and they don't want checkpatch to keep telling them
they made a typo.
Any update on this patch?
Thanks,
Michal
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w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux
On 06/09/2015 02:24 PM, Paul Bolle wrote:
On Tue, 2015-06-09 at 14:12 +0200, Michal Simek wrote
ok. Will check all our drivers we have to get it synchronized but I
expect that a lot of drivers have problems there.
So do I. Cleaning that all up would add a lot of churn. I'm _not_
(zynq_gpio_driver);
+}
+module_exit(zynq_gpio_exit);
+
MODULE_AUTHOR(Xilinx Inc.);
MODULE_DESCRIPTION(Zynq GPIO driver);
MODULE_LICENSE(GPL);
Looks reasonable to me.
Tested-by: Michal Simek michal.si...@xilinx.com
Thanks,
Michal
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On 06/24/2015 10:36 PM, Paul Bolle wrote:
On Tue, 2015-06-23 at 11:00 -0700, Moritz Fischer wrote:
+MODULE_ALIAS(platform:xilinx-mailbox);
So I think this MODULE_ALIAS() is only useful if, in short, there's a
corresponding platform_device created. Ie, a platform_device with a
name
On 06/25/2015 09:31 AM, Paul Bolle wrote:
On Thu, 2015-06-25 at 08:55 +0200, Michal Simek wrote:
On 06/24/2015 10:36 PM, Paul Bolle wrote:
On Tue, 2015-06-23 at 11:00 -0700, Moritz Fischer wrote:
+MODULE_ALIAS(platform:xilinx-mailbox);
So I think this MODULE_ALIAS() is only useful
On 06/25/2015 11:35 AM, Paul Bolle wrote:
On Thu, 2015-06-25 at 09:47 +0200, Michal Simek wrote:
It has to be platform_device somewhere for sure.
In past we had folder in arch/microblaze/platform folder.
Currently you can add this code to for example
arch/microblaze/kernel/platform.c
cp error from berlin sata phy driver.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/phy/phy-berlin-usb.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/phy/phy-berlin-usb.c b/drivers/phy/phy-berlin-usb.c
index d7431f6ab975..762f0fbdc119
Remove unneeded space after tab.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/phy/phy-berlin-usb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/phy-berlin-usb.c b/drivers/phy/phy-berlin-usb.c
index 762f0fbdc119..0fe0d81c29ee 100644
There was big cleanup in past to remove this unneeded setting.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Can be also tracked by coccinelle script.
scripts/coccinelle/api/platform_no_drv_owner.cocci
---
drivers/phy/phy-berlin-usb.c | 1 -
1 file changed, 1 deletion(-)
diff --git
ff0a.gpio: Unbalanced pm_runtime_enable!
root@zynqmp:~# rmmod gpio_zynq
root@zynqmp:~# lsmod
Not tainted
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/gpio/gpio-zynq.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpio/gpio-zynq.c b/drivers/gpio/gpio-zynq.c
+ XGPIO_CHANNEL_OFFSET,
chip-gpio_dir[1]);
}
Reviewed-by: Michal Simek michal.si...@xilinx.com
Thanks,
Michal
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pci_dev declaration
Michal Simek (2):
microblaze: Add missing release version code
microblaze: Label local function static
arch/microblaze/include/asm/pci.h| 17 -
arch/microblaze/kernel/cpu/cpuinfo.c | 2 ++
arch/microblaze/kernel/dma.c | 1 +
arch
On 06/23/2015 08:00 PM, Moritz Fischer wrote:
The Xilinx LogiCORE IP mailbox is a FPGA core that allows for
interprocessor communication via AXI4 memory mapped / AXI4 stream
interfaces.
It is single channel per core and allows for transmit and receive.
Changes from v4:
- Have separate
, [\rx, #UART_FIFO_OFFSET] @ TXDATA
.endm
.macro waituart,rd,rx
ok - this works too.
Tested-by: Michal Simek michal.si...@xilinx.com
Thanks,
Michal
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Fix kernel-doc format validation to be able to use kernel-doc
script for checking it.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/firmware/memmap.c | 24 +---
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/drivers/firmware/memmap.c b
[] = {
- { .compatible = xlnx,zynq-gpio-1.0, },
- { /* end of table */ }
-};
-MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);
-
static struct platform_driver zynq_gpio_driver = {
.driver = {
.name = DRIVER_NAME,
Acked-by: Michal Simek michal.si...@xilinx.com
Thanks
On 05/28/2015 07:35 PM, Moritz Fischer wrote:
On Wed, May 27, 2015 at 10:45 PM, Michal Simek michal.si...@xilinx.com
wrote:
On 05/27/2015 08:35 PM, Moritz Fischer wrote:
The Xilinx LogiCORE IP mailbox is a FPGA core that allows for
interprocessor communication via AXI4 memory mapped / AXI4
;
+ };
I see you still keep there 0x3c but that's minor detail.
Acked-by: Michal Simek michal.si...@xilinx.com
Thanks,
Michal
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only one channel. */
+ chans[0].con_priv = mbox;
+ mbox-controller.dev = mbox-dev;
+ mbox-controller.num_chans = 1;
+ mbox-controller.chans = chans;
+ mbox-controller.ops = xilinx_mbox_ops;
+
+
only one empty line here but otherwise
Acked-by: Michal Simek michal.si
backward compatible string. There should be two
compatible strings.
Thanks,
Michal
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w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM
data to ICAP */
Tested-by: Michal Simek michal.si...@xilinx.com
Thanks,
Michal
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On 05/26/2015 06:12 PM, Moritz Fischer wrote:
On Mon, May 25, 2015 at 6:56 AM, Jingoo Han jingooh...@gmail.com wrote:
On Monday, May 25, 2015 3:05 PM, Michal Simek wrote:
On 05/22/2015 08:03 PM, Moritz Fischer wrote:
This patchset adds mailbox framework integration for the Xilinx LogiCORE IP
On 05/27/2015 10:52 PM, Sören Brinkmann wrote:
On Wed, 2015-05-27 at 03:00PM -0500, Nathan Sullivan wrote:
Use the new zynq binding for macb ethernet, since it will disable half
duplex gigabit like the Zynq TRM says to do. Also allow the compatible
cadence gem binding that won't disable half
On 05/27/2015 08:35 PM, Moritz Fischer wrote:
The Xilinx LogiCORE IP mailbox is a FPGA core that allows for
interprocessor communication via AXI4 memory mapped / AXI4 stream
interfaces.
It is single channel per core and allows for transmit and receive.
Changes from v1:
- Added common
On 05/27/2015 08:35 PM, Moritz Fischer wrote:
Changes from v1:
- Added common clock framework support
Changes from v0:
- Fixed example bindings
Signed-off-by: Moritz Fischer moritz.fisc...@ettus.com
---
.../bindings/mailbox/xilinx-mailbox.txt | 44
1 file
From: Shailendra Verma shailendra.capric...@gmail.com
The variable dirty is bool type. Hence assign the variable with
bool value true/false instead of 1/0.
Signed-off-by: Shailendra Verma shailendra.capric...@gmail.com
Tested-by: Michal Simek michal.si...@xilinx.com
---
drivers/char
a/MAINTAINERS b/MAINTAINERS
index a01df3088b01..f6b16941ae08 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1639,7 +1639,7 @@ M: Michal Simek michal.si...@xilinx.com
R: Sören Brinkmann soren.brinkm...@xilinx.com
L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers)
W
/arch/arm/include/debug/zynq.S
@@ -38,6 +38,7 @@
.endm
.macro senduart,rd,rx
+ARM_BE8( rev \rd, \rd )
str \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA
.endm
Tested-by: Michal Simek michal.si...@xilinx.com
Thanks,
Michal
On 05/22/2015 01:37 AM, Moritz Fischer wrote:
The Xilinx LogiCORE IP mailbox is a FPGA core that allows for
interprocessor communication via AXI4 memory mapped / AXI4 stream
interfaces.
It is single channel per core and allows for transmit and receive.
Signed-off-by: Moritz Fischer
On 05/22/2015 08:03 PM, Moritz Fischer wrote:
This patchset adds mailbox framework integration for the Xilinx LogiCORE IP
mailbox. The Xilinx LogiCORE IP mailbox is a fpga softcore that allows
interprocessor communication between AXI4 stream / memory mapped
processors.
Changes from v0:
On 05/22/2015 01:37 AM, Moritz Fischer wrote:
Signed-off-by: Moritz Fischer moritz.fisc...@ettus.com
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index f8e0afb..f1f0d10 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10986,6
On 05/22/2015 01:37 AM, Moritz Fischer wrote:
Signed-off-by: Moritz Fischer moritz.fisc...@ettus.com
---
.../bindings/mailbox/xilinx-mailbox.txt | 40
1 file changed, 40 insertions(+)
IRC the rule was to send binding first and then the driver.
diff --git
0x18ad /* Atmel AVR32 */
Applied.
We should probably also remove EM_MICROBLAZE_OLD which shouldn't be used
now.
Thanks,
Michal
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w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt
On 08/20/2015 08:18 AM, Vinod Koul wrote:
On Thu, Aug 20, 2015 at 11:41:33AM +0530, punnaiah choudary kalluri wrote:
+- interrupts: Should contain DMA channel interrupt
channel interrupt or interrupts, former says it is plural
ZynqMP DMA has single interrupt for each channel So, that is the
On 08/19/2015 06:50 PM, Will Deacon wrote:
On Wed, Aug 19, 2015 at 09:40:25AM +0100, Jens Wiklander wrote:
Adds helpers to do SMC based on ARM SMC Calling Convention.
CONFIG_HAVE_SMCCC is enabled for architectures that may support
the SMC instruction. It's the responsibility of the caller to
Hi,
On 08/21/2015 03:16 AM, Moritz Fischer wrote:
Hi,
your MUA produces funny messages somehow ...
The driver did not probe for me in it's current form as the bindings
were missing interrupt parents for the interrupts...
It is just a question where interrupt parent is listed. I have seen
arises.
Signed-off-by: Anirudha Sarangi anir...@xilinx.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/tty/serial/xilinx_uartps.c | 194 -
1 file changed, 104 insertions(+), 90 deletions(-)
diff --git a/drivers/tty/serial/xilinx_uartps.c
b
and IGNPAR are not set, this is the
optimal implementation for parity error handling.
Signed-off-by: Anirudha Sarangi anir...@xilinx.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/tty/serial/xilinx_uartps.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff
From: Anirudha Sarangi anirudha.sara...@xilinx.com
The existing implementation includes overrun errors under IGNPAR
option. This patch fixes it by including only parity and framing
error under IGNPAR option.
Signed-off-by: Anirudha Sarangi anir...@xilinx.com
Signed-off-by: Michal Simek michal.si
From: Anirudha Sarangi anirudha.sara...@xilinx.com
Existing set_termios does not handle the option for enabling
odd parity. This patch fixes it.
Signed-off-by: Anirudha Sarangi anir...@xilinx.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
drivers/tty/serial/xilinx_uartps.c | 2
;
} ;
} ;
Acked-by: Michal Simek michal.si...@xilinx.com
Thanks,
Michal
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On 08/24/2015 09:43 AM, Alexandre Belloni wrote:
On 19/08/2015 at 15:23:22 +0530, Suneel Garapati wrote :
adds support for RTC controller found on
Xilinx Zynq Ultrascale+ MPSoC platform.
Signed-off-by: Suneel Garapati suneel.garap...@xilinx.com
---
Changes v3
- fix checkpatch errors
-
Hi,
On 08/24/2015 10:08 AM, Alexandre Belloni wrote:
On 24/08/2015 at 09:48:42 +0200, Michal Simek wrote :
On 08/24/2015 09:43 AM, Alexandre Belloni wrote:
On 19/08/2015 at 15:23:22 +0530, Suneel Garapati wrote :
adds support for RTC controller found on
Xilinx Zynq Ultrascale+ MPSoC platform
From: Suneel Garapati suneel.garap...@xilinx.com
The Ceva ahci controller is available on the Xilinx Zynq UltraScale+
MPSoC.
Signed-off-by: Suneel Garapati suneel.garap...@xilinx.com
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/arm64/configs/defconfig | 4 ++--
1 file changed
On 07/28/2015 10:05 AM, Philipp Zabel wrote:
Am Freitag, den 24.07.2015, 17:21 -0700 schrieb Moritz Fischer:
Signed-off-by: Moritz Fischer moritz.fisc...@ettus.com
---
Documentation/devicetree/bindings/reset/zynq-reset-pl.txt | 13 +
1 file changed, 13 insertions(+)
create mode
On 07/27/2015 11:55 PM, Scott Branden wrote:
Hi Michal,
comment in line
On 15-07-24 06:53 AM, Michal Simek wrote:
The patch mmc: sdhci-of-arasan: Call OF parsing for MMC
(sha1: 16b23787fc709fe60c5d2bd05927b1a3da33d4e9) introduce new
dependency on GPIOLIB which calls mmc_of_parse
On 07/28/2015 08:59 AM, Nicolas Ferre wrote:
Le 28/07/2015 07:03, Moritz Fischer a écrit :
Hi Michal,
I agree we need to be careful with changing the bindings.
On Sun, Jul 26, 2015 at 11:56 PM, Michal Simek mon...@monstr.eu wrote:
Hi Moritz,
On 07/25/2015 02:21 AM, Moritz Fischer wrote
On 07/29/2015 07:38 PM, Sören Brinkmann wrote:
On Tue, 2015-07-28 at 11:14PM -0700, Moritz Fischer wrote:
Hi Sören,
On Tue, Jul 28, 2015 at 3:53 PM, Sören Brinkmann
soren.brinkm...@xilinx.com wrote:
On Mon, 2015-07-27 at 09:52PM -0700, Moritz Fischer wrote:
Hi Sören,
thanks for your
-by: Michal Simek michal.si...@xilinx.com
Thanks,
Michal
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On 08/04/2015 10:09 AM, Philipp Zabel wrote:
Hi Moritz,
Am Donnerstag, den 30.07.2015, 18:13 -0700 schrieb Moritz Fischer:
Signed-off-by: Moritz Fischer moritz.fisc...@ettus.com
---
.../devicetree/bindings/reset/zynq-reset.txt | 68
++
1 file changed, 68
On 07/28/2015 03:07 AM, Shawn Lin wrote:
On 2015/7/27 16:23, Michal Simek wrote:
On 07/27/2015 10:04 AM, Shawn Lin wrote:
This patch adds the interface to get quirks from dts, and
there is no need to assign different quirks by condition statement
of arasan IP version.
Signed-off-by: Shawn
On 07/27/2015 12:01 PM, Shubhrajyoti Datta wrote:
Hi,
On Mon, Jul 27, 2015 at 3:18 PM, Michal Simek michal.si...@xilinx.com wrote:
Add i2c eeprom memories on i2c bus.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts | 18
-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -1,5 +1,6 @@
config ARCH_ZYNQ
bool Xilinx Zynq ARM Cortex A9 Platform if ARCH_MULTI_V7
+ select ARCH_HAS_RESET_CONTROLLER
select ARCH_SUPPORTS_BIG_ENDIAN
select ARM_AMBA
select ARM_GIC
Reviewed-by: Michal Simek
Add i2c eeprom memories on i2c bus.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
Changes in v2:
- Change eeprom max freq from 100k to 400k
---
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts
)
static const struct of_device_id sdhci_arasan_of_match[] = {
{ .compatible = arasan,sdhci-8.9a },
+ { .compatible = arasan,sdhci-5.1 },
{ .compatible = arasan,sdhci-4.9a },
{ }
};
Acked-by: Michal Simek michal.si...@xilinx.com
Thanks,
Michal
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On 08/11/2015 03:34 AM, Shawn Lin wrote:
This patch adds the quirks and compatible string in sdhci-of-arasan.c
to support sdhci-arasan5.1 version of controller. No documented controller
IP version is found in the TRM, so we use ths version of command queueing
engine integrated into this
-ENOSYS.
Error log:
sdhci-arasan ff16.sdhci: parsing dt failed (4294967258)
sdhci-arasan: probe of ff16.sdhci failed with error -38
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
After RFC here https://lkml.org/lkml/2015/7/24/371
adding dependency on MMC_SDHCI.
---
drivers/mmc/host
On 08/05/2015 09:43 PM, Moritz Fischer wrote:
Michal,
On Tue, Aug 4, 2015 at 8:10 AM, Philipp Zabel p.za...@pengutronix.de wrote:
Hi Moritz,
Am Dienstag, den 04.08.2015, 08:05 -0700 schrieb Moritz Fischer:
Hi Philip,
On Tue, Aug 4, 2015 at 1:09 AM, Philipp Zabel p.za...@pengutronix.de
+linux-mmc
On 08/11/2015 04:53 PM, Michal Simek wrote:
On 08/11/2015 09:46 AM, Shawn Lin wrote:
This patch adds the compatible string in sdhci-of-arasan.c to
support sdhci-arasan5.1 version of controller. No documented
controller IP version is found in the TRM, so we use ths version
On 07/28/2015 06:55 AM, Moritz Fischer wrote:
Hi Michal,
On Sun, Jul 26, 2015 at 10:09 PM, Michal Simek mon...@monstr.eu wrote:
On 07/25/2015 02:21 AM, Moritz Fischer wrote:
Signed-off-by: Moritz Fischer moritz.fisc...@ettus.com
---
Documentation/devicetree/bindings/reset/zynq-reset
On 07/28/2015 06:59 AM, Moritz Fischer wrote:
Hi Michal,
On Mon, Jul 27, 2015 at 12:12 AM, Michal Simek mon...@monstr.eu wrote:
On 07/25/2015 02:21 AM, Moritz Fischer wrote:
This adds a reset controller driver to control the Xilinx Zynq
SoC's various resets.
Signed-off-by: Moritz Fischer
On 07/28/2015 07:03 AM, Moritz Fischer wrote:
Hi Michal,
I agree we need to be careful with changing the bindings.
On Sun, Jul 26, 2015 at 11:56 PM, Michal Simek mon...@monstr.eu wrote:
Hi Moritz,
On 07/25/2015 02:21 AM, Moritz Fischer wrote:
Signed-off-by: Moritz Fischer moritz.fisc
On 07/24/2015 09:25 AM, Philipp Zabel wrote:
Am Donnerstag, den 23.07.2015, 15:51 -0700 schrieb Moritz Fischer:
Signed-off-by: Moritz Fischer moritz.fisc...@ettus.com
---
Documentation/devicetree/bindings/reset/zynq-reset-pl.txt | 13 +
1 file changed, 13 insertions(+)
create
On 07/24/2015 12:51 AM, Moritz Fischer wrote:
Signed-off-by: Moritz Fischer moritz.fisc...@ettus.com
---
Documentation/devicetree/bindings/reset/zynq-reset-pl.txt | 13 +
1 file changed, 13 insertions(+)
create mode 100644
+ Kedar
On 07/23/2015 11:13 PM, Andrea Scian wrote:
Simply resetting the peripheral on RX FIFO overflow in not enough,
because we also need to re-initialize the whole device.
Also always enable RX FIFO overflow interrupt otherwise we may hang
until another interrupt arrives (this happens if
it.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq
;
+ compatible = xlnx,zynq-reset-pl;
Compatible property should go first.
I am missing that reg property
+ syscon = slcr;
+ };
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze
will be affected. Definitely this patch should be ACKed by Nicolas.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
ARCH_ZYNQ
bool Xilinx Zynq ARM Cortex A9 Platform if ARCH_MULTI_V7
select ARCH_SUPPORTS_BIG_ENDIAN
+ select ARCH_HAS_RESET_CONTROLLER
select ARM_AMBA
select ARM_GIC
select ARM_GLOBAL_TIMER if !CPU_FREQ
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng
Makefile
-obj-$(CONFIG_ARCH_ZYNQ) += clkc.o pll.o
+obj-y+= clkc.o pll.o
Applied to zynq/soc branch and will go to mainline via arm-soc.
Let me know if someone else wants to take it via different tree.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91
w
|= SDHCI_QUIRK2_HOST_NO_CMD23;
Also is there any binding which is done in this way?
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
The patch:
gpio: Added support to Zynq Ultrascale+ MPSoC
(sha1: bdf7a4ae371894b4dc10b5820006b0a82d484929)
added zynqmp specific features. This patch is switching the driver to
use the zynqmp compatible string.
Also enable the driver for ep108 platform.
Signed-off-by: Michal Simek michal.si
Also enable can0 for ep108.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts | 4
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 24
2 files changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp
Add usb nodes to DTSI and enable both of them on ep108.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts | 12
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 20
2 files changed, 32 insertions(+)
diff --git
Add SMMU DT node to DTSI.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index d58c9689c82a
Enable both sdhcis on ep108.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
index
Enable watchdog on ep108.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
index d6cc4b583587
Add i2c eeprom memories on i2c bus.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
b/arch/arm64/boot/dts/xilinx/zynqmp-ep108
Enable spi flashes on ep108.
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts | 34 +
1 file changed, 34 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
b/arch/arm64/boot/dts/xilinx/zynqmp
Hi Bjorn,
On 07/21/2015 05:40 PM, Bjorn Helgaas wrote:
On Tue, Jul 07, 2015 at 05:54:19PM +0100, Russell Joyce wrote:
Occasionally both MSI and INTx bits in the interrupt decode register are
set at once by the Xilinx AXI PCIe Bridge, so the MSI flag in the
interrupt message should be checked
.sdhci: parsing dt failed (4294967258)
sdhci-arasan: probe of ff16.sdhci failed with error -38
Signed-off-by: Michal Simek michal.si...@xilinx.com
---
This problem is probably in all others drivers.
This is one way how this can be solved.
Maybe better way is to block return value for cd and wp
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