.
Signed-off-by: Mikko Perttunen
---
v2:
- added target-v5-supply and target-12v-supply
- made sata power not always-on
arch/arm/boot/dts/tegra124-jetson-tk1.dts | 35 +++
1 file changed, 35 insertions(+)
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
b/arch/arm
This adds the integrated AHCI-compliant Serial ATA controller present
in Tegra124 systems-on-chip to the Tegra124 device tree.
Signed-off-by: Mikko Perttunen
---
v2:
- added clock-names property
- changed 0 -> GIC_SPI
arch/arm/boot/dts/tegra124.dtsi | 25 +
1 f
This makes the SATA PLL be controlled by hardware instead of software.
This is required for working SATA support.
Signed-off-by: Mikko Perttunen
Acked-by: Stephen Warren
---
drivers/clk/tegra/clk-pll.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/clk/tegra/clk-pll.c b
This patch adds device tree binding documentation for the SATA
controller found on NVIDIA Tegra SoCs.
Signed-off-by: Mikko Perttunen
---
v2:
- added target-5v-supply and target-12v-supply
- changed wording to be similar with other Tegra drivers
.../devicetree/bindings/ata/tegra-sata.txt
Hi,
This series adds support for the onboard AHCI-compliant Serial ATA
controller found on Tegra124 systems-on-chip. The series depends on
Thierry's XUSB pinctrl driver.
A branch containing the series is located at
git://github.com/cyndis/linux.git
branch ahci-rel-v2.
Mikko Pert
This adds the required information to reset the board during an overheating
situation to the Jetson TK1 device tree. The thermal reset is handled by the
PMC by sending an I2C message to the PMIC. The entries specify the I2C
message to be sent.
Signed-off-by: Mikko Perttunen
---
arch/arm/boot
o initiate a controller
shutdown. Should there be a new trip level for an uncontrolled shutdown?
Any thoughts would be appreciated.
Thanks,
Mikko Perttunen
Mikko Perttunen (5):
ARM: tegra: Add PMC thermtrip programming to Jetson TK1 device tree
ARM: tegra: Add soctherm and thermal zones to Tegra1
This adds support for the Tegra SOCTHERM thermal sensing and management
system found in the Tegra124 system-on-chip. Only polling-based thermal
sensing and overheating reset are supported for now.
Signed-off-by: Mikko Perttunen
---
drivers/thermal/Kconfig | 6 +
drivers/thermal
This adds the two clocks, soctherm and tsensor, to the T124 initialization
table.
They are required for soctherm-based thermal sensing.
Signed-off-by: Mikko Perttunen
---
drivers/clk/tegra/clk-tegra124.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/tegra/clk-tegra124.c b
This adds a device tree controlled option to enable PMC-based
thermal reset in overheating situations. Thermtrip is supported on
Tegra114 and Tegra124. The thermal reset only works when the thermal
sensors are calibrated, so a soctherm driver is also required.
Signed-off-by: Mikko Perttunen
This adds the soctherm thermal sensing and management unit to the
Tegra124 device tree along with the four thermal zones it exports.
Signed-off-by: Mikko Perttunen
---
arch/arm/boot/dts/tegra124.dtsi | 47 +
1 file changed, 47 insertions(+)
diff --git a
Yeah, I'll drop this one.
- Mikko
On 22/07/14 01:37, Stephen Warren wrote:
On 07/11/2014 08:18 AM, Mikko Perttunen wrote:
Remove the TEGRA124_CLK_EMC cell value define for tegra124-car
from the binding headers. This clock has never been able to do
anything and is being replaced w
Looks like the TRM doesn't document this either. I'll add an option
("nvidia,short-ram-code" ?) for the next version.
On 22/07/14 20:34, Stephen Warren wrote:
On 07/22/2014 11:22 AM, Andrew Bresticker wrote:
On Tue, Jul 22, 2014 at 9:45 AM, Stephen Warren wrote:
Does the bootloader adjust t
On 22/07/14 19:57, Stephen Warren wrote:
On 07/11/2014 08:18 AM, Mikko Perttunen wrote:
The driver is currently only tested on Tegra124 Jetson TK1, but should
work with other Tegra124 boards, provided that correct EMC tables are
provided through the device tree. Older chip models have differing
It might look nicer if the voltage table was in a separate file. A bit
of a border case, maybe.
On 11/07/14 00:42, Tuomas Tynkkynen wrote:
...
+ nvidia,pmic-voltage-table =
+ <0x1e 70>,
+ <0x1f 71>,
+ <0x20
This adds a new file, tegra124-jetson-tk1-emc.dtsi that contains
valid timings for the EMC memory clock. The file is included to the
main Jetson TK1 device tree.
Signed-off-by: Mikko Perttunen
---
arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi | 2323
arch/arm/boot/dts
Add binding documentation for the nvidia,tegra124-emc device tree
node.
Signed-off-by: Mikko Perttunen
---
.../bindings/memory-controllers/tegra-emc.txt | 42 ++
1 file changed, 42 insertions(+)
create mode 100644
Documentation/devicetree/bindings/memory-controllers
Add these clocks to the binding header so that EMC timings that have
them as parent can refer to the clocks.
Signed-off-by: Mikko Perttunen
---
include/dt-bindings/clock/tegra124-car.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/tegra124
This adds a node for the EMC memory controller. It is always enabled,
but only provides read-only functionality without board-specific
timing tables.
Signed-off-by: Mikko Perttunen
---
arch/arm/boot/dts/tegra124.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts
These clocks are used as parents for some EMC timings.
Signed-off-by: Mikko Perttunen
---
drivers/clk/tegra/clk-tegra124.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 99cc5ea..a4f8150 100644
--- a/drivers
These clocks have never been able to do anything.
Signed-off-by: Mikko Perttunen
---
drivers/clk/tegra/clk-tegra124.c | 13 -
1 file changed, 13 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 80efe51..99cc5ea 100644
--- a/drivers
gra_car TEGRA124_CLK_EMC>
instead of <&emc> or similar.
Signed-off-by: Mikko Perttunen
---
include/dt-bindings/clock/tegra124-car.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/tegra124-car.h
b/include/dt-bindings/clock/tegra124
/null
+++ b/drivers/clk/tegra/clk-emc.c
@@ -0,0 +1,1508 @@
+/*
+ * drivers/clk/tegra/clk-emc.c
+ *
+ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Author:
+ * Mikko Perttunen
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License
compile-time dependencies.
Patch 7 has a DTC dependency on patch 3.
Also available from git in
git://github.com/cyndis/linux.git, branch emc-v1
Mikko Perttunen (8):
clk: tegra124: Remove old emc_mux and emc clocks
ARM: tegra: Remove TEGRA124_CLK_EMC from tegra124-car.h
ARM: tegra: Add
On 07/11/2014 05:51 PM, Thierry Reding wrote:
On Fri, Jul 11, 2014 at 05:18:30PM +0300, Mikko Perttunen wrote:
Add binding documentation for the nvidia,tegra124-emc device tree
node.
Signed-off-by: Mikko Perttunen
---
.../bindings/memory-controllers/tegra-emc.txt | 42
Sure, I'll do that for v2.
On 07/11/2014 07:43 PM, Andrew Bresticker wrote:
On Fri, Jul 11, 2014 at 7:18 AM, Mikko Perttunen wrote:
Add binding documentation for the nvidia,tegra124-emc device tree
node.
diff --git a/Documentation/devicetree/bindings/memory-controllers/tegra-emc.t
Hi Hans, have you been able to take a look at this?
Thanks,
Mikko
On 08/07/14 16:22, Tejun Heo wrote:
(cc'ing Hans)
Hans, can you please review this patch?
On Wed, Jun 18, 2014 at 05:23:25PM +0300, Mikko Perttunen wrote:
+#define SATA_CONFIGURATION_0 0x180
+#d
Ok, that's good, thanks.
Mikko
On 14/07/14 09:25, Hans de Goede wrote:
Hi Miko,
On 07/14/2014 08:21 AM, Mikko Perttunen wrote:
Hi Hans, have you been able to take a look at this?
Not yet, it is on my todo list I hope to get around to
it today or tomorrow.
Regards,
Hans
On 11/07/14 19:01, Mikko Perttunen wrote:
On 07/11/2014 05:51 PM, Thierry Reding wrote:
On Fri, Jul 11, 2014 at 05:18:30PM +0300, Mikko Perttunen wrote:
...
...
In this case, all the registers that will be written are such that the
MC driver will never need to write them. They are shadowed
On 14/07/14 11:15, Thierry Reding wrote:
* PGP Signed by an unknown key
On Mon, Jul 14, 2014 at 10:55:51AM +0300, Mikko Perttunen wrote:
On 11/07/14 19:01, Mikko Perttunen wrote:
On 07/11/2014 05:51 PM, Thierry Reding wrote:
On Fri, Jul 11, 2014 at 05:18:30PM +0300, Mikko Perttunen wrote
On 14/07/14 12:31, Thierry Reding wrote:
* PGP Signed by an unknown key
On Mon, Jul 14, 2014 at 12:06:32PM +0300, Mikko Perttunen wrote:
On 14/07/14 11:15, Thierry Reding wrote:
Old Signed by an unknown key
On Mon, Jul 14, 2014 at 10:55:51AM +0300, Mikko Perttunen wrote:
On 11/07/14 19:01
On 14/07/14 13:29, Thierry Reding wrote:
* PGP Signed by an unknown key
> ...
Yes, this sounds sensible. I'll make such a patch. I suppose having another
timings table in the MC node with just the rate and mc-burst-data would
separate the concerns best. It occurs to me that we could also write
On 14/07/14 14:10, Thierry Reding wrote:
* PGP Signed by an unknown key
On Mon, Jul 14, 2014 at 01:54:36PM +0300, Mikko Perttunen wrote:
On 14/07/14 13:29, Thierry Reding wrote:
Old Signed by an unknown key
...
Yes, this sounds sensible. I'll make such a patch. I suppose having an
Heh, what you are describing is the v1 of this series :)
However,
17/06/14 Thierry Reding wrote:
> I would've preferred tegra_powergate_sequence_power_up() to be used
> consistently in all drivers. I'm still not convinced that using the
> platform AHCI driver this way is really the best option,
On 15/07/14 11:55, Hans de Goede wrote:
Hi,
On 07/15/2014 09:12 AM, Mikko Perttunen wrote:
Heh, what you are describing is the v1 of this series :)
However,
17/06/14 Thierry Reding wrote:
I would've preferred tegra_powergate_sequence_power_up() to be used
consistently in all drivers
Inline.
On 01/07/14 00:08, Stephen Warren wrote:
On 06/27/2014 02:11 AM, Mikko Perttunen wrote:
This adds support for hardware-tracked trip points to the device tree
thermal sensor framework.
The framework supports an arbitrary number of trip points. Whenever
the current temperature is
Inline.
On 30/06/14 23:48, Stephen Warren wrote:
On 06/27/2014 02:11 AM, Mikko Perttunen wrote:
This adds the soctherm thermal sensing and management unit to the
Tegra124 device tree along with the four thermal zones it exports.
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot
Inline.
On 01/07/14 00:23, Stephen Warren wrote:
On 06/27/2014 02:11 AM, Mikko Perttunen wrote:
This adds support for the Tegra SOCTHERM thermal sensing and management
system found in the Tegra124 system-on-chip. This initial driver supports
the four thermal zones with hardware-tracked trip
On 01/07/14 21:26, Stephen Warren wrote:
Ah, so there's some manufacturing calibration process that sets some
fuse value, and the HW uses a combination of that fuse value, and some
parameters of the manufacturing process as represented by the
SENSOR_CONFIG2 register, to apply the calibration?
On 01/07/14 21:15, Stephen Warren wrote:
The thermal core only supports a fixed number of trip points for each
driver and the core informs the driver of any changes to those, so
drivers using the core framework can already have hardware trip points,
but just a fixed number of them.
The way of-th
FWIW, from IRC, the series
> Tested-by: Steev Klimaszewski
On 24/06/14 22:35, Stephen Warren wrote:
On 06/18/2014 08:23 AM, Mikko Perttunen wrote:
This adds support for the integrated AHCI-compliant Serial ATA
controller present on the NVIDIA Tegra124 system-on-chip.
At a quick gla
This adds the soctherm thermal sensing and management unit to the
Tegra124 device tree along with the four thermal zones it exports.
Signed-off-by: Mikko Perttunen
---
arch/arm/boot/dts/tegra124.dtsi | 48 +
1 file changed, 48 insertions(+)
diff --git a
This adds support for the Tegra SOCTHERM thermal sensing and management
system found in the Tegra124 system-on-chip. This initial driver supports
the four thermal zones with hardware-tracked trip points.
Signed-off-by: Mikko Perttunen
---
drivers/thermal/Kconfig | 7 +
drivers
This adds critical trip points to the Jetson TK1 device tree.
The device will do a controlled shutdown when either the CPU, GPU
or MEM thermal zone reaches 101 degrees Celsius.
Signed-off-by: Mikko Perttunen
---
arch/arm/boot/dts/tegra124-jetson-tk1.dts | 32 +++
1
This adds the two clocks, soctherm and tsensor, to the T124 initialization
table.
They are required for soctherm-based thermal sensing.
Signed-off-by: Mikko Perttunen
---
Peter, one more zero for TSENSOR, please :)
drivers/clk/tegra/clk-tegra124.c | 2 ++
1 file changed, 2 insertions(+)
diff
Signed-off-by: Mikko Perttunen
---
drivers/thermal/of-thermal.c | 97 ++--
include/linux/thermal.h | 3 +-
2 files changed, 95 insertions(+), 5 deletions(-)
diff --git a/drivers/thermal/of-thermal.c b/drivers/thermal/of-thermal.c
index 04b1be7.
-tracked trip point support. While the
hardware supports four tracked trip points, only one is used.
Mikko Perttunen (6):
thermal: of: Add support for hardware-tracked trip points
of: Add bindings for nvidia,tegra124-soctherm
ARM: tegra: Add thermal trip points for Jetson TK1
ARM: tegra: Add
This adds binding documentation and headers for the Tegra124
SOCTHERM device tree node.
Signed-off-by: Mikko Perttunen
---
.../devicetree/bindings/thermal/tegra-soctherm.txt | 32 ++
include/dt-bindings/thermal/tegra124-soctherm.h| 15 ++
2 files changed, 47
On 08/07/14 16:08, Thierry Reding wrote:
* PGP Signed by an unknown key
On Mon, Jun 09, 2014 at 09:49:24PM +0300, Mikko Perttunen wrote:
On 06/09/2014 09:33 PM, Stephen Warren wrote:
On 06/06/2014 12:27 AM, Mikko Perttunen wrote:
The only compile-time dependencies here should be that
Thanks, I'll fix these.
On 08/07/14 16:22, Tejun Heo wrote:
(cc'ing Hans)
Hans, can you please review this patch?
On Wed, Jun 18, 2014 at 05:23:25PM +0300, Mikko Perttunen wrote:
+#define SATA_CONFIGURATION_0 0x180
+#defineSATA_CONFIGURATI
Thanks, will fix these. Looks like I will have to change the fuse code
to the old style as well.
On 09/07/14 09:49, Thierry Reding wrote:
* PGP Signed by an unknown key
On Wed, Jun 18, 2014 at 05:23:25PM +0300, Mikko Perttunen wrote:
[...]
diff --git a/drivers/ata/ahci_tegra.c b/drivers/ata
Does GK20A itself have any kind of thermal protection capabilities?
Upstream SOCTHERM support is not yet available (though I have a driver
in my tree), so we are thinking of disabling CPU DVFS on boards that
don't have always-on active cooling for now. Same might be necessary for
GPU as well.
Reviewed-by: Mikko Perttunen
Tested-by: Mikko Perttunen
On 10/07/14 14:46, Wolfram Sang wrote:
This driver has been flagged to drop class based instantiation. The removal
improves boot-up time and is unneeded for embedded controllers. Users have been
warned to switch for some time now, so we
ed to read the actual fuse once the
fuse series has landed.
Mikko Perttunen (8):
of: Add NVIDIA Tegra SATA controller binding
ARM: tegra: Add SATA controller to Tegra124 device tree
ARM: tegra: Add SATA and SATA power to Jetson TK1 device tree
clk: tegra: Enable hardware control of SATA PLL
This makes the SATA PLL be controlled by hardware instead of software.
This is required for working SATA support.
Signed-off-by: Mikko Perttunen
---
Already ACKed.
drivers/clk/tegra/clk-pll.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk
This adds ATA, SATA_AHCI and AHCI_TEGRA support to tegra_defconfig
so that the SATA support will be automatically enabled.
Signed-off-by: Mikko Perttunen
---
arch/arm/configs/tegra_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm
This adds the integrated AHCI-compliant Serial ATA controller present
in Tegra124 systems-on-chip to the Tegra124 device tree.
Signed-off-by: Mikko Perttunen
---
arch/arm/boot/dts/tegra124.dtsi | 25 +
1 file changed, 25 insertions(+)
diff --git a/arch/arm/boot/dts
The Tegra124 SATA controller requires 4 clocks. Increase this constant
to be able to use them all.
Signed-off-by: Mikko Perttunen
---
drivers/ata/ahci.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
index 5513296..2ed84e1 100644
This adds support for the integrated AHCI-compliant Serial ATA
controller present on the NVIDIA Tegra124 system-on-chip.
Signed-off-by: Mikko Perttunen
---
changes since v2:
- remove fuse reading: now there is no dependency on the fuse series,
so merging should be easier. always using the
This adds two clocks, SATA and SATA_OOB, to the Tegra124 clock initialization
table. The clocks are needed for working SATA support.
Signed-off-by: Mikko Perttunen
---
Already ACKed.
drivers/clk/tegra/clk-tegra124.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/tegra/clk
.
Signed-off-by: Mikko Perttunen
---
arch/arm/boot/dts/tegra124-jetson-tk1.dts | 35 +++
1 file changed, 35 insertions(+)
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
index 624b0fb..a4221e2 100644
--- a/arch/arm/boot
This patch adds device tree binding documentation for the SATA
controller found on NVIDIA Tegra SoCs.
Signed-off-by: Mikko Perttunen
---
.../devicetree/bindings/ata/tegra-sata.txt | 30 ++
1 file changed, 30 insertions(+)
create mode 100644 Documentation/devicetree
This patch adds device tree binding documentation for the SATA
controller found on NVIDIA Tegra SoCs.
Signed-off-by: Mikko Perttunen
---
v4: clarify mandatory clock order
.../devicetree/bindings/ata/tegra-sata.txt | 31 ++
1 file changed, 31 insertions(+)
create
This adds support for the integrated AHCI-compliant Serial ATA
controller present on the NVIDIA Tegra124 system-on-chip.
Signed-off-by: Mikko Perttunen
---
v4: init phy in power_on
drivers/ata/Kconfig | 9 ++
drivers/ata/Makefile | 1 +
drivers/ata/ahci_tegra.c | 406
Thanks for you comment. I decided to keep the format as is for now,
however, to keep a consistent style between all binding files describing
Tegra hardware.
Mikko
On 16/07/14 12:26, Varka Bhadram wrote:
On 07/16/2014 02:24 PM, Mikko Perttunen wrote:
This patch adds device tree binding
On 17/07/14 10:39, Thierry Reding wrote:
...
One other thing that I've been thinking about is whether it would make
sense to make the ahci_platform library use a list of clock names that
it should request. This would better mirror the clock bindings
convention and allow drivers (such as the Tegra
On 17/07/14 13:23, Hans de Goede wrote:
On 07/17/2014 09:56 AM, Mikko Perttunen wrote:
Also: is there a reason to not use the devm_* variants? I note that the helper
code has not been able to prevent any of the ahci_platform drivers from messing
up by not calling ahci_platform_put_resources
On 04/07/14 11:43, Wei Ni wrote:
On 06/27/2014 04:11 PM, Mikko Perttunen wrote:
This adds support for the Tegra SOCTHERM thermal sensing and management
system found in the Tegra124 system-on-chip. This initial driver supports
the four thermal zones with hardware-tracked trip points.
diff
Use a sequence for enabling hardware control of the SATA PLL
that works both when using the SATA lane with SATA and when
using it with XUSB.
Signed-off-by: Mikko Perttunen
---
Andrew: yes, it does :)
Peter: Feel free to squash if that works for you.
drivers/clk/tegra/clk-pll.c | 11
Hey Tejun,
the prerequisites for this series have now been acked and it would be
nice to have it for 3.17. Could you take a look at it?
Thanks,
Mikko
On 26/06/14 14:18, Mikko Perttunen wrote:
FWIW, from IRC, the series
> Tested-by: Steev Klimaszewski
On 24/06/14 22:35, Stephen War
Thanks, will remove.
- Mikko
On 05/06/14 15:18, Rob Herring wrote:
On Wed, Jun 4, 2014 at 6:32 AM, Mikko Perttunen wrote:
This adds support for the integrated AHCI-compliant Serial ATA
controller present on the NVIDIA Tegra124 system-on-chip.
Signed-off-by: Mikko Perttunen
submitted xusb series, the node isn't actually
named, though. I will fix this in v2)
- Mikko
On 05/06/14 20:29, Stephen Warren wrote:
On 06/04/2014 05:32 AM, Mikko Perttunen wrote:
Hi,
This series adds support for the onboard AHCI-compliant Serial ATA
controller found on Tegra124 syste
Yes, that might be the easiest. If you go that way, you should probably
also add an #include for the XUSB binding include file.
- Mikko
On 06/06/14 10:11, Thierry Reding wrote:
* PGP Signed by an unknown key
On Fri, Jun 06, 2014 at 09:27:07AM +0300, Mikko Perttunen wrote:
The only compile
returned even when a PHY is needed.
This patch modifies the -ENOSYS case to check if a "phys"
device tree node exists. If it exists, then clearly the PHY
subsystem is mistakenly disabled and the driver cannot work,
ahci_platform_get_resources will fail and propagate the error.
Signed-off
On 06/09/2014 09:33 PM, Stephen Warren wrote:
On 06/06/2014 12:27 AM, Mikko Perttunen wrote:
The only compile-time dependencies here should be that:
- patch 8 of 9 which contains the actual driver depends on patch 6 of 9
(though only when building as a module) and the efuse series
- patch 2
On 05/06/14 16:09, Peter De Schrijver wrote:
...
+int tegra_fuse_readl(u32 offset, u32 *val)
+{
+ if (!fuse_readl)
+ return -ENXIO;
+
+ *val = fuse_readl(offset);
+
+ return 0;
+}
+
-EPROBE_DEFER would be a better error value, so that drivers can work
even if th
This makes the SATA PLL be controlled by hardware instead of software.
This is required for working SATA support.
Signed-off-by: Mikko Perttunen
---
drivers/clk/tegra/clk-pll.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
This symbol needs to be exported to power on rails without using
tegra_powergate_sequence_power_up. tegra_powergate_sequence_power_up
cannot be used in situations where the driver wants to handle clocking
by itself.
Signed-off-by: Mikko Perttunen
---
arch/arm/mach-tegra/powergate.c | 1 +
1
This adds ATA, SATA_AHCI and AHCI_TEGRA support to tegra_defconfig
so that the SATA support will be automatically enabled.
Signed-off-by: Mikko Perttunen
---
arch/arm/configs/tegra_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm
This adds support for the integrated AHCI-compliant Serial ATA
controller present on the NVIDIA Tegra124 system-on-chip.
Signed-off-by: Mikko Perttunen
---
drivers/ata/Kconfig | 9 ++
drivers/ata/Makefile | 1 +
drivers/ata/ahci_tegra.c | 386
series is located at
git://github.com/cyndis/linux.git
branch ahci-rel.
Mikko Perttunen (9):
of: Add NVIDIA Tegra SATA controller binding
ARM: tegra: Add SATA controller to Tegra124 device tree
ARM: tegra: Add SATA and SATA power to Jetson TK1 device tree
clk: tegra: Enable hardware
.
Signed-off-by: Mikko Perttunen
Cc: devicet...@vger.kernel.org
---
arch/arm/boot/dts/tegra124-jetson-tk1.dts | 36 +++
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
index 38d3087
The Tegra AHCI device requires four clocks, so increase the maximum
amount of handled clocks from three to four.
Signed-off-by: Mikko Perttunen
---
drivers/ata/ahci.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
index 05882e4
This patch adds device tree binding documentation for the SATA
controller found on NVIDIA Tegra SoCs.
Signed-off-by: Mikko Perttunen
Cc: devicet...@vger.kernel.org
---
.../devicetree/bindings/ata/tegra-sata.txt | 29 ++
1 file changed, 29 insertions(+)
create mode
This adds the integrated AHCI-compliant Serial ATA controller present
in Tegra124 systems-on-chip to the Tegra124 device tree.
Signed-off-by: Mikko Perttunen
Cc: devicet...@vger.kernel.org
---
arch/arm/boot/dts/tegra124.dtsi | 24
1 file changed, 24 insertions(+)
diff
This adds two clocks, SATA and SATA_OOB, to the Tegra124 clock initialization
table. The clocks are needed for working SATA support.
Signed-off-by: Mikko Perttunen
---
drivers/clk/tegra/clk-tegra124.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/tegra/clk-tegra124.c b
It should be mentioned that calling clk_set_rate on the EMC clock
currently does absolutely nothing (except probably returning an error).
The rate switching sequence is not implemented (nor is the clock tree
entirely correct. For example, the kernel thinks that PLL_M is disabled).
Another note
The tegra-cpufreq driver is only for Tegra20, an upcoming driver for
Tegra124 will be separate, so this is not needed.
Thanks,
- Mikko
On 06/16/2014 04:35 PM, Tomeu Vizoso wrote:
Instead of setting a direct correlation to the CPU frequency. This allows
for other devices to influence the final
returned even when a PHY is needed.
This patch modifies the -ENOSYS case to check if a "phys"
device tree node exists. If it exists, then clearly the PHY
subsystem is mistakenly disabled and the driver cannot work,
ahci_platform_get_resources will fail and propagate the error.
Signed-off
I'll try removing use of all libahci_platform stuff except
ahci_platform_init_host for v2.
On 17/06/14 15:13, Thierry Reding wrote:
* PGP Signed by an unknown key
On Mon, Jun 16, 2014 at 04:01:02PM -0600, Stephen Warren wrote:
On 06/04/2014 05:32 AM, Mikko Perttunen wrote:
This symbol
On 06/17/2014 07:15 PM, Stephen Warren wrote:
On 06/17/2014 06:16 AM, Tomeu Vizoso wrote:
On 06/16/2014 10:02 PM, Stephen Warren wrote:
On 06/16/2014 07:35 AM, Tomeu Vizoso wrote:
This binding looks quite anaemic vs.
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt; I
would
On 06/17/2014 08:04 PM, Bartlomiej Zolnierkiewicz wrote:
Hi,
On Tuesday, June 17, 2014 10:10:23 AM Stephen Warren wrote:
On 06/17/2014 06:14 AM, Bartlomiej Zolnierkiewicz wrote:
[...]
+static struct platform_driver tegra_ahci_driver = {
+ .probe = tegra_ahci_probe,
+ .remove =
On 20/08/14 23:25, Stephen Warren wrote:
On 08/13/2014 06:41 AM, Mikko Perttunen wrote:
This adds a device tree controlled option to enable PMC-based
thermal reset in overheating situations. Thermtrip is supported on
Tegra30, Tegra114 and Tegra124. The thermal reset only works when
the thermal
On 21/08/14 18:40, Stephen Warren wrote:
On 08/21/2014 07:11 AM, Mikko Perttunen wrote:
On 20/08/14 23:25, Stephen Warren wrote:
On 08/13/2014 06:41 AM, Mikko Perttunen wrote:
This adds a device tree controlled option to enable PMC-based
thermal reset in overheating situations. Thermtrip is
FWIW, please fix the authorship information for next version.
Cheers,
Mikko
On 25/08/14 09:29, Wei Ni wrote:
From: lightning314
Split set&show temp codes as common functions, so we can use it
directly when implement linux thermal framework.
And handle error return value for the lm90_select_re
On 25/08/14 20:23, Stephen Warren wrote:
On 07/16/2014 02:54 AM, Mikko Perttunen wrote:
This adds the integrated AHCI-compliant Serial ATA controller present
in Tegra124 systems-on-chip to the Tegra124 device tree.
I have applied patches 2 and 3 to Tegra's for-3.18/dt branch. I fixed
t
On 25/08/14 22:22, Stephen Warren wrote:
On 08/18/2014 11:08 AM, Andrew Bresticker wrote:
In addition to the PCIe and SATA PHYs, the XUSB pad controller also
supports 3 UTMI, 2 HSIC, and 2 USB3 PHYs. Each USB3 PHY uses a single
PCIe or SATA lane and is mapped to one of the three UTMI ports.
Th
On 25/08/14 20:40, Stephen Warren wrote:
On 07/11/2014 08:18 AM, Mikko Perttunen wrote:
Hi everyone,
this series adds support for the EMC (external memory controller) clock
in the Tegra124 system-on-chip. The series has been tested on Jetson TK1.
The first two patches remove the old "em
On 26/08/14 10:47, Thierry Reding wrote:
* PGP Signed by an unknown key
On Tue, Aug 26, 2014 at 10:42:21AM +0300, Mikko Perttunen wrote:
On 25/08/14 20:40, Stephen Warren wrote:
On 07/11/2014 08:18 AM, Mikko Perttunen wrote:
Hi everyone,
this series adds support for the EMC (external memory
: Mikko Perttunen
---
v2: reordered and separated includes
drivers/ata/ahci_tegra.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/ata/ahci_tegra.c b/drivers/ata/ahci_tegra.c
index f1fef74..0329044 100644
--- a/drivers/ata/ahci_tegra.c
+++ b/drivers/ata
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