Eduardo: ping
Cheers,
Mikko
On 09/29/2014 05:17 PM, Mikko Perttunen wrote:
From: Mikko Perttunen mperttu...@nvidia.com
This adds support for the Tegra SOCTHERM thermal sensing and management
system found in the Tegra124 system-on-chip. This initial driver supports
temperature polling for four
At least this and 11/12 have lost my Signed-off-by.
Mikko
On 10/21/2014 05:45 PM, Tomeu Vizoso wrote:
From: Mikko Perttunen mperttu...@nvidia.com
The EMC driver needs to know the number of external memory devices and also
needs to update the EMEM configuration based on the new rate
On 10/21/2014 05:45 PM, Tomeu Vizoso wrote:
Needed to properly decode the ram code register.
Signed-off-by: Tomeu Vizoso tomeu.viz...@collabora.com
---
Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git
From: Mikko Perttunen mperttu...@nvidia.com
Currently the i2c-tegra bus driver prepares, enables
and set_rates its clocks separately for each transfer.
This causes locking problems when doing I2C transfers
from clock notifiers; see
http://lists.infradead.org/pipermail/linux-arm-kernel/2014-July
PM, Stephen Warren wrote:
On 08/21/2014 10:53 AM, Thierry Reding wrote:
On Thu, Aug 21, 2014 at 09:38:29AM -0600, Stephen Warren wrote:
On 08/21/2014 12:58 AM, Thierry Reding wrote:
On Wed, Aug 20, 2014 at 02:16:49PM -0600, Stephen Warren wrote:
On 08/13/2014 06:41 AM, Mikko Perttunen wrote
wrote:
On 26 August 2014 09:42, Mikko Perttunen mperttu...@nvidia.com wrote:
On 25/08/14 20:40, Stephen Warren wrote:
On 07/11/2014 08:18 AM, Mikko Perttunen wrote:
Hi everyone,
this series adds support for the EMC (external memory controller) clock
in the Tegra124 system-on-chip. The series
From: Mikko Perttunen mperttu...@nvidia.com
This adds a device tree controlled option to enable PMC-based
thermal reset in overheating situations. Thermtrip is supported on
Tegra30, Tegra114 and Tegra124. The thermal reset only works when
the thermal sensors are calibrated, so a soctherm driver
From: Mikko Perttunen mperttu...@nvidia.com
Sometimes, hardware blocks want to issue requests to devices
connected to I2C buses by itself. In such case, the bus the
target device resides on must be configured into a register.
For this purpose, each I2C controller has a defined ID known
From: Mikko Perttunen mperttu...@nvidia.com
I2C controller ids are required when programming hardware blocks
that send messages to devices connected to an I2C bus, such as
when the PMC sends a poweroff message to the PMIC. Add ids
to all I2C controllers in Tegra124.
Signed-off-by: Mikko
the sensors.
Git repo at
git://github.com/cyndis/linux.git pmc-thermtrip-v3
Mikko Perttunen (5):
of: Add descriptions of thermtrip properties to Tegra PMC bindings
of: Add nvidia,controller-id property to Tegra I2C bindings
ARM: tegra124: Add I2C controller ids to device tree
ARM: tegra: Add
From: Mikko Perttunen mperttu...@nvidia.com
Hardware-triggered thermal reset requires configuring the I2C
reset procedure. This configuration is read from the device tree,
so document the relevant properties in the binding documentation.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
From: Mikko Perttunen mperttu...@nvidia.com
This adds the required information to reset the board during an overheating
situation to the Jetson TK1 device tree. The thermal reset is handled by the
PMC by sending an I2C message to the PMIC. The entries specify the I2C
message to be sent.
Signed
From: Mikko Perttunen mperttu...@nvidia.com
Hardware-triggered thermal reset requires configuring the I2C
reset procedure. This configuration is read from the device tree,
so document the relevant properties in the binding documentation.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
On 10/24/2014 06:08 PM, Vladimir Zapolskiy wrote:
Hello Mikko,
Hello Vladimir!
On 24.10.2014 17:39, Mikko Perttunen wrote:
From: Tuomas Tynkkynen ttynkky...@nvidia.com
Add shared code to support the Tegra DFLL clocksource in open-loop
mode. This root clocksource is present on the Tegra124
devices, which rely on this
code.
Signed-off-by: Paul Walmsley pwalms...@nvidia.com
Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
---
v6:
- disable clks if resume fails
- cosmetic fix in error handling
drivers/clk/tegra/Makefile |1
-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
---
v6:
- return unrounded rates from clk_round_rate and clk_recalc_rate. The rounded
rate doesn't make much sense for a voltage controlled oscillator and cpufreq
freaks out if any rounding
pointed by
With that minor one fixed,
Tested-by: Mikko Perttunen mikko.perttu...@kapsi.fi
Reviewed-by: Mikko Perttunen mikko.perttu...@kapsi.fi
Cheers,
Mikko
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More majordomo
On 11/19/2014 05:41 PM, Mikko Perttunen wrote:
On 11/18/2014 04:39 PM, Eduardo Valentin wrote:
Different drivers request API extensions in of-thermal. For this reason,
additional callbacks are required to fit the new drivers needs.
The current API implementation expects the registering sensor
On 09/17/2014 01:40 AM, Stephen Warren wrote:
That's a huge time-sink, unless I work out NFS root,
which probably isn't properly or easily supported by any distro.
FWIW, this is how I've been working, and it hasn't been /that/ difficult
to get working. The Tegra side is trivial, just append
Hi,
this series adds support for the thermal monitoring features of the
soctherm unit on the Tegra124 SoC.
The branch is also available in my github repo,
git://github.com/cyndis/linux.git soctherm-v6
Thanks,
Mikko
Mikko Perttunen (4):
of: Add bindings for nvidia,tegra124-soctherm
ARM
From: Mikko Perttunen mperttu...@nvidia.com
This adds critical trip points to the Jetson TK1 device tree.
The device will do a controlled shutdown when either the CPU, GPU
or MEM thermal zone reaches 101 degrees Celsius.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
---
v6: added comments
From: Mikko Perttunen mperttu...@nvidia.com
This adds support for the Tegra SOCTHERM thermal sensing and management
system found in the Tegra124 system-on-chip. This initial driver supports
temperature polling for four thermal zones.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
---
v6
From: Mikko Perttunen mperttu...@nvidia.com
This adds binding documentation and headers for the Tegra124
SOCTHERM device tree node.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
Acked-by: Stephen Warren swar...@nvidia.com
Acked-by: Eduardo Valentin edubez...@gmail.com
---
.../devicetree
From: Mikko Perttunen mperttu...@nvidia.com
This adds the soctherm thermal sensing and management unit to the
Tegra124 device tree along with the four thermal zones corresponding
to the four thermal sensors provided by soctherm.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
---
arch/arm
On 09/26/2014 01:19 PM, Thierry Reding wrote:
On Fri, Sep 26, 2014 at 12:43:09PM +0300, Mikko Perttunen wrote:
Hi,
this series adds support for the thermal monitoring features of the
soctherm unit on the Tegra124 SoC.
The branch is also available in my github repo,
git://github.com/cyndis
On 09/26/2014 02:48 PM, Thierry Reding wrote:
On Fri, Sep 26, 2014 at 01:22:52PM +0300, Mikko Perttunen wrote:
On 09/26/2014 01:19 PM, Thierry Reding wrote:
On Fri, Sep 26, 2014 at 12:43:09PM +0300, Mikko Perttunen wrote:
Hi,
this series adds support for the thermal monitoring features
On 09/26/2014 03:05 PM, Thierry Reding wrote:
On Fri, Sep 26, 2014 at 03:00:11PM +0300, Mikko Perttunen wrote:
On 09/26/2014 02:48 PM, Thierry Reding wrote:
On Fri, Sep 26, 2014 at 01:22:52PM +0300, Mikko Perttunen wrote:
On 09/26/2014 01:19 PM, Thierry Reding wrote:
On Fri, Sep 26, 2014
On 09/26/2014 02:45 PM, Thierry Reding wrote:
On Fri, Sep 26, 2014 at 12:43:13PM +0300, Mikko Perttunen wrote:
From: Mikko Perttunen mperttu...@nvidia.com
This adds support for the Tegra SOCTHERM thermal sensing and management
system found in the Tegra124 system-on-chip. This initial driver
On 09/29/2014 11:29 AM, Thierry Reding wrote:
On Fri, Sep 26, 2014 at 11:28:31PM +0300, Mikko Perttunen wrote:
On 09/26/2014 02:45 PM, Thierry Reding wrote:
[...]
I think a more idiomatic way to write this would be:
static int
calculate_tsensor_calibration(const struct tegra_tsensor *sensor
On 09/27/2014 03:06 PM, Juha-Matti Tilli wrote:
On Fri, Sep 26, 2014 at 11:28:31PM +0300, Mikko Perttunen wrote:
I think a more idiomatic way to write this would be:
static int
calculate_tsensor_calibration(const struct tegra_tsensor *sensor,
struct
From: Mikko Perttunen mperttu...@nvidia.com
This adds support for the Tegra SOCTHERM thermal sensing and management
system found in the Tegra124 system-on-chip. This initial driver supports
temperature polling for four thermal zones.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
---
v7
From: Tuomas Tynkkynen ttynkky...@nvidia.com
The Tegra124 will use a different driver for frequency scaling, so
rename the old driver (which handles only Tegra20) appropriately.
Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
From: Mikko Perttunen mperttu...@nvidia.com
Hardware-triggered thermal reset requires configuring the I2C
reset procedure. This configuration is read from the device tree,
so document the relevant properties in the binding documentation.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
From: Mikko Perttunen mperttu...@nvidia.com
This adds the required information to reset the board during an overheating
situation to the Jetson TK1 device tree. The thermal reset is handled by the
PMC by sending an I2C message to the PMIC. The entries specify the I2C
message to be sent.
Signed
From: Mikko Perttunen mperttu...@nvidia.com
I2C controller ids are required when programming hardware blocks
that send messages to devices connected to an I2C bus, such as
when the PMC sends a poweroff message to the PMIC. Add ids
to all I2C controllers in Tegra124.
Signed-off-by: Mikko
with this. Note that there are no compile time dependencies
between the two series; it's just that this series is no-op without the
soctherm driver being present.
Mikko Perttunen (5):
of: Add descriptions of thermtrip properties to Tegra PMC bindings
of: Add nvidia,controller-id property to Tegra I2C
From: Mikko Perttunen mperttu...@nvidia.com
Sometimes, hardware blocks want to issue requests to devices
connected to I2C buses by itself. In such case, the bus the
target device resides on must be configured into a register.
For this purpose, each I2C controller has a defined ID known
From: Mikko Perttunen mperttu...@nvidia.com
This adds a device tree controlled option to enable PMC-based
thermal reset in overheating situations. Thermtrip is supported on
Tegra30, Tegra114 and Tegra124. The thermal reset only works when
the thermal sensors are calibrated, so a soctherm driver
On 11/11/2014 08:37 AM, Alexandre Courbot wrote:
On 11/10/2014 10:12 PM, Mikko Perttunen wrote:
From: Mikko Perttunen mperttu...@nvidia.com
Hardware-triggered thermal reset requires configuring the I2C
reset procedure. This configuration is read from the device tree,
so document the relevant
On 11/12/2014 02:29 PM, Thierry Reding wrote:
On Wed, Nov 12, 2014 at 02:07:51PM +0200, Mikko Perttunen wrote:
On 11/11/2014 08:37 AM, Alexandre Courbot wrote:
On 11/10/2014 10:12 PM, Mikko Perttunen wrote:
From: Mikko Perttunen mperttu...@nvidia.com
Hardware-triggered thermal reset requires
On 11/12/2014 05:45 PM, Thierry Reding wrote:
On Wed, Nov 12, 2014 at 08:56:33AM +0100, Tomeu Vizoso wrote:
[...]
diff --git a/drivers/memory/tegra/tegra124-emc.c
b/drivers/memory/tegra/tegra124-emc.c
[...]
+static int t124_emc_burst_regs[] = {
The t124 prefix seems rather redundant in a
Tested-by: Mikko Perttunen mikko.perttu...@kapsi.fi
One potential issue I can see is that if the cpufreq driver fails to
probe then you'll never get the thermal driver either. For example,
Tegra124 currently has no cpufreq driver, so if CONFIG_CPU_THERMAL was
enabled, then the soctherm driver
From: Mikko Perttunen mperttu...@nvidia.com
This adds a device tree controlled option to enable PMC-based
thermal reset in overheating situations. Thermtrip is supported on
Tegra30, Tegra114 and Tegra124. The thermal reset only works when
the thermal sensors are calibrated, so a soctherm driver
From: Mikko Perttunen mperttu...@nvidia.com
This adds the required information to reset the board during an overheating
situation to the Jetson TK1 device tree. The thermal reset is handled by the
PMC by sending an I2C message to the PMIC. The entries specify the I2C
message to be sent.
Signed
From: Mikko Perttunen mperttu...@nvidia.com
Hardware-triggered thermal reset requires configuring the I2C
reset procedure. This configuration is read from the device tree,
so document the relevant properties in the binding documentation.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
integer field instead of phandle for thermtrip i2c controller id
- Rearrange pmc.c using a forward declaration to prevent huge patch
Mikko Perttunen (3):
of: Add descriptions of thermtrip properties to Tegra PMC bindings
ARM: tegra: Add PMC thermtrip programming to Jetson TK1 device tree
ARM
On 09/24/2014 09:32 PM, Eduardo Valentin wrote:
Hello Mikko,
On Thu, Aug 21, 2014 at 01:17:21PM +0300, Mikko Perttunen wrote:
This adds critical trip points to the Jetson TK1 device tree.
The device will do a controlled shutdown when either the CPU, GPU
or MEM thermal zone reaches 101 degrees
On 09/24/2014 09:41 PM, Eduardo Valentin wrote:
On Wed, Sep 24, 2014 at 09:34:16PM +0300, Mikko Perttunen wrote:
On 09/24/2014 09:32 PM, Eduardo Valentin wrote:
Hello Mikko,
On Thu, Aug 21, 2014 at 01:17:21PM +0300, Mikko Perttunen wrote:
This adds critical trip points to the Jetson TK1
On 09/24/2014 09:48 PM, Eduardo Valentin wrote:
Hello Mikko,
On Wed, Sep 24, 2014 at 09:43:55PM +0300, Mikko Perttunen wrote:
On 09/24/2014 09:41 PM, Eduardo Valentin wrote:
On Wed, Sep 24, 2014 at 09:34:16PM +0300, Mikko Perttunen wrote:
On 09/24/2014 09:32 PM, Eduardo Valentin wrote
On 09/24/2014 10:18 PM, Eduardo Valentin wrote:
Mikko,
On Thu, Aug 21, 2014 at 01:17:22PM +0300, Mikko Perttunen wrote:
...
+
+static int enable_tsensor(struct tegra_soctherm *tegra,
+ const struct tegra_tsensor *sensor,
+ struct
On 09/25/2014 08:59 AM, Thierry Reding wrote:
On Wed, Sep 24, 2014 at 10:32:13PM +0300, Mikko Perttunen wrote:
On 09/24/2014 10:18 PM, Eduardo Valentin wrote:
Mikko,
On Thu, Aug 21, 2014 at 01:17:22PM +0300, Mikko Perttunen wrote:
...
+
+static int enable_tsensor(struct tegra_soctherm
To better facilitate discussion, here's an outline of how the driver works:
emc_set_rate (CAR) gets called
The current timing (= rate,parent pair) is checked along with the
target timing.
If the target timing has the same clock source (~parent, see
emc_parent_clk_sources in the clk
On 11/07/2014 05:54 PM, Eduardo Valentin wrote:
Terve Mikko,
On Wed, Oct 15, 2014 at 01:05:19PM +0300, Mikko Perttunen wrote:
Eduardo: ping
I had no objections with the driver at this point. Neither with the DT
part. I decided to include it in my -linus queue, which means
On 11/17/2014 01:43 PM, Thierry Reding wrote:
On Fri, Nov 14, 2014 at 12:47:33PM +0200, Mikko Perttunen wrote:
Tested-by: Mikko Perttunen mikko.perttu...@kapsi.fi
One potential issue I can see is that if the cpufreq driver fails to probe
then you'll never get the thermal driver either
On 11/17/2014 03:08 PM, Thierry Reding wrote:
On Mon, Nov 17, 2014 at 02:51:24PM +0200, Mikko Perttunen wrote:
On 11/17/2014 01:43 PM, Thierry Reding wrote:
On Fri, Nov 14, 2014 at 12:47:33PM +0200, Mikko Perttunen wrote:
Tested-by: Mikko Perttunen mikko.perttu...@kapsi.fi
One potential
On 11/18/2014 12:44 AM, Eduardo Valentin wrote:
Different drivers request API extensions in of-thermal. For this reason,
additional callbacks are required to fit the new drivers needs.
The current API implementation expects the registering sensor driver
to provide a get_temp and get_trend
On 10/10/2014 04:14 PM, Mark Rutland wrote:
On Fri, Oct 10, 2014 at 01:46:55PM +0100, Tomeu Vizoso wrote:
From: Mikko Perttunen mperttu...@nvidia.com
Add binding documentation for the nvidia,tegra124-emc device tree node.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
Signed-off
On 11/06/2014 09:56 AM, Alexandre Courbot wrote:
On 10/30/2014 01:22 AM, Tomeu Vizoso wrote:
From: Mikko Perttunen mperttu...@nvidia.com
Implements functionality needed to change the rate of the memory bus
clock.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
Signed-off-by: Tomeu Vizoso
On 11/06/2014 10:04 AM, Alexandre Courbot wrote:
On 10/30/2014 01:22 AM, Tomeu Vizoso wrote:
From: Mikko Perttunen mperttu...@nvidia.com
The driver is currently only tested on Tegra124 Jetson TK1, but should
work with other Tegra124 boards, provided that correct EMC tables are
provided through
On 02/12/2015 03:54 PM, Peter De Schrijver wrote:
On Thu, Jan 08, 2015 at 03:22:04PM +0200, Mikko Perttunen wrote:
From: Tuomas Tynkkynen ttynkky...@nvidia.com
The DFLL is the main clocksource for the fast CPU cluster on Tegra124
and also provides automatic CPU rail voltage scaling as well
On 02/13/2015 12:42 AM, Thierry Reding wrote:
On Thu, Jan 08, 2015 at 03:22:04PM +0200, Mikko Perttunen wrote:
From: Tuomas Tynkkynen ttynkky...@nvidia.com
The DFLL is the main clocksource for the fast CPU cluster on Tegra124
and also provides automatic CPU rail voltage scaling as well
On 02/12/2015 04:19 PM, Peter De Schrijver wrote:
On Thu, Jan 08, 2015 at 03:22:08PM +0200, Mikko Perttunen wrote:
From: Paul Walmsley pwalms...@nvidia.com
The DVCO present in the DFLL IP block has a separate reset line,
exposed via the CAR IP block. This reset line is asserted upon SoC
reset
On 02/09/2015 11:34 PM, Eduardo Valentin wrote:
This change introduces a section in the Introduction Chapter to
list concepts used by the Thermal Framework.
Signed-off-by: Eduardo Valentin edubez...@gmail.com
---
Documentation/DocBook/thermal.tmpl | 129 -
From: Mikko Perttunen mperttu...@nvidia.com
This adds the required information to reset the board during an overheating
situation to the Jetson TK1 device tree. The thermal reset is handled by the
PMC by sending an I2C message to the PMIC. The entries specify the I2C
message to be sent.
Signed
From: Mikko Perttunen mperttu...@nvidia.com
Hardware-triggered thermal reset requires configuring the I2C
reset procedure. This configuration is read from the device tree,
so document the relevant properties in the binding documentation.
Signed-off-by: Mikko Perttunen mperttu...@nvidia.com
From: Mikko Perttunen mperttu...@nvidia.com
This adds a device tree controlled option to enable PMC-based
thermal reset in overheating situations. Thermtrip is supported on
Tegra30, Tegra114 and Tegra124. The thermal reset only works when
the thermal sensors are calibrated, so a soctherm driver
integer field instead of phandle for thermtrip i2c controller id
- Rearrange pmc.c using a forward declaration to prevent huge patch
Mikko Perttunen (3):
of: Add descriptions of thermtrip properties to Tegra PMC bindings
ARM: tegra: Add PMC thermtrip programming to Jetson TK1 device tree
ARM
On 01/06/2015 05:14 PM, Thierry Reding wrote:
On Tue, Jan 06, 2015 at 12:52:58PM +0200, Mikko Perttunen wrote:
From: Mikko Perttunen mperttu...@nvidia.com
This adds a device tree controlled option to enable PMC-based
thermal reset in overheating situations. Thermtrip is supported on
Tegra30
From: Tuomas Tynkkynen ttynkky...@nvidia.com
The cpufreq driver for Tegra124 will be a different one than the old
Tegra20 cpufreq driver (tegra-cpufreq), which does not use the device
tree.
Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu
-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
---
drivers/clk/tegra/clk-tegra124.c | 47
drivers/clk/tegra/clk.h | 3 +++
2 files changed, 50 insertions(+)
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index
in the device tree.
Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
---
.../bindings/clock/nvidia,tegra124-dfll.txt| 69 ++
1 file changed, 69 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock
of the work.
Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
---
drivers/clk/tegra/Makefile | 2 +
drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 165 +
2 files changed, 167 insertions(+)
create
From: Tuomas Tynkkynen ttynkky...@nvidia.com
Add the board-specific properties of the DFLL for the Jetson TK1 board.
On this board, the DFLL will take control of the sd0 regulator on the
on-board AS3722 PMIC.
Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen
From: Tuomas Tynkkynen ttynkky...@nvidia.com
The DFLL clocksource is a separate IP block from the usual
clock-and-reset controller, so it gets its own device tree node.
Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
---
arch/arm
From: Tuomas Tynkkynen ttynkky...@nvidia.com
The Tegra124 cpufreq driver depends on CONFIG_CPUFREQ_DT, so
enable it to get the Tegra driver to build by default.
Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
---
arch/arm/configs
...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
---
drivers/clk/tegra/clk-tegra124.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 623b77f..9354c42 100644
--- a/drivers/clk/tegra/clk
Specify the CPU voltage regulator for the cpufreq driver.
Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
---
arch/arm/boot/dts/tegra124-jetson-tk1.dts | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts
-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
---
drivers/clk/tegra/clk-dfll.c | 666 ++-
1 file changed, 663 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra
From: Tuomas Tynkkynen ttynkky...@nvidia.com
The DFLL clocksource was missing from the list of possible parents for
the fast CPU cluster. Add it to the list.
Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
---
drivers/clk/tegra/clk
...@linaro.org
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
---
drivers/cpufreq/Kconfig.arm| 7 ++
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/tegra124-cpufreq.c | 217 +
3 files changed, 225 insertions(+)
create mode 100644
devices, which rely on this
code.
Signed-off-by: Paul Walmsley pwalms...@nvidia.com
Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
---
drivers/clk/tegra/Makefile |1 +
drivers/clk/tegra/clk-dfll.c | 1090
From: Tuomas Tynkkynen ttynkky...@nvidia.com
The Tegra124 will use a different driver for frequency scaling, so
rename the old driver (which handles only Tegra20) appropriately.
Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
to be calculated
on an per-chip basis.
Add utility functions to parse the Tegra-specific tables and export the
voltage-frequency pairs to the generic OPP framework for other drivers
to use.
Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
From: Tuomas Tynkkynen ttynkky...@nvidia.com
The Tegra124 cpufreq driver relies on certain clocks being present
in the /cpus/cpu@0 node.
Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
---
arch/arm/boot/dts/tegra124.dtsi | 9
this to
the Venice2 should be simple, though do note that it does not have
active cooling.
Thanks,
Tuomas
Mikko Perttunen (1):
ARM: tegra: Add CPU regulator to the Jetson TK1 device tree
Paul Walmsley (1):
clk: tegra: Add DFLL DVCO reset control for Tegra124
Tuomas Tynkkynen (14):
clk: tegra: Add
On 03/02/2015 10:47 AM, Alexandre Courbot wrote:
On Thu, Feb 12, 2015 at 11:06 PM, Tomeu Vizoso
tomeu.viz...@collabora.com wrote:
From: Mikko Perttunen mperttu...@nvidia.com
Add binding documentation for the nvidia,tegra124-emc device tree node.
Signed-off-by: Mikko Perttunen mperttu
On 03/02/2015 10:46 AM, Alexandre Courbot wrote:
On Thu, Feb 12, 2015 at 11:06 PM, Tomeu Vizoso
tomeu.viz...@collabora.com wrote:
From: Mikko Perttunen mperttu...@nvidia.com
Needed for the EMC and MC drivers to know what timings from the DT to use.
Signed-off-by: Mikko Perttunen mperttu
On 03/04/2015 09:11 AM, Tuomas Tynkkynen wrote:
On 03/03/2015 01:33 PM, Mikko Perttunen wrote:
On 03/02/2015 10:49 AM, Paul Bolle wrote:
On Sun, 2015-03-01 at 14:44 +0200, Mikko Perttunen wrote:
[...]
+static struct platform_driver tegra124_cpufreq_platdrv = {
+.driver
rate to zero, hanging the system.
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
---
v8:
- Added
drivers/clk/tegra/clk-tegra-super-gen4.c | 46 ++--
1 file changed, 26 insertions(+), 20 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra-super-gen4.c
b
should not be used, as some functions interpret these as negative error
codes.
Each SoC with these special resets should specify the defined reset control
numbers in a device tree header file.
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
---
v8:
- Added
drivers/clk/tegra/clk.c | 36
.
This series has been tested on the Jetson TK1 (Rev C). Porting this to
the Venice2 should be simple, though do note that it does not have
active cooling.
Thanks,
Tuomas
Mikko Perttunen (3):
clk: tegra: Introduce ability for SoC-specific reset control callbacks
clk: tegra: Initialize PLL_X before
From: Tuomas Tynkkynen ttynkky...@nvidia.com
The cpufreq driver for Tegra124 will be a different one than the old
Tegra20 cpufreq driver (tegra-cpufreq), which does not use the device
tree.
Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu
of the work.
Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
---
v8:
- Removed non-standard dvco reset handlers
drivers/clk/tegra/Makefile | 2 +
drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 163
in the device tree.
Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
Cc: devicet...@vger.kernel.org
---
v8:
- Changed dfll@ - clock@
- Changed compatibility string to nvidia,tegra124-dfll
- Clarified how the vdd-cpu-supply property is used
- Marked
-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
Acked-by: Peter De Schrijver pdeschrij...@nvidia.com
---
drivers/clk/tegra/clk-dfll.c | 666 ++-
1 file changed, 663 insertions(+), 3 deletions(-)
diff --git
[mikko.perttunen: ported to special reset callback]
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
---
v8:
- Changed to use SoC-specific reset system
drivers/clk/tegra/clk-tegra124.c | 68
include/dt-bindings/reset/tegra124-car.h | 11 ++
2 files
...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
Acked-by: Peter De Schrijver pdeschrij...@nvidia.com
---
drivers/clk/tegra/clk-tegra124.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index
devices, which rely on this
code.
Signed-off-by: Paul Walmsley pwalms...@nvidia.com
Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
Acked-by: Peter De Schrijver pdeschrij...@nvidia.com
---
v8:
- Use DVCO reset control instead of non-standard
From: Tuomas Tynkkynen ttynkky...@nvidia.com
The Tegra124 cpufreq driver relies on certain clocks being present
in the /cpus/cpu@0 node.
Signed-off-by: Tuomas Tynkkynen ttynkky...@nvidia.com
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
---
arch/arm/boot/dts/tegra124.dtsi | 9
...@linaro.org
Signed-off-by: Mikko Perttunen mikko.perttu...@kapsi.fi
---
drivers/cpufreq/Kconfig.arm| 7 ++
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/tegra124-cpufreq.c | 217 +
3 files changed, 225 insertions(+)
create mode 100644
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