On Mon, Apr 11, 2016 at 11:31:04AM +0100, Robin Murphy wrote:
> Hi Shawn,
>
> On 11/04/16 03:47, Shawn Guo wrote:
> >The macro sg_dma_len(sg) is commonly used to retrieve length of sg,
> >which could be 'dma_length' or 'length' field, depending on whether
> >NE
.
The patch changes sg_set_page() to use sg_dma_len() for sg length setup
as well, so that NEED_SG_DMA_LENGTH case can be handled.
Signed-off-by: Shawn Guo <shawn...@kernel.org>
---
include/linux/scatterlist.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include
On Wed, Mar 30, 2016 at 02:23:03PM +0200, Lothar Waßmann wrote:
> commit ee36027427c7 ("clk: imx: Add clock support for imx6qp")
> introduced a regression due to a subtle typo in the 'can_root' clock
> definition. The effect is that trying to configure the bitrate of the
> can interfaces fails
On Tue, Mar 01, 2016 at 10:59:54AM -0800, Stephen Boyd wrote:
> This flag is a no-op now. Remove usage of the flag.
>
> Cc: Shawn Guo <shawn...@kernel.org>
> Signed-off-by: Stephen Boyd <sb...@codeaurora.org>
Acked-by: Shawn Guo <shawn...@kernel.org>
> ---
>
On Tue, Mar 01, 2016 at 10:59:49AM -0800, Stephen Boyd wrote:
> This flag is a no-op now. Remove usage of the flag.
>
> Cc: Shawn Guo <shawn...@kernel.org>
> Signed-off-by: Stephen Boyd <sb...@codeaurora.org>
Acked-by: Shawn Guo <shawn...@kernel.org>
> ---
>
- added imx6ul specific compatibles as requested by Lucas Stach
>
> Changes vs. v2:
> - dropped patches which have already been applied in the meantime
> - addressed comments by Shawn Guo
>
>
On Wed, Mar 02, 2016 at 02:11:22PM +0800, Alison Wang wrote:
> According to the current clock driver for Freescale QorIQ platform, new
> clock binding will be used for LS1021A.
Is this a simple clock binding updating/replacing, or does it actually
include some clock assignment changes? I expect
On Thu, Mar 31, 2016 at 11:01:58AM -0700, Tim Harvey wrote:
> On Wed, Mar 30, 2016 at 6:57 PM, Shawn Guo <shawn...@kernel.org> wrote:
> > On Wed, Mar 30, 2016 at 02:09:16PM -0700, Guenter Roeck wrote:
> >> The question was if the property name should be ext-reset-outp
On Wed, Mar 09, 2016 at 06:16:56PM -0800, Stefan Agner wrote:
> Add system suspend and resume support for Vybrid SoC. The standby
> sleep state puts the SoC in STOP mode. The SoC can be woken through
> an interrupt from GPC (Global Power Controller). The GPC can use any
> interrupt as wake-up
;
> >>Any suggestions on whether a vendor specific prefix is necessary?
> >
> >Any comments?
> >
>
> Is this something you can help with, since you are the iMX
> architecture/devicetree maintainer? Appreciate any feedback.
FWIW,
Acked-by: Shawn Guo <shawn...@kernel.o
On Wed, Mar 09, 2016 at 06:16:47PM -0800, Stefan Agner wrote:
> The 2-bit gates found i.MX and Vybrid SoC support different clock
> configuration:
>
> 0b00: clk disabled
> 0b01: clk enabled in RUN mode but disabled in WAIT and STOP mode
> 0b10: clk enabled in RUN, WAIT and STOP mode (only Vybrid)
On Wed, Mar 09, 2016 at 06:16:50PM -0800, Stefan Agner wrote:
> @@ -414,9 +460,12 @@ static void __init vf610_clocks_init(struct device_node
> *ccm_node)
> for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
> clk_prepare_enable(clk[clks_init_on[i]]);
>
> +
On Wed, Mar 09, 2016 at 06:16:51PM -0800, Stefan Agner wrote:
> In order to allow wake support in STOP sleep mode, clocks are
> needed. Use imx_clk_gate2_cgr to disable automatic clock gating
> in low power mode STOP. This allows to enable wake by UART using:
> echo enabled >
On Fri, Mar 11, 2016 at 02:29:30PM +0530, Sanchayan Maity wrote:
> Add OCROM node and introduce phandles to OCROM, MSCM and NVMEM
> OCOTP for use by the Vybrid SoC bus driver.
>
> Signed-off-by: Sanchayan Maity
> ---
> arch/arm/boot/dts/vfxxx.dtsi | 12 +++-
>
On Thu, Apr 21, 2016 at 11:45:20AM +0800, Dong Aisheng wrote:
> On Fri, Jan 29, 2016 at 02:49:23PM -0800, Stefan Agner wrote:
> > If a clock gets enabled early during boot time, it can lead to a PLL
> > startup. The wait_lock function makes sure that the PLL is really
> > stareted up before it
On Mon, Apr 25, 2016 at 06:09:33PM -0700, Joshua Clayton wrote:
> When compiled with "W=1", dtc complains: e.g.
> "Warning (unit_address_vs_reg):
> Node /soc/ipu@0280/port@2/endpoint@0
> has a unit name, but no reg property"
>
> Endpoint nodes don't have a reg property, and the addresses
> in
On Wed, Apr 20, 2016 at 05:38:04PM -0300, Sergio Prado wrote:
> Embest MarS Board [1] is a multi-core platform based on Freescale i.MX6
> Cortex-A9 Dual Core, running up to 1GHz with 1 GB of RAM, 4GB of eMMC
> and with a 4MB SPI flash.
>
> [1] http://www.embest-tech.com/shop/star/marsboard.html
>
On Tue, Apr 26, 2016 at 01:51:13PM +0800, Dong Aisheng wrote:
> Hi Shawn,
>
> On Tue, Apr 26, 2016 at 9:23 AM, Shawn Guo <shawn...@kernel.org> wrote:
> > On Thu, Apr 21, 2016 at 11:45:20AM +0800, Dong Aisheng wrote:
> >> On Fri, Jan 29, 2016 at 02:49:
On Wed, Apr 27, 2016 at 10:57:21AM +0800, Dong Aisheng wrote:
> On Wed, Apr 27, 2016 at 9:58 AM, Shawn Guo <shawn...@kernel.org> wrote:
> > On Tue, Apr 26, 2016 at 07:27:03PM +0800, Dong Aisheng wrote:
> >> Shawn,
> >> What's your suggestion?
> >
> > I
On Tue, Apr 26, 2016 at 07:27:03PM +0800, Dong Aisheng wrote:
> Shawn,
> What's your suggestion?
I think this needs more discussion, and I just dropped Stefan's patch
from my tree.
We need to firstly understand why this is happening. The .prepare hook
is defined to be non-atomic context, and so
On Tue, Apr 26, 2016 at 08:38:22PM -0300, Sergio Prado wrote:
> Embest MarS Board [1] is a multi-core platform based on Freescale i.MX6
> Cortex-A9 Dual Core, running up to 1GHz with 1 GB of RAM, 4GB of eMMC
> and with a 4MB SPI flash.
>
> [1] http://www.embest-tech.com/shop/star/marsboard.html
>
On Tue, Apr 19, 2016 at 04:43:27PM -0500, Stuart Yoder wrote:
> Stuart Yoder (2):
> Documentation: fsl-mc: binding updates for MSIs, ranges, PHYs
> arm64: dts: ls2080a: fsl-mc dt node updates
Applied both, thanks.
On Thu, Apr 28, 2016 at 02:07:03PM -0700, Stefan Agner wrote:
> The clock parent of the AHB root clock when using mux option 1
> is the SYS PLL 270MHz clock. This is specified in Table 5-11
> Clock Root Table of the i.MX 7Dual Applications Processor
> Reference Manual.
>
> While it could be a
On Fri, Apr 29, 2016 at 10:20:49PM +0200, Marcel Ziswiler wrote:
> Add parallel LCD display support for the EDT ET057090DHU 5.7" LCD TFT
> panel.
>
> Signed-off-by: Marcel Ziswiler
Applied, thanks.
On Tue, May 03, 2016 at 06:50:21PM +0800, Dong Aisheng wrote:
> Hi Shawn,
>
> On Tue, May 3, 2016 at 4:32 PM, Shawn Guo <shawn...@kernel.org> wrote:
> > On Thu, Apr 28, 2016 at 02:07:03PM -0700, Stefan Agner wrote:
> >> The clock parent of the AHB root
On Fri, Apr 29, 2016 at 10:19:01AM +0200, Uwe Kleine-König wrote:
> Hello,
>
> $Subject ~= s/imx/imx7/
Updated the subject and applied the patch.
Shawn
On Fri, Apr 29, 2016 at 10:40:18PM +0200, Marcel Ziswiler wrote:
> The GPIO-based bitbanging I2C driver is required to make HDMI work on
> the Apalis iMX6 module plugged into a Ixora carrier board featuring a
> DDC channel to read a screen's EDID being hooked up to regular GPIOs.
>
>
On Fri, Apr 15, 2016 at 06:00:53PM -0700, Stephen Boyd wrote:
> On 01/29, Stefan Agner wrote:
> > If a clock gets enabled early during boot time, it can lead to a PLL
> > startup. The wait_lock function makes sure that the PLL is really
> > stareted up before it gets used. However, the function
On Thu, Apr 14, 2016 at 11:12:06AM -0500, Rob Herring wrote:
> On Wed, Apr 13, 2016 at 06:08:26PM +0800, Yuan Yao wrote:
> > From: Yuan Yao
> >
> > new compatible string: "fsl,ls1043a-qspi".
> >
> > Signed-off-by: Yuan Yao
> > ---
> >
On Sat, Apr 16, 2016 at 10:26:06PM +0200, Arnd Bergmann wrote:
> Building the imx pinctrl driver without regmap fails with multiple
> build errors like:
>
> drivers/pinctrl/freescale/pinctrl-imx.c: In function 'imx_pinctrl_probe':
> drivers/pinctrl/freescale/pinctrl-imx.c:723:9: error: variable
On Wed, Apr 13, 2016 at 08:39:32PM +, Stuart Yoder wrote:
> > > @@ -265,6 +265,93 @@
> > > compatible = "fsl,qoriq-mc";
> > > reg = <0x0008 0x0c00 0 0x40>,/* MC portal
> > > base */
> > > <0x 0x0834 0
On Mon, Apr 18, 2016 at 10:02 AM, Shawn Guo <shawn...@kernel.org> wrote:
> On Wed, Apr 13, 2016 at 08:39:32PM +, Stuart Yoder wrote:
>> > > @@ -265,6 +265,93 @@
>> > > compatible = "fsl,qoriq-mc";
>> > >
On Wed, Apr 13, 2016 at 04:05:23PM -0500, Stuart Yoder wrote:
> updates to the fsl-mc node for full functionality:
>-msi-parent is needed for interrupt support
>-ranges is needed to enable the bus driver to translate bus addresses
>-dpmac nodes provide a basis for relating dpmac
On Mon, Jul 25, 2016 at 11:42:35PM -0700, Stefan Agner wrote:
> Since we have a SoC level node we should make use of it and have
> all nodes which are within the SoC, inside that node. This also
> saves an extra interrupt-parent properties. While at it, also
> order the Coresight nodes according
On Mon, Jul 11, 2016 at 02:18:48PM +0200, Lothar Waßmann wrote:
> The power and reset handling of the FEC ethernet driver is sufficient
> to get the ethernet PHY on the TX28 into a usable state.
> Remove the code that does the PHY initialization on startup.
>
> Signed-off-by: Lothar Waßmann
On Mon, Jul 11, 2016 at 09:08:11PM +0300, Tuomas Tynkkynen wrote:
> The Wandboard Quad comes with a SATA port. Enable the IMX SATA driver by
> default to make it easy to have the root filesystem on it.
>
> Signed-off-by: Tuomas Tynkkynen
Applied both, thanks.
On Thu, Aug 04, 2016 at 12:22:37PM +0200, Fabien Lahoudere wrote:
> In order to use sdma with UART, we need to add DMA configuration in device
> tree.
>
> Signed-off-by: Fabien Lahoudere
Changed subject prefix to 'ARM: dts: imx53: ', and applied patch.
Shawn
On Thu, Aug 04, 2016 at 03:47:32PM +0200, Fabien Lahoudere wrote:
> We have the following messages that tell csi devices are not used:
> imx-ipuv3 1800.ipu: no port@0 node in /soc/ipu@1800, not using CSI0
> imx-ipuv3 1800.ipu: no port@1 node in /soc/ipu@1800, not using CSI1
>
> So
On Mon, Aug 01, 2016 at 10:04:53AM -0400, Lucile Quirion wrote:
> diff --git a/arch/arm/boot/dts/imx6dl-ts4900.dts
> b/arch/arm/boot/dts/imx6dl-ts4900.dts
> new file mode 100644
> index 000..909fd5c
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6dl-ts4900.dts
> +/dts-v1/;
> +#include
On Tue, Jun 28, 2016 at 02:54:44PM +0200, and...@inversepath.com wrote:
> + {
> + pinctrl_esdhc1: esdhc1grp {
> + fsl,pins = <
> + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
> + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
> +
One more comment below.
On Tue, Jun 28, 2016 at 02:54:44PM +0200, and...@inversepath.com wrote:
> + {
> + pinctrl_esdhc1: esdhc1grp {
> + fsl,pins = <
> + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
> + MX53_PAD_SD1_DATA1__ESDHC1_DAT1
use the new
> name instead, as done in commit 26cefdd15db1 for the other occurrence.
>
> Fixes: 26cefdd15db1 ("ARM: dts: imx: replace legacy wakeup property with
> 'wakeup-source'")
> Cc: Sudeep Holla <sudeep.ho...@arm.com>
> Cc: Shawn Guo <shawn...@kernel.org>
On Tue, Jul 05, 2016 at 06:04:09AM +0200, Andreas Färber wrote:
> + {
> + status = "okay";
> + phy-handle = <>;
We generally have 'status' at the bottom of property list.
Shawn
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> +
On Tue, Jul 05, 2016 at 06:04:10AM +0200, Andreas Färber wrote:
> Enable the SDHC node and model the SDIO_PWR GPIO as a regulator.
> Use the SD card as default trigger for the red LED.
>
> Cc: Ettore Chimenti
> Signed-off-by: Andreas Färber
> ---
>
On Tue, Aug 09, 2016 at 11:15:42AM -0400, Lucile Quirion wrote:
> Lucile Quirion (2):
> of: documentation: add bindings documentation for TS-4900
> ARM: dts: TS-4900: add basic device tree
Applied both, thanks.
On Mon, Aug 08, 2016 at 05:00:41PM +0200, Andreas Färber wrote:
> Am 08.08.2016 um 16:12 schrieb Shawn Guo:
> > On Tue, Jul 05, 2016 at 06:04:10AM +0200, Andreas Färber wrote:
> >> Enable the SDHC node and model the SDIO_PWR GPIO as a regulator.
> >> Use the SD card as
On Thu, Aug 11, 2016 at 10:35:16AM -0700, Joshua Clayton wrote:
> Apply hardware workaround for ethernet problem
> See nxp erratum err006687
>
> Signed-off-by: Joshua Clayton
Applied, thanks.
On Thu, Aug 11, 2016 at 08:01:01PM +0200, Fabian Frederick wrote:
> Commit fde57a7c4474
> ("dmaengine: xilinx: Rename driver and config")
>
> renamed config XILINX_VDMA to config XILINX_DMA
> Update defconfig accordingly.
>
> Signed-off-by: Fabian Frederick
I do not see how
On Thu, Aug 11, 2016 at 05:11:06PM -0700, Stefan Agner wrote:
> Only i.MX 7Dual SoC supports CPU frequencies of up to 1GHz. The i.MX
> 7Solo can run with up to 800MHz and does so without making use of DVFS
> usually. While the device tree clearly specified a too fast operating
> point for i.MX
On Tue, Feb 07, 2017 at 11:02:51AM +0800, Baoyou Xie wrote:
> This patch adds zx296718 SoC support for ZTE's i2s controller driver.
>
> Signed-off-by: Baoyou Xie
> ---
> sound/soc/zte/zx-i2s.c | 45 +++--
> 1 file changed, 35
On Tue, Feb 07, 2017 at 11:02:49AM +0800, Baoyou Xie wrote:
> The i2s related clock support is missing from the existing zx296718
> clock driver. This patch adds it, so that the upstream ZX I2S driver
> can work out.
>
> Signed-off-by: Baoyou Xie
> ---
>
On Mon, Feb 06, 2017 at 11:28:20AM +0800, Baoyou Xie wrote:
> + Shawn
>
> On 6 February 2017 at 11:26, Baoyou Xie <baoyou@linaro.org> wrote:
>
> > This patch adds i2c controller driver for ZTE's zx2967 family.
> >
> > Signed-off-by: Baoyou Xie <baoyou.
On Tue, Feb 07, 2017 at 11:02:50AM +0800, Baoyou Xie wrote:
> This patch documents the devicetree for the ZTE's zx296718
> I2S audio controller.
>
> Signed-off-by: Baoyou Xie
> ---
> Documentation/devicetree/bindings/sound/zte,zx-i2s.txt | 6 --
> 1 file changed, 4
Hi Guenter,
On Sat, Feb 04, 2017 at 08:29:27PM -0800, Guenter Roeck wrote:
> Yes. One of the problems is that the patch doesn't apply to my tree
> (which is based on v4.10-rc3), and it doesn't have a common anchestor,
> meaning it is most likely not based on mainline. I would prefer to avoid
>
Hi Baoyou,
On Sun, Feb 05, 2017 at 10:36:38AM +0800, Baoyou Xie wrote:
> On 5 February 2017 at 08:05, Guenter Roeck wrote:
>
> > On 02/03/2017 05:34 PM, Baoyou Xie wrote:
> >
> >> Add the zx2967 watchdog controller driver as maintained by ARM ZTE
> >> architecture
On Wed, Feb 08, 2017 at 06:52:07PM -0600, Rob Herring wrote:
> On Wed, Feb 08, 2017 at 11:02:34AM +0800, Baoyou Xie wrote:
> > ZTE's zx2967 I2S controller driver introduces pclk, this
> > patch documents this fact.
>
> Now we have the same subject for patches 2 and 3.
>
> Personally, I'd prefer
On Thu, Feb 09, 2017 at 11:12:56AM +0800, Baoyou Xie wrote:
> The i2s related clock support is missing from the existing zx296718
> clock driver. This patch adds it, so that the upstream ZX I2S driver
> can work out.
>
> Signed-off-by: Baoyou Xie <baoyou@linaro.org>
o change the clock name from tx to wclk
> to make it clear.
>
> Signed-off-by: Baoyou Xie <baoyou....@linaro.org>
Reviewed-by: Shawn Guo <shawn...@kernel.org>
Hi Eduardo,
On Tue, Feb 07, 2017 at 08:45:39PM -0800, Eduardo Valentin wrote:
>
> On Tue, Feb 07, 2017 at 08:56:40AM +0800, Baoyou Xie wrote:
> > Add the zx2967 thermal drivers as maintained by ARM ZTE
> > architecture maintainers, as they're parts of the core IP.
>
> What kernel version is
On Wed, Feb 08, 2017 at 11:02:35AM +0800, Baoyou Xie wrote:
> The pclk is necessary for zx2967 I2S controller. the driver
> currently doesn't handle it. This is something we need to fix.
>
> In turn, the driver supports zx296718's I2S controller.
>
> By the way, this patch also change the clock
Only a couple of comments below. Otherwise, the patch looks fine to me.
On Thu, Jan 26, 2017 at 09:00:31PM +0800, Baoyou Xie wrote:
> +static int zx2967_i2c_flush_fifos(struct zx2967_i2c_info *zx_i2c)
> +{
> + u32 val;
> + u32 offset;
> +
> + if (zx_i2c->msg_rd) {
> +
On Fri, Jan 20, 2017 at 04:43:47PM +0800, Baoyou Xie wrote:
> +static int zx2967_i2c_probe(struct platform_device *pdev)
> +{
> + struct resource *res;
> + struct zx2967_i2c_info *zx_i2c = NULL;
> + struct clk *clk;
> + void __iomem *reg_base;
> + int ret = 0;
> +
> +
On Thu, Jan 12, 2017 at 06:06:20PM -0500, Vivien Didelot wrote:
> The ZII Dev Rev C board has EEPROMs hanging the 88E6390 Ethernet switch
> chips. Add an "eeprom-length" property to allow access from ethtool.
>
> Signed-off-by: Vivien Didelot
Applied,
On Fri, Jan 20, 2017 at 12:09:33AM +0100, Jagan Teki wrote:
> From: Jagan Teki <ja...@amarulasolutions.com>
>
> Fixed code indent tabs in respetcive imx6qdl dtsi files and
> also add space on imx6qdl-icore-rqs.dtsi on usdhc bus-width nodes.
>
> Cc: Shawn Guo <shawn.
On Tue, Jan 10, 2017 at 02:32:53PM +0100, Sébastien Szymanski wrote:
> OPOS6UL is an i.MX6UL based SoM.
> OPOS6ULDev is a carrier board for the OPOS6UL SoM.
>
> For more details see:
> http://www.opossom.com/english/products-processor_boards-opos6ul.html
>
1: SDHCI controller on 2194000.usdhc [2194000.usdhc] using ADMA
> mmc1: new DDR MMC card at address 0001
> mmcblk1: mmc1:0001 M62704 3.53 GiB
>
> Cc: Matteo Lisi <matteo.l...@engicam.com>
> Cc: Michael Trimarchi <mich...@amarulasolutions.com>
> Cc: Signed-off-by: Shawn
having the
> TRM for all the other SoCs, I've let them alone.
>
> Signed-off-by: Marc Zyngier <marc.zyng...@arm.com>
> ---
> arch/arm/boot/dts/imx6ul.dtsi| 4 ++--
Acked-by: Shawn Guo <shawn...@kernel.org>
On Tue, Jan 10, 2017 at 01:19:05PM +0100, Arnd Bergmann wrote:
> A bugfix added a new local variable that is only used inside of an #ifdef
> section, and unused if CONFIG_PERF_EVENTS is disabled:
>
> arch/arm/mach-imx/mmdc.c:63:25: warning: 'cpuhp_mmdc_state' defined but not
> used
-rqs.dtsi on usdhc bus-width nodes.
>
> Cc: Shawn Guo <shawn...@kernel.org>
> Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
On Wed, Jan 18, 2017 at 11:09:51AM +0100, Sébastien Szymanski wrote:
> GPIO4_11 is on pin 152(MX6DL_PAD_KEY_ROW2) and not on pin
> 151(MX6DL_PAD_KEY_ROW1).
>
> I found the error while booting a mainline kernel on APF6S SoM and
> noticed the following message:
>
> [2.609337] imx6dl-pinctrl
On Mon, Jan 23, 2017 at 01:03:26PM +0800, Baoyou Xie wrote:
> This patch adds i2c controller driver for ZTE's zx2967 family.
>
> Signed-off-by: Baoyou Xie
> ---
> drivers/i2c/busses/Kconfig | 9 +
> drivers/i2c/busses/Makefile | 1 +
>
On Wed, Jan 25, 2017 at 06:25:48AM +0100, linux-kernel-...@beckhoff.com wrote:
> From: Patrick Bruenn
>
> The pinmux configuration in device tree was different from manual
> muxing in /board/freescale/mx53loco/mx53loco.c
> All pins were configured as NO_PAD_CTL(1 << 31),
On Thu, Feb 16, 2017 at 07:05:04PM +0800, Baoyou Xie wrote:
> This patch adds dt-binding documentation for zte's tdm controller.
>
> Signed-off-by: Baoyou Xie <baoyou@linaro.org>
Reviewed-by: Shawn Guo <shawn...@kernel.org>
On Thu, Feb 16, 2017 at 07:05:06PM +0800, Baoyou Xie wrote:
> This patch adds tdm controller driver for zte's SoC family.
>
> Signed-off-by: Baoyou Xie <baoyou@linaro.org>
Reviewed-by: Shawn Guo <shawn...@kernel.org>
On Mon, Feb 13, 2017 at 04:17:31PM +0800, Baoyou Xie wrote:
> This patch adds dt-binding documentation for zte's tdm controller.
>
> Signed-off-by: Baoyou Xie
"bindings doc" instead of "documentation" in patch subject is more
clear.
> ---
>
On Mon, Feb 13, 2017 at 04:17:33PM +0800, Baoyou Xie wrote:
> This patch adds tdm controller driver for zte's SoC family.
>
> Signed-off-by: Baoyou Xie
The patch looks rather pretty to me. I have only a few small comments
below.
> ---
> sound/soc/zte/Kconfig | 8 +
>
On Wed, Feb 15, 2017 at 06:55:08PM +0800, Baoyou Xie wrote:
> This patch adds dt-binding documentation for zte's aud96p22 controller.
>
> Signed-off-by: Baoyou Xie
Suggest to replace "documentation" with "bindings doc" in patch subject.
> ---
>
On Wed, Feb 15, 2017 at 06:55:10PM +0800, Baoyou Xie wrote:
> This patch adds aud96p22 controller driver for zte's SoC family.
>
> Signed-off-by: Baoyou Xie
s/controller/codec in patch subject.
> ---
> sound/soc/codecs/Kconfig | 4 +
> sound/soc/codecs/Makefile
On Mon, Jan 23, 2017 at 04:14:59PM +0100, linux-kernel-...@beckhoff.com wrote:
> From: Patrick Bruenn
>
> The pinmux configuration in device tree is different from manual
> muxing in /board/freescale/mx53loco/mx53loco.c
> It seems the device tree configuration is never
On Tue, Jan 24, 2017 at 03:34:06AM +0530, afzal mohammed wrote:
> Enable EXT4_FS to have rootfs in EXT[2-4].
>
> Other changes are result of savedefconfig keeping minimal config (even
> without enabling EXT4_FS, these would be present).
>
> Signed-off-by: afzal mohammed
On Thu, Feb 09, 2017 at 04:46:45PM +, Mark Brown wrote:
> On Thu, Feb 09, 2017 at 11:12:57AM +0800, Baoyou Xie wrote:
>
> > - - compatible : Must be "zte,zx296702-i2s"
> > + - compatible : Must be one of:
> > + "zte,zx296718-i2s", "zte,zx296702-i2s"
> > + "zte,zx296702-i2s"
>
> You've
On Mon, Jan 16, 2017 at 12:19:53PM +0800, Baoyou Xie wrote:
> This patch adds dt-binding documentation for zx2967 family
> watchdog controller.
>
> Signed-off-by: Baoyou Xie
> ---
> .../bindings/watchdog/zte,zx2967-wdt.txt | 29
> ++
> 1
On Fri, Jan 13, 2017 at 06:46:58PM +0800, Baoyou Xie wrote:
> This patch adds thermal driver for ZTE's zx2967 family.
>
> Signed-off-by: Baoyou Xie <baoyou@linaro.org>
Reviewed-by: Shawn Guo <shawn...@kernel.org>
On Sat, Jan 14, 2017 at 03:05:28PM +0800, Baoyou Xie wrote:
> This patch adds dt-binding documentation for zx2967 family
> reset controller.
>
> Signed-off-by: Baoyou Xie <baoyou@linaro.org>
Reviewed-by: Shawn Guo <shawn...@kernel.org>
On Sat, Jan 14, 2017 at 03:05:30PM +0800, Baoyou Xie wrote:
> +static int zx2967_reset_assert(struct reset_controller_dev *rcdev,
> +unsigned long id)
> +{
> + struct zx2967_reset *reset = NULL;
> + int bank = id / 32;
> + int offset = id % 32;
> + unsigned
On Sat, Jan 14, 2017 at 03:05:30PM +0800, Baoyou Xie wrote:
> This patch adds reset controller driver for ZTE's zx2967 family.
>
> Signed-off-by: Baoyou Xie
> ---
> drivers/reset/Kconfig| 6 ++
> drivers/reset/Makefile | 1 +
>
On Tue, Jan 17, 2017 at 11:22:57AM +0800, Baoyou Xie wrote:
> This patch adds reset controller driver for ZTE's zx2967 family.
>
> Signed-off-by: Baoyou Xie <baoyou@linaro.org>
Reviewed-by: Shawn Guo <shawn...@kernel.org>
On Mon, Jan 16, 2017 at 12:19:55PM +0800, Baoyou Xie wrote:
> This patch adds watchdog controller driver for ZTE's zx2967 family.
>
> Signed-off-by: Baoyou Xie
> ---
> drivers/watchdog/Kconfig | 10 ++
> drivers/watchdog/Makefile | 1 +
>
On Thu, Jan 19, 2017 at 09:59:50AM +0800, Baoyou Xie wrote:
> This patch adds dt-binding documentation for zx2967 family
> watchdog controller.
>
> Signed-off-by: Baoyou Xie
It seems that the comments I put on v1 remains unresolved.
> ---
>
On Thu, Jan 19, 2017 at 09:59:52AM +0800, Baoyou Xie wrote:
> This patch adds watchdog controller driver for ZTE's zx2967 family.
>
> Signed-off-by: Baoyou Xie
> ---
> drivers/watchdog/Kconfig | 10 ++
> drivers/watchdog/Makefile | 1 +
>
brobin...@gmail.com>
Acked-by: Shawn Guo <shawn@linaro.org>
On Mon, Sep 05, 2016 at 06:01:33PM +0800, shh@gmail.com wrote:
> + {
> + status = "okay";
For sake of consistency, please have 'status' at the end of property
list.
Shawn
> + #address-cells = <2>;
> + #size-cells = <1>;
> + /* NAND Flashe and CPLD on board */
> + ranges
On Tue, Sep 06, 2016 at 05:45:34PM +0800, Meng Yi wrote:
> add of_graph dt nodes to describe the panel, and removed
> "fsl,panel" property
>
> Signed-off-by: Meng Yi
Applied, thanks.
On Mon, Sep 05, 2016 at 06:01:31PM +0800, shh@gmail.com wrote:
> + soc {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + clockgen: clocking@1ee1000 {
> +
On Mon, Sep 05, 2016 at 12:11:15PM +0200, and...@inversepath.com wrote:
> Andrej Rosano (2):
> devicetree: Add vendor prefix for Inverse Path
> ARM: dts: imx53: add support for USB armory board
Applied both, thanks.
On Tue, Sep 06, 2016 at 02:53:25PM +0200, Arnd Bergmann wrote:
> The imx6ul soc code gained support for cpuidle, but that causes
> a link failure if CONFIG_SOC_IMX6SX is disabled:
>
> arch/arm/mach-imx/mach-imx6ul.o: In function `imx6ul_init_late':
> mach-imx6ul.c:(.init.text+0xc): undefined
ite MCIMX6G2, 528 MHz
> RAM 128MB, 16-bit DDR3
> NAND SLC 256MB
> Power supply Single 5V
> MAX LCD RES up to WXGA, 1366x768
>
> and more info at
> http://www.engicam.com/prodotti/embedded/som/sodimm/gea-m6ul
>
> Cc: Shawn Guo <shawn...@kernel.org>
On Wed, Aug 31, 2016 at 02:37:21PM +0800, Po Liu wrote:
> NXP some platforms aer interrupt was not MSI/MSI-X/INTx
> but using interrupt line independently. This patch add a "aer"
> interrupt-names for aer interrupt.
> With the interrupt-names "aer", code could probe aer interrupt
> line for pcie
On Wed, Aug 31, 2016 at 12:00:29PM -0500, Zhengyu Shen wrote:
> MMDC is a multi-mode DDR controller that supports DDR3/DDR3L x16/x32/x64
> and LPDDR2 two channel x16/x32 memory types. MMDC is configurable, high
> performance, and optimized. MMDC is present on i.MX6 Quad and i.MX6
> QuadPlus
On Fri, Sep 02, 2016 at 10:34:40AM +0200, Martin Kaiser wrote:
> Signed-off-by: Martin Kaiser
Applied, thanks.
> ---
> arch/arm/mach-imx/hardware.h |2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-imx/hardware.h
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