On Mon, Mar 29 2021 at 09:31, Len Brown wrote:
> On Sat, Mar 27, 2021 at 6:20 PM Thomas Gleixner wrote:
>
>> What's the actual downside of issuing TILERELEASE conditionally
>> depending on prev->AMX INIT=0? Is it slow or what's the real
>> problem here?
>
> TILERELEASE is fast, so there
On Sat, Mar 27, 2021 at 6:20 PM Thomas Gleixner wrote:
> What's the actual downside of issuing TILERELEASE conditionally
> depending on prev->AMX INIT=0? Is it slow or what's the real
> problem here?
TILERELEASE is fast, so there should be no down-side to execute it.
Indeed, checking
Len,
On Sat, Mar 27 2021 at 00:53, Len Brown wrote:
>> 3.3 RECOMMENDATIONS FOR SYSTEM SOFTWARE
>>
>> System software may disable use of Intel AMX by clearing XCR0[18:17],
>> by clearing CR4.OSXSAVE, or by setting
>> IA32_XFD[18]. It is recommended that system software initialize AMX
>> state
> 3.3 RECOMMENDATIONS FOR SYSTEM SOFTWARE
>
> System software may disable use of Intel AMX by clearing XCR0[18:17],
> by clearing CR4.OSXSAVE, or by setting
> IA32_XFD[18]. It is recommended that system software initialize AMX
> state (e.g., by executing TILERELEASE)
> before doing so. This is
On Fri, Mar 26, 2021 at 2:17 PM Borislav Petkov wrote:
>
> On Fri, Mar 26, 2021 at 01:53:47PM -0400, Len Brown wrote:
> > At Dave's suggestion, we had a 64 *KB* sanity check on this path.
> > Boris forced us to remove it, because we could not tell him
> > how we chose the number 64.
>
> The only
Len,
On Fri, Mar 26 2021 at 11:27, Len Brown wrote:
> On Thu, Mar 25, 2021 at 7:10 PM Dave Hansen wrote:
>> From some IRC chats with Thomaas and Andy, I think it's safe to say that
>> they're not comfortable blindly enabling even our "simple features". I
>> think we're going to need at least
On Fri, Mar 26, 2021 at 01:53:47PM -0400, Len Brown wrote:
> At Dave's suggestion, we had a 64 *KB* sanity check on this path.
> Boris forced us to remove it, because we could not tell him
> how we chose the number 64.
The only 64 I can remember is
#define XSTATE_BUFFER_MAX_BYTES
On Fri, Mar 26, 2021 at 10:54 AM Len Brown wrote:
>
> On Fri, Mar 26, 2021 at 11:48 AM Andy Lutomirski wrote:
>
> > > I submit, that after the generic XFD support is in place,
> > > there is exactly 1 bit that needs to be flipped to enable
> > > user applications to benefit from AMX.
> >
> > The
On Fri, Mar 26, 2021 at 11:48 AM Andy Lutomirski wrote:
> > I submit, that after the generic XFD support is in place,
> > there is exactly 1 bit that needs to be flipped to enable
> > user applications to benefit from AMX.
>
> The TILERELEASE opcode itself is rather longer than one bit, and the
On Fri, Mar 26, 2021 at 8:34 AM Len Brown wrote:
>
> On Thu, Mar 25, 2021 at 9:42 PM Andy Lutomirski wrote:
>
> > Regardless of what you call AMX, AMX requires kernel enabling.
>
> I submit, that after the generic XFD support is in place,
> there is exactly 1 bit that needs to be flipped to
On Thu, Mar 25, 2021 at 9:50 PM Thomas Gleixner wrote:
> Please provide the architectural document which guarantees that and does
> so in a way that it can be evaluated by the kernel. Have not seen that,
> so it does not exist at all.
>
> Future CPUID attributes are as useful as the tweet of
On Thu, Mar 25, 2021 at 9:42 PM Andy Lutomirski wrote:
> Regardless of what you call AMX, AMX requires kernel enabling.
I submit, that after the generic XFD support is in place,
there is exactly 1 bit that needs to be flipped to enable
user applications to benefit from AMX.
I submit the patch
On Thu, Mar 25, 2021 at 7:10 PM Dave Hansen wrote:
>
> On 3/25/21 3:59 PM, Len Brown wrote:
> > We call AMX a "simple state feature" -- it actually requires NO KERNEL
> > ENABLING
> > above the generic state save/restore to fully support userspace AMX
> > applications.
> >
> > While not all ISA
Len,
On Thu, Mar 25 2021 at 18:59, Len Brown wrote:
> On Sat, Mar 20, 2021 at 4:57 PM Thomas Gleixner wrote:
>
>> We won't enable features which are unknown ever. Keep that presilicon
>> test gunk where it belongs: In the Intel poison cabinet along with the
>> rest of the code which nobody ever
On Thu, Mar 25, 2021 at 3:59 PM Len Brown wrote:
>
> On Sat, Mar 20, 2021 at 4:57 PM Thomas Gleixner wrote:
>
> > We won't enable features which are unknown ever. Keep that presilicon
> > test gunk where it belongs: In the Intel poison cabinet along with the
> > rest of the code which nobody
On 3/25/21 3:59 PM, Len Brown wrote:
> We call AMX a "simple state feature" -- it actually requires NO KERNEL
> ENABLING
> above the generic state save/restore to fully support userspace AMX
> applications.
>
> While not all ISA extensions can be simple state features, we do expect
> future
On Sat, Mar 20, 2021 at 4:57 PM Thomas Gleixner wrote:
> We won't enable features which are unknown ever. Keep that presilicon
> test gunk where it belongs: In the Intel poison cabinet along with the
> rest of the code which nobody ever want's to see.
I agree, it would be irresponsible to
On Sun, Feb 21 2021 at 10:56, Chang S. Bae wrote:
> "xstate.disable=0x6" will disable AMX on a system that has AMX compiled
> into XFEATURE_MASK_USER_ENABLED.
>
> "xstate.enable=0x6" will enable AMX on a system that does NOT have AMX
> compiled into XFEATURE_MASK_USER_ENABLED (assuming the
On 2/21/21 12:10 PM, Bae, Chang Seok wrote:
> On Feb 21, 2021, at 11:30, Randy Dunlap wrote:
>> Can we tell people (in this Doc file) where to look up the values that can be
>> used in xstate.enable and xstate.disable?
>
> Perhaps add something like this with the change below:
> “See comment
On Feb 21, 2021, at 11:30, Randy Dunlap wrote:
> Can we tell people (in this Doc file) where to look up the values that can be
> used in xstate.enable and xstate.disable?
Perhaps add something like this with the change below:
“See comment before function fpu__init_parse_early_param() in
On 2/21/21 10:56 AM, Chang S. Bae wrote:
> "xstate.disable=0x6" will disable AMX on a system that has AMX compiled
> into XFEATURE_MASK_USER_ENABLED.
>
> "xstate.enable=0x6" will enable AMX on a system that does NOT have AMX
> compiled into XFEATURE_MASK_USER_ENABLED (assuming the kernel
"xstate.disable=0x6" will disable AMX on a system that has AMX compiled
into XFEATURE_MASK_USER_ENABLED.
"xstate.enable=0x6" will enable AMX on a system that does NOT have AMX
compiled into XFEATURE_MASK_USER_ENABLED (assuming the kernel is new enough
to support this feature).
Rename
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