Hi Dinh,
Do you have any idea from last Jaehoon's comment?
On Wed, February 05, 2014, Dinh Nguyen wrote:
From: Dinh Nguyen dingu...@altera.com
This patch will enable the SDMMC_CMD_USE_HOLD_REG bit when the slot is
operating all timing modes, except for SDR50, DDR50, SDR104, and MMC_HS200.
From: Dinh Nguyen dingu...@altera.com
This patch will enable the SDMMC_CMD_USE_HOLD_REG bit when the slot is
operating all timing modes, except for SDR50, DDR50, SDR104, and MMC_HS200.
According to the Synopsys databook :To meet the relatively high Input Hold
Time requirement for SDR12, SDR25,
Hi Dinh,
On 01/10/2014 01:15 AM, Dinh Nguyen wrote:
On Thu, 2014-01-09 at 12:41 +0900, Jaehoon Chung wrote:
Dear, Dinh
On 01/08/2014 11:12 PM, Dinh Nguyen wrote:
On 1/7/14 6:37 PM, Jaehoon Chung wrote:
Hi, Dinh.
Sorry for replying too late.
..[snip]..
+sdr_timing[1] =
On Thu, 2014-01-09 at 12:41 +0900, Jaehoon Chung wrote:
Dear, Dinh
On 01/08/2014 11:12 PM, Dinh Nguyen wrote:
On 1/7/14 6:37 PM, Jaehoon Chung wrote:
Hi, Dinh.
Sorry for replying too late.
..[snip]..
+sdr_timing[1] = ddr_timing[1] = 1;
+of_property_read_u32_array(np,
On 1/7/14 6:37 PM, Jaehoon Chung wrote:
Hi, Dinh.
Sorry for replying too late.
..[snip]..
+sdr_timing[1] = ddr_timing[1] = 1;
+of_property_read_u32_array(np,
+samsung,dw-mshc-sdr-timing, sdr_timing, 2);
+
+of_property_read_u32_array(np,
+
Dear, Dinh
On 01/08/2014 11:12 PM, Dinh Nguyen wrote:
On 1/7/14 6:37 PM, Jaehoon Chung wrote:
Hi, Dinh.
Sorry for replying too late.
..[snip]..
+sdr_timing[1] = ddr_timing[1] = 1;
+of_property_read_u32_array(np,
+samsung,dw-mshc-sdr-timing, sdr_timing, 2);
+
+
On Thu, 2013-12-26 at 11:26 -0600, Dinh Nguyen wrote:
Hi Jaehoon,
On 12/25/13 8:57 PM, Jaehoon Chung wrote:
On 12/17/2013 11:54 PM, zhangfei wrote:
On 12/17/2013 10:03 PM, Dinh Nguyen wrote:
Hi Zhangfei,
On 12/17/13 2:11 AM, zhangfei wrote:
On 12/17/2013 01:01 AM,
Hi, Dinh.
Sorry for replying too late.
..[snip]..
+sdr_timing[1] = ddr_timing[1] = 1;
+of_property_read_u32_array(np,
+samsung,dw-mshc-sdr-timing, sdr_timing, 2);
+
+of_property_read_u32_array(np,
+samsung,dw-mshc-ddr-timing, ddr_timing, 2);
+
+
Hi Jaehoon,
On 12/25/13 8:57 PM, Jaehoon Chung wrote:
On 12/17/2013 11:54 PM, zhangfei wrote:
On 12/17/2013 10:03 PM, Dinh Nguyen wrote:
Hi Zhangfei,
On 12/17/13 2:11 AM, zhangfei wrote:
On 12/17/2013 01:01 AM, dingu...@altera.com wrote:
From: Dinh Nguyen dingu...@altera.com
This patch
On 12/17/2013 11:54 PM, zhangfei wrote:
On 12/17/2013 10:03 PM, Dinh Nguyen wrote:
Hi Zhangfei,
On 12/17/13 2:11 AM, zhangfei wrote:
On 12/17/2013 01:01 AM, dingu...@altera.com wrote:
From: Dinh Nguyen dingu...@altera.com
This patch will enable the SDMMC_CMD_USE_HOLD_REG bit when the
On 12/17/2013 01:01 AM, dingu...@altera.com wrote:
From: Dinh Nguyen dingu...@altera.com
This patch will enable the SDMMC_CMD_USE_HOLD_REG bit when the slot is
operating all timing modes, except for SDR50, DDR50, SDR104, and MMC_HS200.
According to the Synopsys databook :To meet the
On 12/17/2013 10:03 PM, Dinh Nguyen wrote:
Hi Zhangfei,
On 12/17/13 2:11 AM, zhangfei wrote:
On 12/17/2013 01:01 AM, dingu...@altera.com wrote:
From: Dinh Nguyen dingu...@altera.com
This patch will enable the SDMMC_CMD_USE_HOLD_REG bit when the slot is
operating all timing modes, except
From: Dinh Nguyen dingu...@altera.com
This patch will enable the SDMMC_CMD_USE_HOLD_REG bit when the slot is
operating all timing modes, except for SDR50, DDR50, SDR104, and MMC_HS200.
According to the Synopsys databook :To meet the relatively high Input Hold
Time requirement for SDR12, SDR25,
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