This patch helps gettimg m25p80 probed through dt.
To get the id of the exact flash type supported for dt case,
data-type is getting parsed from dt entry.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/mtd/devices/m25p80.c | 22 +-
1 files changed, 21
+ correct device tree mailing list
On Friday 02 August 2013 12:19 PM, Sourav Poddar wrote:
This patch helps gettimg m25p80 probed through dt.
To get the id of the exact flash type supported for dt case,
data-type is getting parsed from dt entry.
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
* Tero Kristo t-kri...@ti.com [130801 08:37]:
On 08/01/2013 06:24 PM, Nishanth Menon wrote:
On 08/01/2013 10:18 AM, Tero Kristo wrote:
On 08/01/2013 05:25 PM, Nishanth Menon wrote:
On 07/31/2013 05:07 AM, Tero Kristo wrote:
On 07/30/2013 09:40 PM, Nishanth Menon wrote:
On 07/23/2013 02:20
* Tero Kristo t-kri...@ti.com [130731 08:17]:
On 07/31/2013 09:35 AM, Tony Lindgren wrote:
* Nishanth Menon n...@ti.com [130730 13:26]:
Tony and a lot of people is not going to like removing support for
non-dt boot for OMAP3 before it's time is due ;)
I think the only showstopper for that
* Stephen Warren swar...@wwwdotorg.org [130731 10:04]:
On 07/31/2013 12:46 AM, Tony Lindgren wrote:
I think we're best off removing the remaining uncompress code
configured port detection features as the port properties are now
defined in kconfig anyways. That simplifies the code quite a
Hi Nishant,
On 08/01/2013 06:06 PM, Nishanth Menon wrote:
On 08/01/2013 09:58 AM, Roger Quadros wrote:
USB_DPLL must be initialized and locked at boot so that
USB modules can work.
Also program USB_DLL_M2 output to half rate.
Signed-off-by: Roger Quadros rog...@ti.com
---
IRQF_DISABLED is a no-op by now and should be
removed.
Signed-off-by: Felipe Balbi ba...@ti.com
---
drivers/net/ethernet/ti/cpsw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 05a1674..22a7a43 100644
---
On Friday 02 August 2013 01:14 PM, Felipe Balbi wrote:
IRQF_DISABLED is a no-op by now and should be
removed.
Signed-off-by: Felipe Balbiba...@ti.com
Acked-by: Mugunthan V N mugunthan...@ti.com
Regards
Mugunthan V N
--
To unsubscribe from this list: send the line unsubscribe linux-omap in
the
On Fri, Aug 02, 2013 at 12:29:25AM -0700, Tony Lindgren wrote:
It seems the best strategy seems to be to just init things later on
so DEBUG_LL is only needed when booting breaks really early on
during the boot process.
... which is exactly the whole point and use case of DEBUG_LL. :)
--
To
On Thu, Aug 01, 2013 at 07:17:13PM +0100, Santosh Shilimkar wrote:
From: Vaibhav Bedia vaibhav.be...@ti.com
The generic code is well equipped to differentiate between
SMP and UP configurations.However, there are some devices which
use Cortex-A9 MP core IP with 1 CPU as configuration. To let
Am 31.07.2013 10:35, schrieb Javier Martinez Canillas:
The problem is that board files and drivers that has not not been completed
migrated to DT assumes (at least for OMAP) that *every* GPIO line is mapped as
an IRQ and they just do:
gpio_request(gpio,...);
gpio_direction_input()
On 08/01/2013 01:30 PM, Sebastian Andrzej Siewior wrote:
On 08/01/2013 12:52 PM, Sebastian Andrzej Siewior wrote:
On 08/01/2013 07:24 AM, George Cherian wrote:
b/arch/arm/boot/dts/am33xx.dtsi
index 38b446b..0f756ca 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++
On 08/02/2013 10:30 AM, Roger Quadros wrote:
Hi Nishant,
On 08/01/2013 06:06 PM, Nishanth Menon wrote:
On 08/01/2013 09:58 AM, Roger Quadros wrote:
USB_DPLL must be initialized and locked at boot so that
USB modules can work.
Also program USB_DLL_M2 output to half rate.
Signed-off-by: Roger
On 8/1/2013 10:35 PM, Mark Rutland wrote:
On Tue, Jul 30, 2013 at 05:21:14PM +0100, Sekhar Nori wrote:
On 7/30/2013 8:25 PM, Mark Rutland wrote:
On Tue, Jul 30, 2013 at 06:05:52AM +0100, Gururaja Hebbar wrote:
Hi,
On 7/3/2013 2:17 PM, Hebbar Gururaja wrote:
Since AM33xx RTC IP has
On Fri, Aug 02, 2013 at 12:07:36PM +0100, Gururaja Hebbar wrote:
On 8/1/2013 10:35 PM, Mark Rutland wrote:
On Tue, Jul 30, 2013 at 05:21:14PM +0100, Sekhar Nori wrote:
On 7/30/2013 8:25 PM, Mark Rutland wrote:
On Tue, Jul 30, 2013 at 06:05:52AM +0100, Gururaja Hebbar wrote:
Hi,
On
On 8/2/2013 4:50 PM, Mark Rutland wrote:
On Fri, Aug 02, 2013 at 12:07:36PM +0100, Gururaja Hebbar wrote:
On 8/1/2013 10:35 PM, Mark Rutland wrote:
On Tue, Jul 30, 2013 at 05:21:14PM +0100, Sekhar Nori wrote:
On 7/30/2013 8:25 PM, Mark Rutland wrote:
On Tue, Jul 30, 2013 at 06:05:52AM +0100,
On 23/07/13 12:06, Tomi Valkeinen wrote:
Hi Tony,
Here's a fix for 3.11 that makes EDID read for DVI work again.
I also included a cleanup patch that removes the non-DT support functions that
are no longer called from anywhere. It's not a fix, but as we're in quite
early
rcs, I thought
On Thursday 01 August 2013 10:00 PM, Richard Zhao wrote:
pass of_phandle_args dma_spec to dma_request_channel in of_dma_simple_xlate,
so the filter function could access of_node in of_phandle_args.
Am just curious the reasoning behind doing so. Can you please expand
above bit more with why you
On Friday 02 August 2013 05:53 AM, Will Deacon wrote:
On Thu, Aug 01, 2013 at 07:17:13PM +0100, Santosh Shilimkar wrote:
From: Vaibhav Bedia vaibhav.be...@ti.com
The generic code is well equipped to differentiate between
SMP and UP configurations.However, there are some devices which
use
On Fri, Aug 02, 2013 at 12:48:07PM +0100, Gururaja Hebbar wrote:
On 8/2/2013 4:50 PM, Mark Rutland wrote:
On Fri, Aug 02, 2013 at 12:07:36PM +0100, Gururaja Hebbar wrote:
On 8/1/2013 10:35 PM, Mark Rutland wrote:
On Tue, Jul 30, 2013 at 05:21:14PM +0100, Sekhar Nori wrote:
On 7/30/2013
* Tomi Valkeinen tomi.valkei...@ti.com [130802 05:05]:
On 23/07/13 12:06, Tomi Valkeinen wrote:
Hi Tony,
Here's a fix for 3.11 that makes EDID read for DVI work again.
I also included a cleanup patch that removes the non-DT support functions
that
are no longer called from
On 02/08/13 15:46, Tony Lindgren wrote:
* Tomi Valkeinen tomi.valkei...@ti.com [130802 05:05]:
On 23/07/13 12:06, Tomi Valkeinen wrote:
Hi Tony,
Here's a fix for 3.11 that makes EDID read for DVI work again.
I also included a cleanup patch that removes the non-DT support functions
that
On 08/02/2013 05:57 AM, Tero Kristo wrote:
On 08/02/2013 10:30 AM, Roger Quadros wrote:
Hi Nishant,
On 08/01/2013 06:06 PM, Nishanth Menon wrote:
On 08/01/2013 09:58 AM, Roger Quadros wrote:
USB_DPLL must be initialized and locked at boot so that
USB modules can work.
Also program
On 07/23/2013 04:06 AM, Tomi Valkeinen wrote:
Panda's DVI connector's DDC pins are connected to OMAP's third i2c bus.
With non-DT, the bus number was 3, and that is what is used in the
dss-common.c which contains the platform data for Panda's DVI.
However, with DT, the bus number is 2. As we
On 07/23/2013 04:06 AM, Tomi Valkeinen wrote:
This is no longer needed as omap4 is now booted using device tree.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
arch/arm/mach-omap2/dss-common.c | 47
arch/arm/mach-omap2/dss-common.h | 2 --
On 02/08/13 15:54, Nishanth Menon wrote:
On 07/23/2013 04:06 AM, Tomi Valkeinen wrote:
Panda's DVI connector's DDC pins are connected to OMAP's third i2c bus.
With non-DT, the bus number was 3, and that is what is used in the
dss-common.c which contains the platform data for Panda's DVI.
On 02/08/13 15:56, Nishanth Menon wrote:
On 07/23/2013 04:06 AM, Tomi Valkeinen wrote:
This is no longer needed as omap4 is now booted using device tree.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
snip
diff --git a/arch/arm/mach-omap2/dss-common.h
On 8/2/2013 1:58 AM, Joel Fernandes wrote:
On 08/01/2013 01:13 AM, Sekhar Nori wrote:
On Thursday 01 August 2013 07:57 AM, Joel Fernandes wrote:
On 07/31/2013 04:18 AM, Sekhar Nori wrote:
On Wednesday 31 July 2013 10:19 AM, Joel Fernandes wrote:
Hi Sekhar,
On 07/30/2013 02:05 AM, Sekhar
On 08/02/2013 08:00 AM, Tomi Valkeinen wrote:
On 02/08/13 15:54, Nishanth Menon wrote:
On 07/23/2013 04:06 AM, Tomi Valkeinen wrote:
Panda's DVI connector's DDC pins are connected to OMAP's third i2c bus.
With non-DT, the bus number was 3, and that is what is used in the
dss-common.c which
On 08/02/2013 08:04 AM, Tomi Valkeinen wrote:
On 02/08/13 15:56, Nishanth Menon wrote:
On 07/23/2013 04:06 AM, Tomi Valkeinen wrote:
This is no longer needed as omap4 is now booted using device tree.
Signed-off-by: Tomi Valkeinen tomi.valkei...@ti.com
---
snip
diff --git
Hi,
AM43x PRCM support (excluding clock tree) is being added with this
series. AM43x reuses most of the IP's from AM335x, as that is the
case, much of the AM335x hwmod data is reused.
I am aware that this series adds around +1K lines to platform. We in
TI, here are making efforts to clean
AM335x AM43x have most of the interconnects, IPs similar. Instead of
adding new hwmod data for AM43x, reuse AM335x hwmod data as much as
possible.
In the hwmod entries that could be reused on AM43x, major changes are
in register offsets and different ocpif clock for most of peripherals
that
Hwmod common to AM43x AM335x has some of fields different (CLKCTRL,
RSTCTRL, RSTST, ocpif clk and clockdomain). It is now updated based
on SoC detection at run time, hence remove statically initialized
entries.
Signed-off-by: Afzal Mohammed af...@ti.com
---
Update AM335x CLKCTRL, RSTCTRL, RSTST offsets, clockdomain ocpif clk
that differ with AM43x at runtime. This is being done so that static
initialization of these details (which are different between AM335x
and AM43x) can be removed to aid in sharing of hwmod data between both
platforms as much as
From: Vaibhav Bedia vaibhav.be...@ti.com
65aa94b ARM: OMAP4: clockdomain/CM code: Update supported transition modes
removed SW_SLEEP mode for clockdomains on OMAP4 class of devices. Not
having SW_SLEEP mode works fine for OMAP4/5 devices but it gets in the
way of reuse for other devices like
Add AM43x CMINST, CDOFFS, RM_RSTST RM_RSTCTRL definitions - minimal
ones that would be used.
Signed-off-by: Afzal Mohammed af...@ti.com
---
arch/arm/mach-omap2/prcm43xx.h | 141
1 file changed, 141 insertions(+)
create mode 100644
From: Ankur Kishore a-kish...@ti.com
Most of the AM43x CM reg address offsets are with MSB bit '1' (on
16-bit value) leading to arithmetic miscalculations while calculating
CLOCK ENABLE register's address because cm_inst field was a type of
const s16, so make it const u16.
Also modify relevant
Update AM43x CLKCTRL, RSTCTRL, RSTST offsets, clockdomain ocpif clk
that differ with AM335x at runtime. This helps in reusing much of the
AM335x hwmod data's for AM43x.
Signed-off-by: Afzal Mohammed af...@ti.com
---
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 110
Reuse OMAP4 operations on AM43x.
Signed-off-by: Ambresh K ambr...@ti.com
Signed-off-by: Afzal Mohammed af...@ti.com
---
arch/arm/mach-omap2/omap_hwmod.c |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index
From: Ambresh K ambr...@ti.com
Add the data file to describe clock domains in AM43x SoC.
OMAP4 clockdomain operations is being reused here.
Signed-off-by: Ambresh K ambr...@ti.com
Signed-off-by: Afzal Mohammed af...@ti.com
---
arch/arm/mach-omap2/clockdomain.h |2 +
From: Ambresh K ambr...@ti.com
Add the data file to describe all power domains in AM43x SoC.
OMAP4 powerdomain operations is being reused here.
Signed-off-by: Ambresh K ambr...@ti.com
Signed-off-by: Afzal Mohammed af...@ti.com
---
arch/arm/mach-omap2/powerdomain.h |1 +
Add hwmod support for IP's that are present in AM43x, but not in
AM335x. AM43x additional ones added here are,
1. synctimer
2. timer8-11
3. ehrpwm3-5
4. spi2-4
5. gpio4-5
Also AM43x pruss interconnect is different asc compared to AM335x.
Update hwmod with the above details and register 'ocpif'
From: Ambresh K ambr...@ti.com
Initialise AM43x HWMOD, powerdomains and clockdomains.
Signed-off-by: Ambresh K ambr...@ti.com
Signed-off-by: Afzal Mohammed af...@ti.com
---
arch/arm/mach-omap2/io.c |6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-omap2/io.c
Build AM43x power domain, clock domain and hwmod data.
Many of AM43x IP's and interconnects are similar as that in AM335x,
hence AM335x hwmod data is being reused with necessary changes.
Earlier the plan was to reuse AM335x specific PRCM code, but as AM43x
PRCM is much similar to OMAP4/5, AM335x
Populate uarts, timers, rtc, wdt, gpio, i2c, spi, cpsw pwm nodes.
Reason for adding these nodes early - hwmod code required address
space of peripherals corresponding to these nodes (as address space
details are removed from hwmod database).
uart0, timers - 1 2 and synctimer were already
Update AM4372 cpu node to the latest cpus/cpu bindings for ARM.
Signed-off-by: Afzal Mohammed af...@ti.com
---
arch/arm/boot/dts/am4372.dtsi |4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index ddc1df7..4635e7f 100644
---
On an AM43x only config, currently default ARCH_NR_GPIO would be zero.
Default it to that supported by the SoC.
Signed-off-by: Afzal Mohammed af...@ti.com
---
arch/arm/Kconfig |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 37c0f4e..c5356c5 100644
On Wed, 2013-07-24 at 17:48 +, Gupta, Pekon wrote:
Hi Olof,
fb1585bc13b (mtd: nand: omap2: clean-up BCHx_HW and BCHx_SW ECC
configurations in device_probe) introduced a warning when the new option
is disabled, i.e. with omap2plus_defconfig:
drivers/mtd/nand/omap2.c:1075:13:
VPE:
VPE(Video Processing Engine) is an IP found on DRA7xx, and in some past TI
multimedia SoCs which don't have baseport support in the mainline kernel.
VPE is a memory to memory block used for performing de-interlacing, scaling and
color conversion on input buffers. It's primarily used to
Add support for the de-interlacer block in VPE.
For de-interlacer to work, we need to enable 2 more sets of VPE input ports
which fetch data from the 'last' and 'last to last' fields of the interlaced
video. Apart from that, we need to enable the Motion vector output and input
ports, and also
Create functions which the VPE driver can use to create a VPDMA descriptor and
add it to a VPDMA descriptor list. These functions take a pointer to an existing
list, and append the configuration/data/control descriptor header to the list.
In the case of configuration descriptors, the creation of
The primary function of VPDMA is to move data between external memory and
internal processing modules(in our case, VPE) that source or sink data. VPDMA is
capable of buffering this data and then delivering the data as demanded to the
modules as programmed. The modules that source or sink data are
Add a DT node for VPE in dra7.dtsi. This is experimental because we might need
to split the VPE address space a bit more, and also because the IRQ line
described is accessible the IRQ crossbar driver is added for DRA7XX.
Cc: Rajendra Nayak rna...@ti.com
Cc: Sricharan R r.sricha...@ti.com
Add hwmod data for the VPE IP, this is needed for the IP to be reset during
boot, and control the functional clock when the driver needs it via
pm_runtime apis. Add the corresponding ocp_if struct and add it DRA7XX's
ocp interface list.
Cc: Rajendra Nayak rna...@ti.com
Cc: Sricharan R
On Fri, Aug 02, 2013 at 12:19:30PM +0530, Sourav Poddar wrote:
This patch helps gettimg m25p80 probed through dt.
without this patch, we also can get the right SPI NOR type from the
dt entry.
Could you explain why we should get the m25p80 probed though the DT?
or give an example.
thanks
Huang
On Thu, Aug 01, 2013 at 02:17:13PM -0400, Santosh Shilimkar wrote:
From: Vaibhav Bedia vaibhav.be...@ti.com
The generic code is well equipped to differentiate between
SMP and UP configurations.However, there are some devices which
use Cortex-A9 MP core IP with 1 CPU as configuration. To let
On 02/08/13 16:30, Nishanth Menon wrote:
On 08/02/2013 08:00 AM, Tomi Valkeinen wrote:
Feel free to help me develop the DT support for DSS =). When that's
done, we can remove all this code.
suggesting here - but it will be nice we have some steps towards this
direction - is there anything
More comments...
On 08/02/2013 04:03 PM, Archit Taneja wrote:
Add support for the de-interlacer block in VPE.
For de-interlacer to work, we need to enable 2 more sets of VPE input ports
which fetch data from the 'last' and 'last to last' fields of the interlaced
video. Apart from that, we
On 08/02/2013 09:22 AM, Tomi Valkeinen wrote:
On 02/08/13 16:30, Nishanth Menon wrote:
On 08/02/2013 08:00 AM, Tomi Valkeinen wrote:
Feel free to help me develop the DT support for DSS =). When that's
done, we can remove all this code.
suggesting here - but it will be nice we have some
Hi Archit,
I've got a few comments:
On 08/02/2013 04:03 PM, Archit Taneja wrote:
VPE is a block which consists of a single memory to memory path which can
perform chrominance up/down sampling, de-interlacing, scaling, and color space
conversion of raster or tiled YUV420 coplanar, YUV422
On 01/08/13 19:17, Santosh Shilimkar wrote:
From: Vaibhav Bedia vaibhav.be...@ti.com
The generic code is well equipped to differentiate between
SMP and UP configurations.However, there are some devices which
use Cortex-A9 MP core IP with 1 CPU as configuration. To let
these SOCs to co-exist
On 8/2/2013 3:59 PM, Sebastian Andrzej Siewior wrote:
On 08/01/2013 01:30 PM, Sebastian Andrzej Siewior wrote:
On 08/01/2013 12:52 PM, Sebastian Andrzej Siewior wrote:
On 08/01/2013 07:24 AM, George Cherian wrote:
b/arch/arm/boot/dts/am33xx.dtsi
index 38b446b..0f756ca 100644
---
Hi Hans,
Thanks for the comments. Some replies below.
On Friday 02 August 2013 08:06 PM, Hans Verkuil wrote:
Hi Archit,
I've got a few comments:
On 08/02/2013 04:03 PM, Archit Taneja wrote:
VPE is a block which consists of a single memory to memory path which can
perform chrominance up/down
On 8/1/2013 8:28 PM, Roger Quadros wrote:
Add nodes for the Super Speed USB controllers, omap-control-usb,
USB2 PHY and USB3 PHY devices.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 136 +++
1 files changed, 136
On 8/1/2013 8:28 PM, Roger Quadros wrote:
Add USB drv_vbus pinctrl information and USB mode
for the USB controller.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts | 22 ++
1 files changed, 22 insertions(+), 0 deletions(-)
diff --git
Hi Huang,
On Saturday 03 August 2013 07:52 AM, Huang Shijie wrote:
On Fri, Aug 02, 2013 at 12:19:30PM +0530, Sourav Poddar wrote:
This patch helps gettimg m25p80 probed through dt.
without this patch, we also can get the right SPI NOR type from the
dt entry.
Could you explain why we should
On Friday 02 August 2013 10:18 AM, Dave Martin wrote:
On Thu, Aug 01, 2013 at 02:17:13PM -0400, Santosh Shilimkar wrote:
From: Vaibhav Bedia vaibhav.be...@ti.com
The generic code is well equipped to differentiate between
SMP and UP configurations.However, there are some devices which
use
On Friday 02 August 2013 10:45 AM, Sudeep KarkadaNagesha wrote:
On 01/08/13 19:17, Santosh Shilimkar wrote:
From: Vaibhav Bedia vaibhav.be...@ti.com
The generic code is well equipped to differentiate between
SMP and UP configurations.However, there are some devices which
use Cortex-A9 MP
Am 02.08.2013 11:57, schrieb Alexander Holler:
There must have been a bug in the patch too. I've also added that
iinterrupt-parent stuff (with the same flags as used by the driver) and
just have let the driver call
request_threaded_irq(gpio_to_irq(gpio), flags);
without the
On 02/08/13 16:22, Santosh Shilimkar wrote:
On Friday 02 August 2013 10:45 AM, Sudeep KarkadaNagesha wrote:
On 01/08/13 19:17, Santosh Shilimkar wrote:
From: Vaibhav Bedia vaibhav.be...@ti.com
The generic code is well equipped to differentiate between
SMP and UP configurations.However, there
On Fri, Aug 02, 2013 at 04:45:46PM +0100, Sudeep KarkadaNagesha wrote:
On 02/08/13 16:22, Santosh Shilimkar wrote:
+ @ Core indicates it is SMP. Check for Aegis SOC where a single
+ @ Cortex-A9 CPU is present but SMP operations fault.
+ mov r4, #0x4100
+ orr r4, r4,
On Thu, 2013-07-18 at 01:22 +0530, Pekon Gupta wrote:
This patch series add support of BCH16_ECC scheme.
As BCH16_ECC scheme generates 26bytes of ECC syndrome per 512B data,
hence this scheme is usable only for NAND devices having 4K or above
page-size, as their OOB/spare area has enough space
Hi,
This set mainly fixes comments received from Nishanth Menon for v4.
AM43xx + AM35xx clock data was added as new feature, also OMAP3
platforms use either the old style kernel clock data or DT data,
based on boot type.
Testing done:
omap3 beagle : boot, suspend / resume
omap4 panda es: boot,
From: Keerthy j-keer...@ti.com
The patch adds a mux node to choose the parent of apll_pcie_ck node.
Signed-off-by: Keerthy j-keer...@ti.com
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 19 +++
1 file changed, 15 insertions(+), 4
From: Roger Quadros rog...@ti.com
USB_DPLL must be initialized and locked at boot so that
USB modules can work.
Signed-off-by: Roger Quadros rog...@ti.com
Signed-off-by: Tero Kristo t-kri...@ti.com
---
drivers/clk/ti/clk-54xx.c | 18 +-
1 file changed, 17 insertions(+), 1
clk-54xx.c now contains the clock init functionality for omap5, including
DT clock registration and adding of static clkdev entries.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/io.c |1 +
drivers/clk/ti/Makefile |2 +-
drivers/clk/ti/clk-54xx.c | 59
The OMAP clock driver now supports DPLL clock type. This patch also
adds support for DT DPLL nodes.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
.../devicetree/bindings/clock/ti/dpll.txt | 70 +++
arch/arm/mach-omap2/clock.h| 144 +-
clk_get_sys / clk_get can now find clocks from device-tree. If a DT clock
is found, an entry is added to the clk_lookup list also for subsequent
searches.
Signed-off-by: Tero Kristo t-kri...@ti.com
Cc: Russell King li...@arm.linux.org.uk
---
drivers/clk/clkdev.c | 33
clk-44xx.c now contains the clock init functionality for omap4, including
DT clock registration and adding of static clkdev entries.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/clock.h |1 -
drivers/clk/ti/clk-44xx.c | 118 +++
Some devices require their clocks to be available with a specific
dev-id con-id mapping. With DT, the clocks can be found by default
only with their name, or alternatively through the device node of
the consumer. With drivers, that don't support DT fully yet, add
mechanism to register specific
TI clk driver now routes some of the basic clocks through own
registration routine to allow autoidle support. This routine just
checks a couple of device node properties and adds autoidle support
if required, and just passes the registration forward to basic clocks.
Signed-off-by: Tero Kristo
This node adds support for a clock node which allows control to the
clockdomain enable / disable.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
.../devicetree/bindings/clock/ti/gate.txt | 41
arch/arm/mach-omap2/clock.h|9 --
From: Keerthy j-keer...@ti.com
This patch changes apll_pcie_m2_ck to fixed factor
clock as there are no configurable divider associated to m2.
Signed-off-by: Keerthy j-keer...@ti.com
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/boot/dts/dra7xx-clocks.dtsi |9 +++--
1 file
This patch creates a unique node for each AM35xx specific clock in the
AM35xx power, reset and clock manager (PRCM). Most of the AM35xx clock
data is shared with OMAP3xxx, this patch only creates the delta.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/boot/dts/am35xx-clocks.dtsi |
clk-7xx.c now contains the clock init functionality for dra7, including
DT clock registration and adding of static clkdev entries.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
drivers/clk/ti/Makefile |3 ++-
drivers/clk/ti/clk-7xx.c | 67 ++
2
AM33xx clocks have now been moved to DT, thus remove the old data file
and use the new init code under OMAP clock driver.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/Makefile |1 -
arch/arm/mach-omap2/cclock33xx_data.c | 1059 -
From: Keerthy j-keer...@ti.com
This patch adds optfclk_pciephy_clk and optfclk_pciephy_div_clk
which are used by PCIe phy. It also adds a mux clock to choose
the source of optfclk_pciephy_div_clk clock.
Signed-off-by: Keerthy j-keer...@ti.com
Signed-off-by: Tero Kristo t-kri...@ti.com
---
Adding set-rate-parent to clock node now allows a node to forward
clk_set_rate request to its parent clock.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
drivers/clk/clk-divider.c |6 +-
drivers/clk/clk-fixed-factor.c |6 +-
drivers/clk/clk-gate.c |8 ++--
OMAP3 platforms support both DT and non-DT boot at the moment, make
the clock init work according to the used setup.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/clock3xxx.h |4
arch/arm/mach-omap2/io.c| 13 -
2 files changed, 16
This patch creates a unique node for each clock in the DRA7 power,
reset and clock manager (PRCM).
TODO: apll_pcie clock node is still a dummy in this version, and
proper support for the APLL should be added.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/boot/dts/dra7xx-clocks.dtsi |
This patch creates a unique node for each clock in the AM43xx power,
reset and clock manager (PRCM).
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/boot/dts/am43xx-clocks.dtsi | 671 ++
1 file changed, 671 insertions(+)
create mode 100644
AM35xx now uses the clock data from device tree. Most of the data is
shared with OMAP3xxx, but as there is some delta, a new base .dtsi
file is also created for the SoC.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/boot/dts/am3517-evm.dts|2 +-
From: Keerthy j-keer...@ti.com
The patch adds support for DRA7 PCIe APLL. The APLL
sources the optional functional clocks for PCIe module.
APLL stands for Analog PLL. This is different when comapred
with DPLL meaning Digital PLL, the phase detection is done
using an analog circuit.
This patch creates a unique node for each clock in the OMAP5 power,
reset and clock manager (PRCM).
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/boot/dts/omap5.dtsi |7 +
arch/arm/boot/dts/omap54xx-clocks.dtsi | 1410
2 files changed,
clk-33xx.c now contains the clock init functionality for am33xx, including
DT clock registration and adding of static clkdev entries.
This patch also moves the omap2_clk_enable_init_clocks declaration to
the driver include, as this is needed by the am33xx clock init code.
Signed-off-by: Tero
clk-3xxx.c now contains the clock init functionality for omap3, including
DT clock registration and adding of static clkdev entries.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/clock3xxx.h |1 -
drivers/clk/ti/Makefile |3 +-
drivers/clk/ti/clk-3xxx.c
OMAP3 has interface clocks in addition to functional clocks, which
require special handling for the autoidle and idle status register
offsets mainly.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
.../devicetree/bindings/clock/ti/interface.txt | 45 +
arch/arm/mach-omap2/clock.h
If the main clock for a hwmod is of basic clock type, it is illegal to type
cast this to clk_hw_omap and will result in bogus data. Fixed by checking
the clock flags before attempting the type cast.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/mach-omap2/omap_hwmod.c |2 ++
1 file
This patch creates a unique node for each clock in the OMAP4 power,
reset and clock manager (PRCM). OMAP443x and OMAP446x have slightly
different clock tree which is taken into account in the data.
Signed-off-by: Tero Kristo t-kri...@ti.com
---
arch/arm/boot/dts/omap443x-clocks.dtsi | 17 +
OMAP3630 dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
dpll4_m5_ck dpll4_m6_ck dividers gets loaded with reset
value after their respective PWRDN bits are set. Any dummy write
(Any other value different from the Read value) to the
corresponding CM_CLKSEL register will refresh the dividers.
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