On Tuesday 22 January 2013 11:31 AM, Srinidhi Kasagar wrote:
On Mon, Jan 21, 2013 at 19:22:37 +0100, Tony Lindgren wrote:
* srinidhi kasagar [130121 05:19]:
Forgot to complete the subject and add the description?
No :) It has the subject, but description is intentionally skipped
because subj
On Monday 21 January 2013 01:41 PM, Santosh Shilimkar wrote:
On Friday 18 January 2013 10:45 PM, Tony Lindgren wrote:
Hi,
* Santosh Shilimkar [130118 07:30]:
From: Benoit Cousson
Adding the hwmod data for OMAP54xx platforms.
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
On Monday 21 January 2013 07:47 PM, Daniel Lezcano wrote:
Hi All,
I have a question regarding the behavior of cpuidle on pandaboard.
1. cpuidle is enabled
2. The deep idle states seem to be reach
for i in $(find /sys/devices/system/cpu -name "usage"); do echo "$i :
$(cat $i)"; done
/sys/devi
On Monday 21 January 2013 07:57 PM, Sebastien Guiriec wrote:
Hi Santosh,
I check the tree with Audio and it is working. Just a comment for the
addition of ABE DPLL locking like for OMAP4.
Excellent. Can you send the update please?
I will fold that in.
Regards
santosh
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On Friday 18 January 2013 10:49 PM, Tony Lindgren wrote:
* Santosh Shilimkar [130118 07:30]:
From: Rajendra Nayak
Add the clock tree related data for OMAP54xx platforms.
Cc: Paul Walmsley
Signed-off-by: Rajendra Nayak
Signed-off-by: Benoit Cousson
[santosh.shilim...@ti.com: Generated
On Friday 18 January 2013 10:45 PM, Tony Lindgren wrote:
Hi,
* Santosh Shilimkar [130118 07:30]:
From: Benoit Cousson
Adding the hwmod data for OMAP54xx platforms.
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
+/* bb2d */
+static struct omap_hwmod_irq_info
On Friday 18 January 2013 11:19 PM, Jan Luebbe wrote:
Other devices in the device tree can use omap-gpio as an interrupt
controller with something like:
interrupt-parent = <&gpio1>;
interrupts = <19 8>;
(in this case with #interrupt-cells = <2> in the gpio node to be able
to confi
On Saturday 19 January 2013 08:16 PM, Marc Zyngier wrote:
On Sat, 19 Jan 2013 00:21:22 +0530, Santosh Shilimkar
wrote:
On Friday 18 January 2013 10:38 PM, Marc Zyngier wrote:
On 18/01/13 17:00, Santosh Shilimkar wrote:
On Friday 18 January 2013 09:32 PM, Marc Zyngier wrote:
On 18/01/13 15
On Friday 18 January 2013 10:38 PM, Marc Zyngier wrote:
On 18/01/13 17:00, Santosh Shilimkar wrote:
On Friday 18 January 2013 09:32 PM, Marc Zyngier wrote:
On 18/01/13 15:32, Santosh Shilimkar wrote:
From: Rajendra Nayak
Specify both secure as well as nonsecure PPI IRQ for arch
timer. This
On Friday 18 January 2013 09:32 PM, Marc Zyngier wrote:
On 18/01/13 15:32, Santosh Shilimkar wrote:
From: Rajendra Nayak
Specify both secure as well as nonsecure PPI IRQ for arch
timer. This fixes the following errors seen on DT OMAP5 boot..
[0.00] arch_timer: No interrupt available
From: Rajendra Nayak
Specify both secure as well as nonsecure PPI IRQ for arch
timer. This fixes the following errors seen on DT OMAP5 boot..
[0.00] arch_timer: No interrupt available, giving up
Cc: Benoit Cousson
Signed-off-by: Rajendra Nayak
Signed-off-by: Santosh Shilimkar
On OMAP5 to detect invalid/bad memory accesses, 16MB of DDR is used as a trap.
Hence available memory for linux OS is 2032 MB on boards popullated with 2 GB
memory.
Cc: Benoit Cousson
Signed-off-by: Santosh Shilimkar
---
arch/arm/boot/dts/omap5-evm.dts |2 +-
1 file changed, 1 insertion
Allow prm init to success on OMAP5 SOCs.
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/prm44xx.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index c05a343..1aae198 100644
--- a/arch/arm/mach
OMAP5 clockdata has different sys clock clock node name. Fix the timer code
to take care of it.
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/timer.c |5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
Update OMAP5 ES2 idcode and make ES2 as default detection.
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/id.c | 16 +---
arch/arm/mach-omap2/soc.h |2 ++
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2
)
Rajendra Nayak (1):
ARM: dts: OMAP5: Specify nonsecure PPI IRQ for arch timer
Santosh Shilimkar (4):
ARM: OMAP5: Update SOC id detection code for ES2
ARM: OMAP2+: timer: Update the OMAP5 clocksource name as per clock
data
From: Benoit Cousson
Add the data file to describe all power domains inside the OMAP54XX soc.
Cc: Paul Walmsley
Signed-off-by: Benoit Cousson
[santosh.shilim...@ti.com: Generated es2.0 data]
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/powerdomain.h |1 +
arch/arm
From: Benoit Cousson
Add the data file to describe all clock domains inside the OMAP54XX soc.
Cc: Paul Walmsley
Signed-off-by: Benoit Cousson
[santosh.shilim...@ti.com: Generated es2.0 data]
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/clockdomain.h |1 +
arch/arm
Include the OMAP5 data files in build. Initialise the voltage, power,
clock domains and the clock tree.
Cc: Paul Walmsley
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/Makefile |6 +-
arch/arm/mach-omap2/io.c |9 +
2 files changed, 14 insertions(+), 1
From: Benoit Cousson
Add the PRCM MPU registers for OMAP54XX platforms.
Cc: Paul Walmsley
Signed-off-by: Benoit Cousson
[santosh.shilim...@ti.com: Generated es2.0 data]
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/prcm44xx.h |6 +++
arch/arm/mach-omap2/prcm_mpu54xx.h
Add voltagedomain related data for OMAP54XX SOCs.
Cc: Paul Walmsley
Signed-off-by: Benoit Cousson
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/voltage.h |1 +
arch/arm/mach-omap2/voltagedomains54xx_data.c | 102 +
2 files changed, 103
From: Benoit Cousson
Adding the OMAP5 specific header for SCRM module.
Cc: Paul Walmsley
Signed-off-by: Benoit Cousson
[santosh.shilim...@ti.com: Generated es2.0 data]
Signed-off-by: Santosh Shilimkar
---
arch/arm/mach-omap2/scrm54xx.h | 231
1
AP5: hwmod data: Create initial OMAP5 SOC hwmod data
Rajendra Nayak (1):
ARM: OMAP5: clock data: Add OMAP54XX full clock tree and headers
Santosh Shilimkar (2):
ARM: OMAP5: voltagedomain data: Add OMAP5 voltage domain data
ARM: OMAP5: Enable build and frameowrk initialisations
arch/arm/mach-om
event devices. Leverages these
callbacks to have AM33XX clockevent timer which is
in not in WKUP domain to behave properly across system
suspend.
Signed-off-by: Vaibhav Bedia
Cc: Santosh Shilimkar
Cc: Benoit Cousson
Cc: Paul Walmsley
Cc: Kevin Hilman
Cc: Vaibhav Hiremath
Cc: Jon Hunter
a_lch_count' is zero before 1st call of omap_system_dma_probe.
so it will be failed for omap_dma_reserve_channels, when 1st call.
so, need use 'd->lch_count' instead of 'dma_lch_count' for judging.
Signed-off-by: Chen Gang
Signed-off-by: Santosh Shilimkar
On Friday 11 January 2013 10:33 AM, Chen Gang wrote:
> 于 2013年01月10日 18:48, Santosh Shilimkar 写道:
>> 'omap_dma_reserve_channels' when used is suppose to be from command
>> line. Hence the proposed fix in the review is the right one.
>
>ok, thank you for your
On Thursday 10 January 2013 04:18 PM, Santosh Shilimkar wrote:
On Thursday 10 January 2013 03:59 PM, Chen Gang wrote:
dma_lch_count is zero before 1st call of omap_system_dma_probe.
omap_dma_reserve_channels has value before 1st call of
omap_system_dma_probe
when 1st call of
On Thursday 10 January 2013 03:59 PM, Chen Gang wrote:
dma_lch_count is zero before 1st call of omap_system_dma_probe.
omap_dma_reserve_channels has value before 1st call of omap_system_dma_probe
when 1st call of omap_system_dma_probe
we need set dma_lch_count before use it for ju
wrote:
Add minimal APIs for writing to the IPC and the M3_TXEV registers
in the Control module. These will be used in a subsequent patch which
adds suspend-resume support for AM33XX.
Signed-off-by: Vaibhav Bedia
Cc: Tony Lingren
Cc: Santosh Shilimkar
Cc: Benoit Cousson
Cc: Paul Walmsley
Cc
subsequent patch which
adds suspend-resume support for AM33XX.
Signed-off-by: Vaibhav Bedia
Cc: Tony Lingren
Cc: Santosh Shilimkar
Cc: Benoit Cousson
Cc: Paul Walmsley
Cc: Kevin Hilman
Cc: Vaibhav Hiremath
---
On Control module, we are trying to move driver/module
specific code to respective
Vaibhav,
On Monday 31 December 2012 06:36 PM, Vaibhav Bedia wrote:
Hi,
This is the second version of the patch series for adding suspend-resume
support for AM33XX. Based on the feedback received on the previous patch
series [1] almost all the patches have undergone a bit a rework.
The 1st two
which was done in the previous version
of the AM33XX suspend-resume support.
Signed-off-by: Vaibhav Bedia
Cc: Tony Lingren
Cc: Santosh Shilimkar
Cc: Benoit Cousson
Cc: Paul Walmsley
Cc: Kevin Hilman
---
Unrelated to series. You can post this patch separately.
regards
Santosh
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On Monday 31 December 2012 06:37 PM, Vaibhav Bedia wrote:
Add minimal APIs for writing to the IPC and the M3_TXEV registers
in the Control module. These will be used in a subsequent patch which
adds suspend-resume support for AM33XX.
Signed-off-by: Vaibhav Bedia
Cc: Tony Lingren
Cc: Santosh
as clocksource
and clockevent for AM33XX.
For now a new DT property has been added to allow the timer code
to select the timer with the right property.
It has been pointed out by Santosh Shilimkar and Kevin Hilman
that such a change will result in soc-idle never being achieved
on AM33XX. There
: Vaibhav Bedia
Cc: Santosh Shilimkar
Cc: Benoit Cousson
Cc: Paul Walmsley
Cc: Kevin Hilman
Cc: Vaibhav Hiremath
Cc: Jon Hunter
---
v1->v2:
Get rid of harcoded timer id.
Note: since a platform device is not created for these timer
instances and because there
. To ensure that the OMAP PM code does not
attempt to disable the clock to OCMC RAM as part of the
suspend process add the no_idle_on_suspend flag.
Signed-off-by: Vaibhav Bedia
Cc: Tony Lindgren
Cc: Santosh Shilimkar
Cc: Benoit Cousson
Cc: Paul Walmsley
Cc: Kevin Hilman
Cc: Vaibhav Hiremath
On Monday 31 December 2012 06:37 PM, Vaibhav Bedia wrote:
WKUP-M3 has a reset status bit (RM_WKUP_STST.WKUP_M3_LRST)
Update the hardreset API to ensure that the reset line properly
deasserted.
Signed-off-by: Vaibhav Bedia
Cc: Santosh Shilimkar
Cc: Benoit Cousson
Cc: Paul Walmsley
Cc: Kevin
Vaibhav,
On Monday 31 December 2012 06:37 PM, Vaibhav Bedia wrote:
WKUP-M3 has a reset status bit (RM_WKUP_STST.WKUP_M3_LRST)
Update the WKUP-M3 hwmod data to reflect the same.
Signed-off-by: Vaibhav Bedia
Cc: Santosh Shilimkar
Cc: Benoit Cousson
Cc: Paul Walmsley
Cc: Kevin Hilman
Cc
e 2nd region
has the SYSCONFIG register. This leads to the HWMOD code
accessing the wrong memory address for idle and standby
operations. Fix this by removing the ADDR_TYPE_RT flag from
the 1st memory region in CPGMAC0 hwmod entry.
Signed-off-by: Vaibhav Bedia
Cc: Santosh Shilimkar
Cc: Benoit Cousso
On Monday 31 December 2012 06:37 PM, Vaibhav Bedia wrote:
TPTC0 needs to be idled and put to standby under SW control.
Add the appropriate flags in the TPTC0 hwmod entry.
Can you please expand TPTC0 in chane log.
Signed-off-by: Vaibhav Bedia
Cc: Santosh Shilimkar
Cc: Benoit Cousson
Cc
On Monday 31 December 2012 06:36 PM, Vaibhav Bedia wrote:
OCMC RAM lies in the PER power domain and this memory
support retention.
Signed-off-by: Vaibhav Bedia
Cc: Santosh Shilimkar
Cc: Benoit Cousson
Cc: Paul Walmsley
Cc: Kevin Hilman
Cc: Vaibhav Hiremath
---
Looks fine to me.
Acked-by
On Monday 31 December 2012 06:36 PM, Vaibhav Bedia wrote:
This is necessary to ensure that macros declared here can
be reused from assembly files.
Signed-off-by: Vaibhav Bedia
Cc: Santosh Shilimkar
Cc: Paul Walmsley
Cc: Benoit Cousson
Cc: Kevin Hilman
Cc: Vaibhav Hiremath
---
v1->
On Monday 31 December 2012 06:36 PM, Vaibhav Bedia wrote:
Some of the included header files are not needed so
remove them.
Signed-off-by: Vaibhav Bedia
Cc: Santosh Shilimkar
Cc: Benoit Cousson
Cc: Paul Walmsley
Cc: Kevin Hilman
Cc: Vaibhav Hiremath
---
Acked-by: Santosh Shilimkar
--
To
ibhav Bedia
Cc: Santosh Shilimkar
Cc: Benoit Cousson
Cc: Aneesh V
---
v1->v2:
This is a new patch in the series to enable code reuse
between the EMIF driver and AM33XX PM code
drivers/memory/emif.c |2 +-
drivers/memory/emif.h
the assigned mailbox sub-module.
This patch adds an API in the mailbox code which the MPU
can use to empty the FIFO by issuing a readback command.
Signed-off-by: Vaibhav Bedia
Cc: Santosh Shilimkar
---
Note: This patch which will be slightly reworked once the mailbox
driver changes are finalized
for communication
between MPU and WKUP-M3.
Signed-off-by: Vaibhav Bedia
Cc: Russ Dill
Cc: Santosh Shilimkar
---
v1->v2:
Address the comment on operator usage from Russ Dill
drivers/mailbox/mailbox-omap2.c | 35 ++-
1 files changed, 34 inserti
On Thursday 03 January 2013 12:58 PM, R Sricharan wrote:
Hi,
On Sunday 30 December 2012 02:13 AM, ahema...@gmail.com wrote:
From: ahemaily
The variable dma_lch_count used for comparison
(omap_dma_reserve_channels <= dma_lch_count)
before it initialized to the value from omap_dma_dev_attr :
On Monday 31 December 2012 06:26 PM, Paul Walmsley wrote:
Hi
On Mon, 31 Dec 2012, Santosh Shilimkar wrote:
This is more of question. If the limitation is w.r.t MPU power
state then shouldn't we just prevent the MPU power state rather
than blocking the WFI completely.
Can you please cl
So in the case where CORE stays active, just call
WFI directly from the mach-omap2/pm24xx.c code. This removes some
unnecessary SRAM code.
Signed-off-by: Paul Walmsley
Cc: Richard Woodruff
Cc: Kevin Hilman
---
This sounds correct to me.
Acked-by: Santosh Shilimkar
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Paul,
On Sunday 30 December 2012 11:58 PM, Paul Walmsley wrote:
Apparently, on some OMAPs, the MPU can't be allowed to enter WFI while
certain peripherals are active. It's not clear why, and it's likely
that there is simply some other bug in the driver or integration code.
But since the likelih
to my eyes o.w
Acked-by: Santosh Shilimkar
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On Wednesday 26 December 2012 10:51 AM, Kyungmin Park wrote:
From: Kyungmin Park
As apollon board doesn't used anymore, remove it.
Signed-off-by: Kyungmin Park
---
Acked-by: Santosh Shilimkar
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t;plat/"
include path shortcut.
Signed-off-by: Paul Walmsley
Looks good to my eyes.
Acked-by : Santosh Shilimkar
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On Thursday 20 December 2012 10:52 PM, Paul Walmsley wrote:
On Wed, 19 Dec 2012, Jon Hunter wrote:
My understanding is that for OMAP4 devices, the core power domain may
not be active the same time as the MPU power domain. The Cortex-A9 has
the ability to access some peripherals (such as timer,
On Monday 17 December 2012 01:33 AM, Tony Lindgren wrote:
Hi all,
Finally it can be dropped. Thanks for help everybody.
Looks fine to me with update plat/cpu.h patch. Thanks
to you as well for all those patches.
Acked-by: Santosh Shilimkar
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On Monday 17 December 2012 02:57 PM, Andreas Fenkart wrote:
Please add some changelog here too.
Signed-off-by: Andreas Fenkart
---
Patch seems straight forward thought will be interesting where you found
the need of it.
drivers/gpio/gpio-omap.c |2 ++
1 file changed, 2 insertions(+)
OMAP2+ config will not boot on them.
Also, it is good to have devtmpfs at /dev automount enabled by default.
[1]: http://permalink.gmane.org/gmane.linux.hotplug.devel/17230
Signed-off-by: Javier Martinez Canillas
Acked-by: Santosh Shilimkar
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le L2 cache in the aux control register */
+ mrc p15, 0, r10, c1, c0, 1
+ bic r10, r10, #2
+ mcr p15, 0, r10, c1, c0, 1
An isb will be make it safe.
Otherwise patch looks good to me.
Feel free to add my review-by tag if you need one.
Reviewed-by: Santosh Shilimkar
--
On Sunday 09 December 2012 02:23 AM, Paul Walmsley wrote:
Fix the following sparse warnings in the OMAP3/4 CPUIdle code:
arch/arm/mach-omap2/cpuidle34xx.c:272:1: warning: symbol 'omap3_idle_dev' was
not declared. Should it be static?
arch/arm/mach-omap2/cpuidle34xx.c:274:23: warning: symbol 'om
Olof,
On Friday 30 November 2012 12:48 PM, Olof Johansson wrote:
On Mon, Nov 26, 2012 at 05:06:11PM -0800, Tony Lindgren wrote:
The following changes since commit 9dc57643738f9fbe45c10cc062903d5dfda5bdd9:
Merge branch 'fixes-timer' of github.com:jonhunter/linux into
omap-for-v3.8/timer (20
t declared. Should it be static?
arch/arm/mach-omap2/timer.c:213:12: warning: symbol
'omap_dm_timer_get_errata' was not declared. Should it be static?
Add static to function declaration to fix warnings.
Signed-off-by: Vaibhav Hiremath
Signed-off-by: Jon Hunter
---
Acked-by: Santo
or certain configurations.
Cc: Igor Grinberg
Signed-off-by: Jon Hunter
---
Acked-by: Santosh Shilimkar
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On Wednesday 28 November 2012 09:31 PM, Jon Hunter wrote:
On 11/28/2012 09:55 AM, Santosh Shilimkar wrote:
On Wednesday 28 November 2012 09:17 PM, Jon Hunter wrote:
On 11/28/2012 12:09 AM, Santosh Shilimkar wrote:
On Wednesday 28 November 2012 07:45 AM, Jon Hunter wrote:
In commit fa6d79d
On Wednesday 28 November 2012 09:17 PM, Jon Hunter wrote:
On 11/28/2012 12:09 AM, Santosh Shilimkar wrote:
On Wednesday 28 November 2012 07:45 AM, Jon Hunter wrote:
In commit fa6d79d (ARM: OMAP: Add initialisation for the real-time
counter), the function realtime_counter_init() was added
On Wednesday 28 November 2012 09:17 PM, Jon Hunter wrote:
On 11/28/2012 12:09 AM, Santosh Shilimkar wrote:
On Wednesday 28 November 2012 07:45 AM, Jon Hunter wrote:
In commit fa6d79d (ARM: OMAP: Add initialisation for the real-time
counter), the function realtime_counter_init() was added
On Wednesday 28 November 2012 12:16 PM, Igor Grinberg wrote:
On 11/28/12 08:28, Santosh Shilimkar wrote:
On Wednesday 28 November 2012 07:45 AM, Jon Hunter wrote:
When compiling the kernel with configuration options ...
# CONFIG_ARCH_OMAP2 is not set
# CONFIG_ARCH_OMAP3 is not set
On Wednesday 28 November 2012 07:45 AM, Jon Hunter wrote:
When compiling the kernel with configuration options ...
# CONFIG_ARCH_OMAP2 is not set
# CONFIG_ARCH_OMAP3 is not set
# CONFIG_ARCH_OMAP4 is not set
# CONFIG_SOC_OMAP5 is not set
CONFIG_SOC_AM33XX=y
... the following build w
realtime_counter_init() if CONFIG_SOC_OMAP5 is selected.
Cc: Santosh Shilimkar
Reported-by: Tony Lindgren
Signed-off-by: Jon Hunter
---
The #ifdef was avoided because the real-time counter can be used on
other future SOCs. And the those SOCs just select
SOC_HAS_REALTIME_COUNTER. And that stub was added
e "sync32k" in
the function name "omap4_sync32_timer_init". Therefore, correct this
typo to resolve the above error and warning.
Cc: Igor Grinberg
Reported-by: Tony Lindgren
Signed-off-by: Jon Hunter
---
Acked-by: Santosh Shilimkar
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On Saturday 24 November 2012 09:12 AM, Paul Walmsley wrote:
The OMAP4 MPU subsystem power management code contains several unnecessary
shim functions for powerdomain control; remove them.
Signed-off-by: Paul Walmsley
Cc: Santosh Shilimkar
Cc: Kevin Hilman
---
Most of them are inline
()
function. Remove the #ifdef CONFIG_OMAP_32K_TIMER around the
__omap2_sync32k_clocksource_init() function.
Signed-off-by: Igor Grinberg
Cc: Jon Hunter
Cc: Santosh Shilimkar
Cc: Vaibhav Hiremath
---
nice clean-up Igor. Patch looks good to my eyes.
Feel free to add ,
Acked-by: Santosh
On Wednesday 07 November 2012 05:28 PM, Jon Hunter wrote:
On 11/07/2012 04:14 PM, Santosh Shilimkar wrote:
Looks sensible considering alternative WAs.
Acked-by: Santosh Shilimkar
Thanks. With further thought I think that it would be best to combine
patches #2 and #3. Really the main
Jon,
On Wednesday 07 November 2012 01:01 PM, Jon Hunter wrote:
This series includes several fixes for the OMAP DMTIMER driver. This is
based upon 3.7-rc4 with the two series adding device-tree support for
DMTIMERs [1] and the 32kHz Counter [2]
Tested on OMAP5912 OSK, OMAP2420 H4, OMAP3430 Beagl
er) which was before the
omap_dm_timer_enable_posted() function was introduced. Although this is a
regression from the original code it only impacts performance and so is not
needed for stable.
Signed-off-by: Jon Hunter
---
Acked-by: Santosh Shilimkar
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On Wednesday 07 November 2012 04:11 PM, Jon Hunter wrote:
On 11/07/2012 04:04 PM, Santosh Shilimkar wrote:
On Wednesday 07 November 2012 01:01 PM, Jon Hunter wrote:
For OMAP2+ devices, when using DMTIMERs for system timers
(clock-events and
clock-source) the posted mode configuration of the
sensible considering alternative WAs.
Acked-by: Santosh Shilimkar
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On Wednesday 07 November 2012 01:01 PM, Jon Hunter wrote:
When using a DMTIMER as the clock-source timer, posted mode configuration of
the DMTIMER is used. Posted mode is only benefical when configuring timers as
it allows writes to be posted and does not stall the CPU until the write is
complete
e one comment,
Acked-by: Santosh Shilimkar
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Hi,
On Tuesday 06 November 2012 07:47 PM, Joshua Emele wrote:
The iva coprocessor, available on some omap platforms, shares a voltage domain
with the mpu. If cpufreq is active and the mpu processor is scaled down, the iva
coprocessor should also be scaled. The goal is to make sure we do not ramp
+ Sricharan,
On Tuesday 06 November 2012 06:46 PM, Kevin Hilman wrote:
Hello,
I just noticed that the kernel wakeup from suspend using RTC is broken
after I upgraded u-boot from v2012.04.01 to v2012.10 on my
OMAP4430/Panda and OMAP4460/Panda-ES.
I haven't isolated the cause yet, but am hoping
On Tuesday 06 November 2012 06:29 AM, Bedia, Vaibhav wrote:
Hi Santosh, Kevin
On Tue, Nov 06, 2012 at 03:22:16, Shilimkar, Santosh wrote:
[...]
+
+/*
+ * This a subset of registers defined in drivers/memory/emif.h
+ * Move that to include/linux/?
+ */
I'd probably suggest just moving the reg
On Monday 05 November 2012 11:33 PM, Kevin Hilman wrote:
"Bedia, Vaibhav" writes:
On Sat, Nov 03, 2012 at 18:34:30, Kevin Hilman wrote:
[...]
Doesn't this also mean that you won't get timer wakeups
in idle? Or are you keeping the domain where the clockevent is
on during idle?
The lowest
On Monday 05 November 2012 11:10 PM, Kevin Hilman wrote:
+Santosh (to help with EMIF questions/comments)
On 11/02/2012 12:32 PM, Vaibhav Bedia wrote:
AM335x supports various low power modes as documented
in section 8.1.4.3 of the AM335x TRM which is available
@ http://www.ti.com/litv/pdf/spruh7
On Tuesday 06 November 2012 02:49 AM, Santosh Shilimkar wrote:
On Tuesday 06 November 2012 12:59 AM, Kevin Hilman wrote:
"Bedia, Vaibhav" writes:
On Mon, Nov 05, 2012 at 20:23:11, Shilimkar, Santosh wrote:
[...]
On OMAP the OCMC RAM is always clocked and doesn't need an
On Tuesday 06 November 2012 12:59 AM, Kevin Hilman wrote:
"Bedia, Vaibhav" writes:
On Mon, Nov 05, 2012 at 20:23:11, Shilimkar, Santosh wrote:
[...]
On OMAP the OCMC RAM is always clocked and doesn't need any special
clock enable. CM_L3_2_OCMC_RAM_CLKCTRL module mode field is read only.
Isn
On Sunday 04 November 2012 08:56 PM, Bedia, Vaibhav wrote:
On Sat, Nov 03, 2012 at 21:40:37, Shilimkar, Santosh wrote:
[...]
+#if defined(CONFIG_SOC_AM33XX)
+ else if (soc_is_am33xx()) {
+ list = am33xx_mboxes;
+
+ list[0]->irq = platform_get_irq(pdev, 0);
+
On Sunday 04 November 2012 08:56 PM, Bedia, Vaibhav wrote:
On Sat, Nov 03, 2012 at 21:33:47, Shilimkar, Santosh wrote:
[...]
+static int omap2_mbox_fifo_needs_flush(struct omap_mbox *mbox)
+{
+ struct omap_mbox2_fifo *fifo =
+ &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo
On Sunday 04 November 2012 08:56 PM, Bedia, Vaibhav wrote:
On Sat, Nov 03, 2012 at 21:24:14, Shilimkar, Santosh wrote:
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
Signed-off-by: Vaibhav Bedia
---
arch/arm/boot/dts/am33xx.dtsi | 11 +++
1 files changed, 11 insertion
On Sunday 04 November 2012 08:55 PM, Bedia, Vaibhav wrote:
Hi Santosh,
On Sat, Nov 03, 2012 at 21:22:04, Shilimkar, Santosh wrote:
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
From: Vaibhav Hiremath
The current OMAP timer code registers two timers -
one as clocksource and one as
On Sunday 04 November 2012 08:56 PM, Bedia, Vaibhav wrote:
On Sat, Nov 03, 2012 at 21:24:14, Shilimkar, Santosh wrote:
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
Signed-off-by: Vaibhav Bedia
---
arch/arm/boot/dts/am33xx.dtsi | 11 +++
1 files changed, 11 insertion
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
AM335x supports various low power modes as documented
in section 8.1.4.3 of the AM335x TRM which is available
@ http://www.ti.com/litv/pdf/spruh73f
DeepSleep0 mode offers the lowest power mode with limited
wakeup sources without a system
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
AM33XX has only one usable timer in the WKUP domain.
Currently the timer instance in WKUP domain is used
as the clockevent and the timer in non-WKUP domain
as the clocksource. The timer in WKUP domain can keep
running in suspend from a 32K
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
Get rid of some unnecessary header file inclusions
and also use __ASSEMBLER__ macros to allow the
various register offsets from PM assembly code
which be added in a subsequent patch.
Signed-off-by: Vaibhav Bedia
Ideally you should spli
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
The first entry for CPGMAC0 should be ADDR_MAP_ON_INIT
instead of ADDR_TYPE_RT to ensure the omap hwmod code
maps the memory space at init and writes to the SYSCONFIG
registers.
Signed-off-by: Vaibhav Bedia
---
Sorry again similar quest
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
The hwmod data for OCMCRAM in AM33XX was commented out.
This data is needed by the power management code, hence
uncomment the same and register the OCP interface for it.
Why this data is needed by PM code ?
Regards
Santosh
--
To unsubsc
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
Add the reset status offset for WKUP_M3 in the hwmod data
Signed-off-by: Vaibhav Bedia
---
arch/arm/mach-omap2/omap_hwmod_33xx_data.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hw
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
The power management code for AM33XX is a late_initcall
and the PM features depend on the mailbox for IPC.
In preparation for this, convert the mailbox init to
a device_initcall.
Signed-off-by: Vaibhav Bedia
---
Looks fine
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On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
Mailbox IP on AM33XX, is the same as that present
in OMAP4. The single instance of Mailbox module
contains 8 sub-modules and facilitates communication
between MPU, PRUs and WKUP_M3.
The first mailbox sub-module is assigned for
communicati
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
On AM33XX, the mailbox module between the MPU and the
WKUP-M3 co-processor facilitates a one-way communication.
MPU uses the assigned mailbox sub-module to issue the
interrupt to the WKUP-M3 co-processor which then goes
and reads the the I
On Friday 02 November 2012 06:02 PM, Vaibhav Bedia wrote:
Signed-off-by: Vaibhav Bedia
---
arch/arm/boot/dts/am33xx.dtsi | 11 +++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index bb31bff..e2cbf24 100
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