On Tuesday 26 November 2013 06:40 PM, Mark Brown wrote:
On Tue, Nov 26, 2013 at 01:05:07PM +0530, Sourav Poddar wrote:
Set mmap flag to true to indicate that the qspi controller
supports memory mapped operations.
Please combine some of these patches - adding the mmap support
On Tuesday 26 November 2013 06:49 PM, Mark Brown wrote:
On Tue, Nov 26, 2013 at 06:30:15PM +0530, Sourav Poddar wrote:
I mean to say, do I need to document qspi_base, qspi_ctrlmod
register names
also which I have used in omy dts files.
Yes, you need to document what the valid names
From: Darren Etheridge detheri...@ti.com
AM43xx devices have an extra MUX_MODE for certain pins.
Updating dt include to have MUX_MODE8 which maps to 0x8.
Signed-off-by: Darren Etheridge detheri...@ti.com
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
include/dt-bindings/pinctrl/am43xx.h
Add pwm-cells node for all ecap, ehrpwm in am43x dtsi files.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/am4372.dtsi |9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index
on 3.13-rc1. So, tested pwm part with this temporary patch[2].
[2]: http://www.spinics.net/lists/arm-kernel/msg288215.html
Darren Etheridge (1):
pinctrl: am43xx: dt-bindings: add MUX_MODE8
Sourav Poddar (4):
arm: dts: am4372: Add pwm-cellsproperty for ecap device.
arm: dts: am43x-epos-evm
From: Sourav Poddar Date: Sat, 5 Oct 2013 05:19:46 +0530 sourav.pod...@ti.com
Add pwm backlight support for am43x epos evm.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/am43x-epos-evm.dts | 24
1 files changed, 24 insertions(+), 0 deletions
-evm.
There is a some bug while using regulators through backlight
driver on 3.13-rc1. So, tested pwm part with this patch[3].
[3]: http://www.spinics.net/lists/arm-kernel/msg288215.html
Sourav Poddar (3):
arm: dts: am437x-gp-evm: Enable gpio.
ARM: dts: am43x-gp-evm: Add matrix gpio keys
Add I2C2 dts data.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/am43x-epos-evm.dts | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts
b/arch/arm/boot/dts/am43x-epos-evm.dts
index 5521999..7a504d1
Add SPI dts data.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/am43x-epos-evm.dts | 30 ++
1 files changed, 30 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts
b/arch/arm/boot/dts/am43x-epos-evm.dts
index
Add gpio keys node for am43x gp evm.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/am437x-gp-evm.dts | 21 +
1 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts
b/arch/arm/boot/dts/am437x-gp-evm.dts
Add pwm backlight support for gp evm.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/am437x-gp-evm.dts | 24
1 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts
b/arch/arm/boot/dts/am437x-gp
Enable gpio3, gpio4, it will be used by gpio matrix keys. Also,
can be used by othe peripherals.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/am437x-gp-evm.dts |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/am437x-gp
These add api to configure set up registers which will be used
for memory mapped operations.
These was provided as a pointer in the earlier patch and can be
used by the slave devices to configure the master controller as an
when required according to the usecases.
Signed-off-by: Sourav Poddar
Parse memory map register from device tree.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/spi/spi-ti-qspi.c | 14 +-
1 files changed, 13 insertions(+), 1 deletions(-)
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 776e93d..39aefd7 100644
to configure its set up
register for memory mapped operations.
There was another discussion on some LUT registers for some other
qspi controller in mailing list, these feature can also be used for
that case also.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
include/linux/spi/spi.h |4
the whole flash.
-write to the flash
-read back the flash
- compare the data
Sourav Poddar (17):
spi/spi.h: Add get_buf/put_buf support in spi master..
spi/spi.h: Add configure from slave support.
spi/qspi: parse register by name.
spi/qspi: parse control module register.
spi/qspi: parse memory
for conditional execution of
control module part.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/spi/spi-ti-qspi.c | 17 -
1 files changed, 16 insertions(+), 1 deletions(-)
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 67aa905..776e93d 100644
Modify the qspi driver to parse reg information by name.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/spi/spi-ti-qspi.c |6 +-
1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 033ef8d..67aa905
These add apis that can be used to switch to memory mapped operatons
by configuring control module and qspi registers.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/spi/spi-ti-qspi.c | 28
1 files changed, 28 insertions(+), 0 deletions(-)
diff
that
master address.
These can also be used to turm the master controller clock, as usually
the clocks get turned in spi core. But, in memory mapped case, we will
bypass the spi core and hence needa way out to turn on the controller clock.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
include
These can be used to fill information needed to configure
master controller registers.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/mtd/devices/m25p80.c | 17 +
1 files changed, 17 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/devices/m25p80.c b
Adapt driver to do a memory mapped read.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/mtd/devices/m25p80.c | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index 6a27677..b7ed4be
Adapt qspi driver to use (get_buf/put_buf) pointers added
earlier.
These can be called just before the memcpy operations to get hold
of the memory mapped address and to turn on the controller clocks.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/spi/spi-ti-qspi.c | 17
Set mmap flag to true to indicate that the qspi controller
supports memory mapped operations.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/spi/spi-ti-qspi.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti
Add mem variable in spi_master, which can be used to hold on the
memory mapped address.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
include/linux/spi/spi.h |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index
These update binding information for ti qspi controller.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
Documentation/devicetree/bindings/spi/ti_qspi.txt |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/ti_qspi.txt
b
These add device tree entry for qspi controller driver on dra7.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts | 32
arch/arm/boot/dts/dra7.dtsi| 13 +
2 files changed, 45 insertions(+), 0 deletions
Add mmap flag which can be used to show that the master
controller supports memory mapped operations.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
include/linux/spi/spi.h |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/include/linux/spi/spi.h b/include/linux
These add device tree entry for qspi controller driver on am43x-epos-evm.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/am4372.dtsi| 12
arch/arm/boot/dts/am43x-epos-evm.dts | 28
2 files changed, 40 insertions(+), 0
Idea is to enable memory mapped by default at the end of the probe,
if the control reaches the transfer api, then the operation is
not a memory mapped one. Hence, we switch to Normal mode and at the
end of the transfer function. switch back to memory mapped mode.
Signed-off-by: Sourav Poddar
of the hwmod associated to the McSPI
- ti,pindir-d0-out-d1-in: Select the D0 pin as output and D1 as
Acked-by: Sourav Poddar sourav.pod...@ti.com
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Hi Mugunthan,
On Friday 18 October 2013 07:09 PM, Mugunthan V N wrote:
Adding hwmod data for CPSW and MDIO which is present in DRA7xx SoC
Signed-off-by: Mugunthan V Nmugunthan...@ti.com
change the subject to:
ARM: OMAP2+: hwmod: Add hwmod data for MDIO and CPSW
---
Add hwmod data for qspi for AM437x.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
This was tested on AM437x EPOS EVM with Afzal's v6 of AM43x PRCM
basic support and tero's DT clock series.
arch/arm/mach-omap2/omap_hwmod_43xx_data.c | 34
arch/arm/mach-omap2
On Tuesday 15 October 2013 01:04 AM, Paul Walmsley wrote:
Hi
On Mon, 14 Oct 2013, Sourav Poddar wrote:
Add hwmod data for qspi for AM437x.
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
---
This was tested on AM437x EPOS EVM with Afzal's v6 of AM43x PRCM
basic support and tero's DT clock
Add hwmod data for qspi for AM437x.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
This was tested on AM437x EPOS EVM with Afzal's v6 of AM43x PRCM
basic support and tero's DT clock series.
v1-v2:
Rebase on George Cherian USB hwmod patches.
arch/arm/mach-omap2/omap_hwmod_43xx_data.c
This patch disables devices initially(status = disabled).
Devices will only be probed, if the devices are
present in the board file(status = okay).
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
v1-v2:
change approach to disabling devices in dtsi and
enable it in respective board file
omap5 has all devices enable by default.
Disable thosw not required in omap5 uevm board.
Fix the following:
Added status parameter
Simulataneously, fix some tab formatting.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/omap5-uevm.dts | 38
On Tuesday 24 September 2013 11:14 AM, Sekhar Nori wrote:
On Tuesday 24 September 2013 11:09 AM, Sourav Poddar wrote:
omap5 has all devices enable by default.
Disable thosw not required in omap5 uevm board.
s/thosw/those
Fix the following:
Added status parameter
Simulataneously, fix some tab
Add a compatible string for am43xx.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
Documentation/devicetree/bindings/spi/ti_qspi.txt |2 +-
drivers/spi/spi-ti-qspi.c |1 +
2 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/Documentation
Add a compatible string for am4372.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
v1-v2:
Instead of am43xx, use exact part number.
Documentation/devicetree/bindings/spi/ti_qspi.txt |2 +-
drivers/spi/spi-ti-qspi.c |1 +
2 files changed, 2 insertions(+), 1
Hi Mark,
On Tuesday 20 August 2013 06:55 PM, Sourav Poddar wrote:
The patch add basic support for the quad spi controller.
QSPI is a kind of spi module that allows single,
dual and quad read access to external spi devices. The module
has a memory mapped interface which provide direct interface
.
- All iterations went through without failure.
Test2: Use mtd utilities:
- flash_erase to erase the flash device
- mtd_debug read to read data back.
- mtd_debug write to write to the data flash.
diff between the write and read data shows zero.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
On Tuesday 20 August 2013 06:44 PM, Felipe Balbi wrote:
Hi,
On Tue, Aug 20, 2013 at 06:35:25PM +0530, Sourav Poddar wrote:
+static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t)
+{
+ int ret;
+
+ if (t-tx_buf) {
+ ret = qspi_write_msg(qspi, t
-by: Felipe Balbiba...@ti.com
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
v10-v11:
- Fix a typo
Left 3 warnings(80 characters) for better readibilty of code.
These was posted till now as a two patch series.
Dropping the 2nd patch as of now, will add once the support
for multiple data lines
Hi Felipe,
Hi,
On Sun, Aug 04, 2013 at 02:28:09PM +0530, Sourav Poddar wrote:
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
new file mode 100644
index 000..4328ae2
--- /dev/null
+++ b/drivers/spi/spi-ti-qspi.c
@@ -0,0 +1,591 @@
+/*
+ * TI QSPI driver
On Sunday 04 August 2013 02:28 PM, Sourav Poddar wrote:
The patch add basic support for the quad spi controller.
QSPI is a kind of spi module that allows single,
dual and quad read access to external spi devices. The module
has a memory mapped interface which provide direct interface
once the ongoing discussion in the
community is freezed.
This patch is posted to demonstrate how patch 1 of the series will support
quad read.
[1]: http://comments.gmane.org/gmane.linux.kernel.spi.devel/14047
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/spi/spi-ti-qspi.c | 22
This patch series add support for ti qspi controller.
Adapted this series on top of Mark brown series[1]:
[1]: https://patchwork.kernel.org/patch/2834694/
Sourav Poddar (2):
drivers: spi: Add qspi flash controller
driver: spi: Add quad spi read support
Documentation/devicetree/bindings/spi
.
- All iterations went through without failure.
Test2: Use mtd utilities:
- flash_erase to erase the flash device
- nanddump to read data back.
- nandwrite to write to the data flash.
diff between the write and read data shows zero.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
v8-v9
This patch helps gettimg m25p80 probed through dt.
To get the id of the exact flash type supported for dt case,
data-type is getting parsed from dt entry.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/mtd/devices/m25p80.c | 22 +-
1 files changed, 21
+ correct device tree mailing list
On Friday 02 August 2013 12:19 PM, Sourav Poddar wrote:
This patch helps gettimg m25p80 probed through dt.
To get the id of the exact flash type supported for dt case,
data-type is getting parsed from dt entry.
Signed-off-by: Sourav Poddarsourav.pod...@ti.com
Hi Huang,
On Saturday 03 August 2013 07:52 AM, Huang Shijie wrote:
On Fri, Aug 02, 2013 at 12:19:30PM +0530, Sourav Poddar wrote:
This patch helps gettimg m25p80 probed through dt.
without this patch, we also can get the right SPI NOR type from the
dt entry.
Could you explain why we should
This patch series add support for ti qspi controller.
Adapted this series on top of Mark brown series[1]:
[1]: https://patchwork.kernel.org/patch/2834694/
Sourav Poddar (2):
drivers: spi: Add qspi flash controller
driver: spi: Add quad spi read support
Documentation/devicetree/bindings
once the ongoing discussion in the
community is freezed.
This patch is posted to demonstrate how patch 1 of the series will support
quad read.
[1]: http://comments.gmane.org/gmane.linux.kernel.spi.devel/14047
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/spi/spi-ti-qspi.c | 22
.
- All iterations went through without failure.
Test2: Use mtd utilities:
- flash_erase to erase the flash device
- nanddump to read data back.
- nandwrite to write to the data flash.
diff between the write and read data shows zero.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
I have
suspend.
omap5-uevm:
- Boot tested.
- Tested this series on buses where devices are present.
dra7-evm:
- Boot tested.
- run i2c dump on buses where devices are present.
Tested-by: Sourav Poddar sourav.pod...@ti.com
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HI,
On Wednesday 31 July 2013 01:19 PM, Felipe Balbi wrote:
Hi,
On Wed, Jul 31, 2013 at 11:17:52AM +0530, Sourav Poddar wrote:
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
new file mode 100644
index 000..3d10b69
--- /dev/null
+++ b/drivers/spi/spi-ti-qspi.c
@@ -0,0
On Wednesday 31 July 2013 02:50 PM, Felipe Balbi wrote:
Hi,
On Wed, Jul 31, 2013 at 02:40:51PM +0530, Sourav Poddar wrote:
+#defineQSPI_FRAME_MAX 0xfff
Frame max is 4096, 0x1000, right ?
Yes,
this macro was used initially to fill the register bits, where 4095 =
4096
On Wednesday 31 July 2013 03:18 PM, Felipe Balbi wrote:
Hi,
On Wed, Jul 31, 2013 at 03:10:40PM +0530, Sourav Poddar wrote:
words can be of any length (1, 2 or 4) bytes. So, I think it should be
decremented by 1 only.
this is wrong.
hmm..got the point.
I will pass the count address also
On Thursday 01 August 2013 12:09 AM, Trent Piepho wrote:
On Tue, Jul 30, 2013 at 10:47 PM, Sourav Poddarsourav.pod...@ti.com wrote:
Test details:
-
Tested this on dra7 board.
Test1: Ran mtd_stesstest for 4 iterations.
- All iterations went through without failure.
Test2
Hi Felipe,
On Monday 29 July 2013 06:05 PM, Felipe Balbi wrote:
Hi,
On Mon, Jul 29, 2013 at 04:45:02PM +0530, Sourav Poddar wrote:
+ irq = platform_get_irq(pdev, 0);
+ if (irq 0) {
+ dev_err(pdev-dev, no irq resource?\n);
+ return irq
This patch series add support for ti qspi controller.
Adapted this series on top of Mark brown series[1]:
[1]: https://patchwork.kernel.org/patch/2834694/
And some other cleanups.
Sourav Poddar (2):
drivers: spi: Add qspi flash controller
driver: spi: Add quad spi read support
once the ongoing discussion in the
community is freezed.
This patch is posted to demonstrate how patch 1 of the series will support
quad read.
[1]: http://comments.gmane.org/gmane.linux.kernel.spi.devel/14047
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/spi/spi-ti-qspi.c | 15
.
- All iterations went through without failure.
Test2: Use mtd utilities:
- flash_erase to erase the flash device
- nanddump to read data back.
- nandwrite to write to the data flash.
diff between the write and read data shows zero.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
v6-v7
This patch series add support for ti qspi controller.
Adapted this series on top of Mark brown series[1]:
[1]: https://patchwork.kernel.org/patch/2834694/
And some other cleanups.
Sourav Poddar (2):
drivers: spi: Add qspi flash controller
driver: spi: Add quad spi read support
with the ongoing discussion in the
community.
This patch is posted to demonstrate how patch 1 of the series will support
quad read.
[1]: http://comments.gmane.org/gmane.linux.kernel.spi.devel/14047
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/spi/spi-ti-qspi.c | 16
.
- All iterations went through without failure.
Test2: Use mtd utilities:
- flash_erase to erase the flash device
- nanddump to read data back.
- nandwrite to write to the data flash.
diff between the write and read data shows zero.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
v5-v6
On Monday 29 July 2013 03:02 PM, Felipe Balbi wrote:
On Mon, Jul 29, 2013 at 12:52:30PM +0530, Sourav Poddar wrote:
Since, qspi controller uses quad read.
Configuring the command register, if the transfer of data needs
dual or quad lines.
This patch has been done on top of the following patch
On Monday 29 July 2013 03:01 PM, Felipe Balbi wrote:
Hi,
On Mon, Jul 29, 2013 at 12:52:29PM +0530, Sourav Poddar wrote:
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
new file mode 100644
index 000..51fe95f
--- /dev/null
+++ b/drivers/spi/spi-ti-qspi.c
[ snip
On Monday 29 July 2013 03:50 PM, Felipe Balbi wrote:
Hi,
On Mon, Jul 29, 2013 at 03:42:03PM +0530, Sourav Poddar wrote:
+ frame_length = (m-frame_length 3) / spi-bits_per_word;
there's another way to optimize this. If you assume bits_per_word to
always be power of two you can
On Monday 29 July 2013 04:39 PM, Felipe Balbi wrote:
Hi,
On Mon, Jul 29, 2013 at 04:34:41PM +0530, Sourav Poddar wrote:
+ irq = platform_get_irq(pdev, 0);
+ if (irq0) {
+ dev_err(pdev-dev, no irq resource?\n);
+ return irq
This patch disabled I2C/SPI/UART device initially(status = disabled).
This devices will only be probed, if the devices are
present in the dts file(status = okay).
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/omap5-uevm.dts | 10 +-
arch/arm/boot/dts/omap5
with the ongoing discussion in the
community.
This patch is posted to demonstrate how patch 1 of the series will support
quad read.
[1]: http://comments.gmane.org/gmane.linux.kernel.spi.devel/14047
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/spi/spi-ti-qspi.c | 16
This patch series add support for ti qspi controller.
The previous version link is here:
https://lkml.org/lkml/2013/7/18/154
patch 1 of the previous version already picked.
Resending other two with comments fixed.
Sourav Poddar (2):
drivers: spi: Add qspi flash controller
driver: spi: Add
.
- All iterations went through without failure.
Test2: Use mtd utilities:
- flash_erase to erase the flash device
- nanddump to read data back.
- nandwrite to write to the data flash.
diff between the write and read data shows zero.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
- Modified
On Friday 19 July 2013 10:01 PM, Nishanth Menon wrote:
On 07/19/2013 11:24 AM, Sourav Poddar wrote:
These series add support for I2C/MCSPI/UART pin control datas.
The series is done on top of Rajendra Nayak series[1](posted to the
list),
which has basic dt boot enable for dra7.
These patches
Hi Felipe,
On Thursday 18 July 2013 04:54 PM, Felipe Balbi wrote:
On Thu, Jul 18, 2013 at 04:48:41PM +0530, Sourav Poddar wrote:
+static void qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
+{
+ const u8 *txbuf;
+ int wlen, count;
+
+ count = t-len;
+ txbuf
Hi Mark,
On Thursday 18 July 2013 04:12 PM, Mark Brown wrote:
On Thu, Jul 18, 2013 at 03:31:26PM +0530, Sourav Poddar wrote:
QSPI is a kind of spi module that allows single,
dual and quad read access to external spi devices. The module
has a memory mapped interface which provide direct
Add pin control data for mcspi1 and mcspi2.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts | 33 +
1 files changed, 33 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7
This patch disabled I2C/SPI/UART device initially(status = disabled).
This devices will only be probed, if the devices are
present in the dts file(status = okay).
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 15 +++
1 files changed, 15
://www.spinics.net/lists/linux-omap/msg93535.html
[2]: https://lkml.org/lkml/2013/7/10/335
Sourav Poddar (4):
arm: dts: omap5-evm: Add I2c pinctrl data
arm: dts: omap5-evm: Add I2c pinctrl data
arm: dts: dra7-evm: Add SPI pinctrl data
arm: dts: dra7-evm: Add UART pinctrl data
arch/arm/boot/dts
Add pin control data for i2c1, i2c2 and i2c3.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts | 47
1 files changed, 47 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts
Add pin control datas for uart1, uart2 and uart3.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
arch/arm/boot/dts/dra7-evm.dts | 43
1 files changed, 43 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot
Add support for calculating message length in spi framework.
Add support for quad spi controller.
Patch 2 of this series had been posted before. Sending along
with the series along with ather propsed change.
Sourav Poddar (3):
driver: spi: Modify core to compute the message length
drivers
Make spi core calculate the message length while
populating the other transfer parameters.
Usecase, driver can use it to populate framelength filed in their
controller.
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/spi/spi.c |1 +
include/linux/spi/spi.h |1 +
2
will configure controller clocks, device control
register and for defining low level transfer apis which
will be used by the spi framework to transfer data to
the slave spi device(flash in this case).
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
v3-v4
- Did miscellaneous cleanup
- Added power
as the parent patch goes[1]
[1]: http://comments.gmane.org/gmane.linux.kernel.spi.devel/14047
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
v1-v2
Added support for dual also.
drivers/spi/spi-ti-qspi.c | 17 +++--
1 files changed, 15 insertions(+), 2 deletions(-)
diff --git
Hi Felipe,
On Thursday 18 July 2013 03:54 PM, Felipe Balbi wrote:
Hi,
it might be just me, but ...
On Thu, Jul 18, 2013 at 03:31:26PM +0530, Sourav Poddar wrote:
+static inline unsigned long ti_qspi_readl_data(struct ti_qspi *qspi,
+ unsigned long reg, int wlen
On Thursday 18 July 2013 04:12 PM, Mark Brown wrote:
On Thu, Jul 18, 2013 at 03:31:26PM +0530, Sourav Poddar wrote:
QSPI is a kind of spi module that allows single,
dual and quad read access to external spi devices. The module
has a memory mapped interface which provide direct interface
On Thursday 18 July 2013 04:14 PM, Mark Brown wrote:
On Thu, Jul 18, 2013 at 03:31:27PM +0530, Sourav Poddar wrote:
Since, qspi controller uses quad read.
Configuring the command register, if the transfer of data needs
dual or quad lines.
This patch has been done on top of the following patch
On Thursday 18 July 2013 04:54 PM, Felipe Balbi wrote:
On Thu, Jul 18, 2013 at 04:48:41PM +0530, Sourav Poddar wrote:
+static void qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
+{
+ const u8 *txbuf;
+ int wlen, count;
+
+ count = t-len;
+ txbuf = t-tx_buf
case where we would need to handle IRQs
which we decided to mask, but perhaps there might be some cases, I don't
know.
Based on that, I believe Sourav is reading IRQSTATUS_RAW$n, then he need
to clear the masked bits.
That's not the issue - the issue is that if none of the unmasked
interrupts
On Friday 19 July 2013 12:38 AM, Trent Piepho wrote:
On Thu, Jul 18, 2013 at 3:01 AM, Sourav Poddarsourav.pod...@ti.com wrote:
+Required properties:
+- compatible : should be ti,dra7xxx-qspi.
+- reg: Should contain QSPI registers location and length.
+- #address-cells, #size-cells : Must
On Monday 08 July 2013 08:02 PM, Felipe Balbi wrote:
Hi,
On Mon, Jul 08, 2013 at 07:12:59PM +0530, Sourav Poddar wrote:
+static inline unsigned long dra7xxx_readl(struct dra7xxx_qspi *qspi,
+ unsigned long reg)
+{
+ return readl(qspi-base + reg);
+}
+
+static inline void
On Tuesday 09 July 2013 02:03 AM, Nishanth Menon wrote:
On 19:12-20130708, Sourav Poddar wrote:
[..]
generic comment, given our historical mistakes of making drivers
specific to a SoC family, it never is.
Now, ti-qspi in file name is a step in the right direction, but, rest
of the code(function
On Monday 08 July 2013 08:02 PM, Felipe Balbi wrote:
Hi,
On Mon, Jul 08, 2013 at 07:12:59PM +0530, Sourav Poddar wrote:
+static inline unsigned long dra7xxx_readl(struct dra7xxx_qspi *qspi,
+ unsigned long reg)
+{
+ return readl(qspi-base + reg);
+}
+
+static inline void
Add support for calculating message length in spi framework.
Add support for quad spi controller.
Patch 2 of this series had been posted before. Sending along
with the series along with ather propsed change.
Sourav Poddar (3):
driver: spi: Modify core to compute the message length
drivers
Make spi core calculate the message length while
populating the other transfer parameters. This will
be useful in cases where controller driver need to configure its
framelength field without iterating through the linklist again in the
driver controller.
Signed-off-by: Sourav Poddar sourav.pod
will configure controller clocks, device control
register and for defining low level transfer apis which
will be used by the spi framework to transfer data to
the slave spi device(flash in this case).
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
v2-v3
1. Add threaded irq support
2. made the driver
://comments.gmane.org/gmane.linux.kernel.spi.devel/14047
Signed-off-by: Sourav Poddar sourav.pod...@ti.com
---
drivers/spi/spi-ti-qspi.c |8 ++--
1 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 430de9c..307cbed 100644
101 - 200 of 485 matches
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