While we are at it, this new mapping could do
PROC_ReserveMemory at the same time so that the user-space application
doesn't get a chance to modify the pa.
-- What does PROC_ReserveMemory has to do with pa ?
Sorry, I don't know what kind of address PROC_ReserveMemory returns
(va?),
AM
To: felipe.contre...@gmail.com
Cc: Kanigeri, Hari; Menon, Nishanth; linux-omap@vger.kernel.org; Menon,
Nishanth
Subject: Re: [PATCH 2/2] DSPBRIDGE: add checking 128 byte alignment for
dsp cache line size
From: ext Felipe Contreras felipe.contre...@gmail.com
Subject: Re: [PATCH 2/2
On Fri, May 15, 2009 at 5:54 PM, Kanigeri, Hari h-kanige...@ti.com wrote:
While we are at it, this new mapping could do
PROC_ReserveMemory at the same time so that the user-space application
doesn't get a chance to modify the pa.
-- What does PROC_ReserveMemory has to do with pa ?
checking 128 byte alignment for
dsp cache line size
On Fri, May 15, 2009 at 5:54 PM, Kanigeri, Hari h-kanige...@ti.com
wrote:
While we are at it, this new mapping could do
PROC_ReserveMemory at the same time so that the user-space
application
doesn't get a chance to modify the pa
On Fri, May 15, 2009 at 8:32 PM, Kanigeri, Hari h-kanige...@ti.com wrote:
Do you know of any client that doing ReseveMemory and Map independently?
How much overhead is there in ReserveMemory?
What happens if the Map size is different than the ReserveMemory? What
happens if the size is bigger?
Hi Felipe,
-- I cannot disclose the name, but it is some major Mobile Company that
is following this approach. One big chunk of DSP Virtual address region is
grabbed during boot time, and after that all the maps/unmaps are managed
from this memory region.
On Linux?
-- Yes.
So the DSP
From: ext Felipe Contreras felipe.contre...@gmail.com
Subject: Re: [PATCH 2/2] DSPBRIDGE: add checking 128 byte alignment for dsp
cache line size
Date: Tue, 12 May 2009 23:41:04 +0200
On Tue, May 12, 2009 at 8:38 AM, Hiroshi DOYU hiroshi.d...@nokia.com wrote:
From: ext Kanigeri, Hari h-kanige
On Wed, May 13, 2009 at 12:10 PM, Hiroshi DOYU hiroshi.d...@nokia.com wrote:
From: ext Felipe Contreras felipe.contre...@gmail.com
Subject: Re: [PATCH 2/2] DSPBRIDGE: add checking 128 byte alignment for dsp
cache line size
Date: Tue, 12 May 2009 23:41:04 +0200
On Tue, May 12, 2009 at 8:38
From: ext Felipe Contreras felipe.contre...@gmail.com
Subject: Re: [PATCH 2/2] DSPBRIDGE: add checking 128 byte alignment for dsp
cache line size
Date: Wed, 13 May 2009 13:13:35 +0200
On Wed, May 13, 2009 at 12:10 PM, Hiroshi DOYU hiroshi.d...@nokia.com wrote:
From: ext Felipe Contreras
On Wed, May 13, 2009 at 5:18 PM, Hiroshi DOYU hiroshi.d...@nokia.com wrote:
From: ext Felipe Contreras felipe.contre...@gmail.com
Subject: Re: [PATCH 2/2] DSPBRIDGE: add checking 128 byte alignment for dsp
cache line size
Date: Wed, 13 May 2009 14:50:26 +0200
[...]
If we are not going
cache line size
From: ext Kanigeri, Hari h-kanige...@ti.com
Subject: RE: [PATCH 2/2] DSPBRIDGE: add checking 128 byte
alignment for dsp cache line size
Date: Mon, 11 May 2009 20:26:11 +0200
To summarize the discussion.
Thanks
We need to have the check for 128 bytes alignment (upper
On Tue, May 12, 2009 at 8:38 AM, Hiroshi DOYU hiroshi.d...@nokia.com wrote:
From: ext Kanigeri, Hari h-kanige...@ti.com
Subject: RE: [PATCH 2/2] DSPBRIDGE: add checking 128 byte alignment for dsp
cache line size
Date: Mon, 11 May 2009 20:26:11 +0200
To summarize the discussion.
Thanks
Hi Doyu-san,
A buffer shared with MPU and DSP has to be aligned on both cache line
size to avoid memory corrupton with some DSP cache operations. Since
there's no way for dspbridge to know how the shared buffer will be
used like: read-only, write-only, rw through its life span, any
shared
Hi Hari,
From: ext Kanigeri, Hari h-kanige...@ti.com
Subject: RE: [PATCH 2/2] DSPBRIDGE: add checking 128 byte alignment for dsp
cache line size
Date: Mon, 11 May 2009 17:09:03 +0200
Hi Doyu-san,
A buffer shared with MPU and DSP has to be aligned on both cache line
size to avoid memory
Hi Doyu-san,
Hi Hari,
From: ext Kanigeri, Hari h-kanige...@ti.com
Subject: RE: [PATCH 2/2] DSPBRIDGE: add checking 128 byte alignment for
dsp cache line size
Date: Mon, 11 May 2009 17:09:03 +0200
Hi Doyu-san,
A buffer shared with MPU and DSP has to be aligned on both cache line
On Mon, May 11, 2009 at 6:47 PM, Hiroshi DOYU hiroshi.d...@nokia.com wrote:
Hi Hari,
From: ext Kanigeri, Hari h-kanige...@ti.com
Subject: RE: [PATCH 2/2] DSPBRIDGE: add checking 128 byte alignment for dsp
cache line size
Date: Mon, 11 May 2009 17:09:03 +0200
Hi Doyu-san,
A buffer
On Mon, May 11, 2009 at 7:26 PM, Kanigeri, Hari h-kanige...@ti.com wrote:
Hi Doyu-san,
Hi Hari,
From: ext Kanigeri, Hari h-kanige...@ti.com
Subject: RE: [PATCH 2/2] DSPBRIDGE: add checking 128 byte alignment for
dsp cache line size
Date: Mon, 11 May 2009 17:09:03 +0200
Hi Doyu-san
On Mon, May 11, 2009 at 8:35 PM, Hiroshi DOYU hiroshi.d...@nokia.com wrote:
From: ext Felipe Contreras felipe.contre...@gmail.com
Subject: Re: [PATCH 2/2] DSPBRIDGE: add checking 128 byte alignment for dsp
cache line size
Date: Mon, 11 May 2009 18:31:28 +0200
On Mon, May 11, 2009 at 6:47 PM
From: ext Felipe Contreras felipe.contre...@gmail.com
Subject: Re: [PATCH 2/2] DSPBRIDGE: add checking 128 byte alignment for dsp
cache line size
Date: Mon, 11 May 2009 18:31:28 +0200
On Mon, May 11, 2009 at 6:47 PM, Hiroshi DOYU hiroshi.d...@nokia.com wrote:
Hi Hari,
From: ext Kanigeri
: [PATCH 2/2] DSPBRIDGE: add checking 128 byte alignment for
dsp cache line size
On Mon, May 11, 2009 at 8:35 PM, Hiroshi DOYU hiroshi.d...@nokia.com
wrote:
From: ext Felipe Contreras felipe.contre...@gmail.com
Subject: Re: [PATCH 2/2] DSPBRIDGE: add checking 128 byte alignment for
dsp cache
On Mon, May 11, 2009 at 9:26 PM, Kanigeri, Hari h-kanige...@ti.com wrote:
To summarize the discussion.
We need to have the check for 128 bytes alignment (upper and lower). The 2
places that this can be done are in flush function or in Map function.
- I prefer the check is done in Map
Felipe,
IMHO the only sensible way to approach this is to create a new ioctl
for a special restrictive mapping where user-space specifies if the
memory area is read-only or write-only and the size must be the real
size. This also has advantage that it does not break legacy
applications.
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