From: Ulrich Hecht
Adds compatible strings for the R-Car CAN FD controller in the D3 SoC.
Signed-off-by: Ulrich Hecht
Acked-by: Rob Herring
Reviewed-by: Geert Uytterhoeven
Reviewed-by: Simon Horman
---
Documentation/devicetree/bindings/net/can/rcar_canfd.txt | 8
1 file changed, 4
From: Ulrich Hecht
Adds compatible strings for the R-Car CAN controller in the D3 SoC.
Signed-off-by: Ulrich Hecht
Acked-by: Rob Herring
Reviewed-by: Geert Uytterhoeven
Reviewed-by: Simon Horman
---
Documentation/devicetree/bindings/net/can/rcar_can.txt | 3 ++-
1 file changed, 2
Hi!
These are the bindings for CAN and CAN FD controllers on R-Car D3
(R8A77995).
Changes since v2:
- rebased
- made wording less redundant in rcar_canfd.txt
- added dt-bindings prefix to subjects
CU
Uli
Ulrich Hecht (2):
dt-bindings: can: rcar_can: add r8a77995 (R-Car D3) compatibility
> On November 16, 2018 at 9:42 AM Geert Uytterhoeven
> wrote:
>
>
> Hi Uli,
>
> On Fri, Nov 16, 2018 at 8:21 AM Ulrich Hecht wrote:
> > Used by I2C controllers 0, 3 and 5 in R8A7795 and R8A7796 SoCs.
> >
> > Signed-off-by: Ulrich Hecht
>
> T
From: Takeshi Kihara
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7795 SoC.
These pins are physically muxed with other pins. Therefore, setup of
MOD_SEL is needed for exclusive control with other pins.
Signed-off-by: Takeshi Kihara
Signed-off-by: Ulrich Hecht
---
drivers
From: Takeshi Kihara
This patch adds I2C{0,3,5} pins, groups and functions to
the R8A7795 ES1.x SoC.
These pins are physically muxed with other pins. Therefore, setup of
MOD_SEL is needed for exclusive control with other pins.
Signed-off-by: Takeshi Kihara
Signed-off-by: Ulrich Hecht
From: Takeshi Kihara
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7796 SoC.
These pins are physically muxed with other pins. Therefore, setup of
MOD_SEL is needed for exclusive control with other pins.
Signed-off-by: Takeshi Kihara
Signed-off-by: Ulrich Hecht
---
drivers
Used by I2C controllers 0, 3 and 5 in R8A7795 and R8A7796 SoCs.
Signed-off-by: Ulrich Hecht
---
drivers/pinctrl/sh-pfc/sh_pfc.h | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 1fc1336..6bb9c6b
I2C{0,3,5} pins, groups and
functions
pinctrl: sh-pfc: r8a7796: Add I2C{0,3,5} pins, groups and functions
Ulrich Hecht (1):
pinctrl: sh-pfc: Add physical pin multiplexing helper macros
drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c | 97 ---
drivers/pinctrl/sh-pfc
77486..5aafe548ca5f3082 100644
> --- a/drivers/dma/sh/shdmac.c
> +++ b/drivers/dma/sh/shdmac.c
> @@ -665,12 +665,6 @@ static const struct shdma_ops sh_dmae_shdma_ops = {
> .get_partial = sh_dmae_get_partial,
> };
>
> -static const struct of_device_id sh_dmae_of_match[] = {
> - {.compatible = "renesas,shdma-r8a73a4", .data = r8a73a4_shdma_devid,},
> - {}
> -};
> -MODULE_DEVICE_TABLE(of, sh_dmae_of_match);
> -
> static int sh_dmae_probe(struct platform_device *pdev)
> {
> const enum dma_slave_buswidth widths =
> @@ -915,7 +909,6 @@ static struct platform_driver sh_dmae_driver = {
> .driver = {
> .pm = _dmae_pm,
> .name = SH_DMAE_DRV_NAME,
> - .of_match_table = sh_dmae_of_match,
> },
> .remove = sh_dmae_remove,
> };
> --
> 2.17.1
>
Reviewed-by: Ulrich Hecht
CU
Uli
rx)
> - sci_receive_chars(ptr);
> + sci_receive_chars(port);
> }
>
> sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
> --
> 2.17.1
>
Reviewed-by: Ulrich Hecht
CU
Uli
ort->port.type == PORT_SCIFB ||
> - port->port.type == PORT_HSCIF) {
> + if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF) {
> sysfs_remove_file(>dev.kobj,
> _attr_rx_fifo_timeout.attr);
> }
> --
> 1.9.1
>
Reviewed-by: Ulrich Hecht
CU
Uli
Signed-off-by: Ulrich Hecht
---
drivers/tty/serial/sh-sci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 426241d..ff6ba6d 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -1516
Sorry for the delay...
> On April 13, 2018 at 7:27 PM Geert Uytterhoeven wrote:
>
> On Fri, Apr 13, 2018 at 7:00 PM, Ulrich Hecht
> wrote:
> > These patches make sure that the device is up while the suspend/resume code
> > is executed. Up-port from the BSP, t
> On September 4, 2018 at 9:20 AM Wolfram Sang wrote:
>
>
> On Mon, Sep 03, 2018 at 12:02:19PM +0100, Mark Brown wrote:
> > On Mon, Sep 03, 2018 at 11:28:19AM +0200, Wolfram Sang wrote:
> > > On Fri, Aug 24, 2018 at 11:12:31AM +0200, Ulrich Hecht wrote:
&
Document support for the MSIOF module in the Renesas D3 (r8a77995) SoC.
No driver update is needed.
Signed-off-by: Ulrich Hecht
Reviewed-by: Simon Horman
Reviewed-by: Geert Uytterhoeven
---
This patch fell by the wayside, probably because I forgot to cc devicetree.
CU
Uli
Documentation
Hi!
This series adds CPU idle support for H3 and M3-W. It's a straight
up-port from the BSP.
The part that disables cpuidle for the CA53 cores on M3ULCB is a bit
dodgy. Is it a valid assumption that all M3ULCB boards have an ES1.0
SoC?
CU
Uli
Dien Pham (2):
arm64: dts: r8a7795: Add cpuidle
[dien.pham.ry: Apply new cpuidle parameters]
Signed-off-by: Dien Pham
Signed-off-by: Ulrich Hecht
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index
parameters]
Signed-off-by: Dien Pham
Signed-off-by: Takeshi Kihara
Signed-off-by: Ulrich Hecht
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index
From: Dien Pham
Enable cpuidle (core shutdown) support for R-Car M3-W CA53 cores.
Signed-off-by: Dien Pham
Signed-off-by: Takeshi Kihara
Signed-off-by: Ulrich Hecht
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64
From: Takeshi Kihara
The revision of the R8A7796 SoC on the M3ULCB board is ES1.0. This revision
can not use cpuidle for CA53 cores.
Therefore, this patch disables cpuidle support for CA53 cores.
Signed-off-by: Takeshi Kihara
Signed-off-by: Ulrich Hecht
---
arch/arm64/boot/dts/renesas
From: Dien Pham
Enables cpuidle (core shutdown) support for R-Car H3 CA53 cores.
Signed-off-by: Dien Pham
Signed-off-by: Takeshi Kihara
Signed-off-by: Ulrich Hecht
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64
From: Takeshi Kihara
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7796 SoC.
These pins are physically muxed with other pins. Therefore, setup of
MOD_SEL is needed for exclusive control with other pins.
Signed-off-by: Takeshi Kihara
Signed-off-by: Ulrich Hecht
---
drivers
From: Takeshi Kihara
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7795 SoC.
These pins are physically muxed with other pins. Therefore, setup of
MOD_SEL is needed for exclusive control with other pins.
Signed-off-by: Takeshi Kihara
Signed-off-by: Ulrich Hecht
---
drivers
From: Takeshi Kihara
This patch adds I2C{0,3,5} pins, groups and functions to
the R8A7795 ES1.x SoC.
These pins are physically muxed with other pins. Therefore, setup of
MOD_SEL is needed for exclusive control with other pins.
Signed-off-by: Takeshi Kihara
Signed-off-by: Ulrich Hecht
Hi!
This is an up-port from the BSP. Unfortunately I could not test these
because none of those pins seem to be accessible on Salvator boards (not on
ULCB either, AFAICT), so the best thing I can say is that they don't seem to
break anything.
CU
Uli
Takeshi Kihara (3):
pinctrl: sh-pfc:
ceived data is the _LAST_, go to new phase. */
> + if (priv->pos + 1 == msg->len) {
> + if (priv->flags & ID_LAST_MSG) {
> + rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
> + } else {
> + rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
> + priv->flags |= ID_P_REP_AFTER_RD;
> + }
> + }
So "priv->pos + 1 <= msg->len" is an invariant? (The current code seems to
imply that it isn't.)
If it is,
Reviewed-by: Ulrich Hecht
CU
Uli
sometimes */
> +#define ID_P_PM_BLOCKED BIT(31)
> +#define ID_P_MASKGENMASK(31, 30)
>
> enum rcar_i2c_type {
> I2C_RCAR_GEN1,
> --
> 2.11.0
>
Reviewed-by: Ulrich Hecht
CU
Uli
bri->set_sda(adap, 1);
> - ndelay(RECOVERY_NDELAY);
> + bri->set_sda(adap, scl);
> + ndelay(RECOVERY_NDELAY / 2);
>
> /*
> * By this time SCL is high, as we need to give 9 falling-rising edges
> --
> 2.11.0
>
Reviewed-by: Ulrich Hecht
CU
Uli
arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 106
>> > +
>> > arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts | 120
>> >
>>
>> Laurent, could you review this?
>
> Ping
For the Condor part:
Reviewed-by: Ulrich Hecht
Unfortunately, I do not have documentation for the other board.
CU
Uli
Document support for the MSIOF module in the Renesas D3 (r8a77995) SoC.
No driver update is needed.
Signed-off-by: Ulrich Hecht
Reviewed-by: Simon Horman
Reviewed-by: Geert Uytterhoeven
---
Added Reviewed-bys.
CU
Uli
Documentation/devicetree/bindings/spi/sh-msiof.txt | 1 +
1 file changed
From: Hiroyuki Yokoyama
Renesas R-Car E3 (R8A77990) SoC also has the R-Car gen2/3 compatible DMA
controllers, so document the SoC specific binding.
Signed-off-by: Hiroyuki Yokoyama
Signed-off-by: Ulrich Hecht
Reviewed-by: Simon Horman
Acked-by: Rob Herring
Reviewed-by: Geert Uytterhoeven
From: Hiromitsu Yamasaki
This patch adds MSIOF device nodes for the R8A77995 SoC.
Signed-off-by: Hiromitsu Yamasaki
Signed-off-by: Takeshi Kihara
[uli: remove unimplemented ref clock, clock-names]
Signed-off-by: Ulrich Hecht
---
Removed clock-names and fixed the number formatting. Thanks
On Thu, May 17, 2018 at 9:56 AM, Wolfram Sang <w...@the-dreams.de> wrote:
> On Wed, May 16, 2018 at 03:05:15PM +0200, Ulrich Hecht wrote:
>> From: Hiromitsu Yamasaki <hiromitsu.yamasaki...@renesas.com>
>>
>> This patch adds MSIOF device nodes for the R8A77995 So
ase of the temperature
> reported by the 'temp' attribute.
Pointing a heat gun at the SoC, I managed to get the temperature up to
8, and it went back to 40000 when I removed it. I'd say this
works.
Tested-By: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
CU
Uli
On Wed, May 16, 2018 at 10:59 AM, Sergei Shtylyov
<sergei.shtyl...@cogentembedded.com> wrote:
> Hello!
>
> On 5/16/2018 10:54 AM, Simon Horman wrote:
>
>>> Add support for the R-Car D3 (R8A77995) SoC to the LVDS encoder driver.
>>>
>>> Signed-off-by:
shed]
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt
b/Documentation/devicetree/bindings/dma/renesas,
From: Hiroyuki Yokoyama <hiroyuki.yokoyama...@renesas.com>
Renesas R-Car E3 (R8A77990) SoC also has the R-Car gen2/3 compatible DMA
controllers, so document the SoC specific binding.
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama...@renesas.com>
Signed-off-by: Ulrich Hecht &
From: Takeshi Kihara <takeshi.kihara...@renesas.com>
This patch adds the device nodes for SCIF-{0,1,3,4,5} serial ports,
incl. clocks and power domain.
Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
--
ref clock]
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
arch/arm64/boot/dts/renesas/r8a77995.dtsi | 66 +++
1 file changed, 66 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
b/arch/arm64/boot/dts/renesas/r8a77995.dts
Document support for the MSIOF module in the Renesas D3 (r8a77995) SoC.
No driver update is needed.
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
Documentation/devicetree/bindings/spi/sh-msiof.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devi
Adds LVDS decoder, HDMI encoder and connector for Draak boards.
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 80 ++
1 file changed, 80 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8
Add support for the R-Car D3 (R8A77995) SoC to the LVDS encoder driver.
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
drivers/gpu/drm/rcar-du/rcar_lvds.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c
b/drivers/gpu/drm/r
From: Kieran Bingham <kieran.bingham+rene...@ideasonboard.com>
The r8a77995 D3 platform has 2 LVDS channels connected to the DU.
Signed-off-by: Kieran Bingham <kieran.bingham+rene...@ideasonboard.com>
[uli: moved lvds* into the soc node, added PM domains, resets]
Signed-off-by:
74.25 Mhz oscillator X12 is connected to DU_DOTCLKIN0.
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
b/arch
From: Koji Matsuoka <koji.matsuoka...@renesas.com>
Add support for the R-Car D3 (R8A77995) SoC to the R-Car DU driver.
Signed-off-by: Koji Matsuoka <koji.matsuoka...@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
drivers/gpu/drm/rcar-du/
arm64: dts: renesas: r8a77995: Add LVDS support
Koji Matsuoka (1):
drm: rcar-du: Add r8a77995 device support
Ulrich Hecht (3):
drm: rcar-du: lvds: Add R8A77995 support
arm64: dts: renesas: r8a77995-draak: add HDMI output
arm64: dts: renesas: r8a77995-draak: add X12 input dot clock
arch/arm6
On Fri, Apr 27, 2018 at 6:03 PM, Laurent Pinchart
<laurent.pinch...@ideasonboard.com> wrote:
> Hi Ulrich,
>
> On Thursday, 15 March 2018 16:45:36 EEST Ulrich Hecht wrote:
>> Hi!
>>
>> I have run the tests on a Renesas R-Car M3-W's DU device, and have fou
...@renesas.com>
[uli: simplified code, added pm field to platform driver]
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
Slightly brushed up port from the BSP; tested to execute on suspend/resume
without breaking anything.
CU
Uli
drivers/spi/spi-sh-msiof.c | 23 +++
by: Hiromitsu Yamasaki <hiromitsu.yamasaki...@renesas.com>
[uli: edited description for clarity]
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
drivers/tty/serial/sh-sci.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/tty/serial/sh-s
Hi!
These patches make sure that the device is up while the suspend/resume code
is executed. Up-port from the BSP, tested not to break stuff.
CU
Uli
Hien Dang (2):
serial: sh-sci: Use pm_runtime_get_sync()/put() on suspend
serial: sh-sci: Use pm_runtime_get_sync()/put() on resume
suspend by using pm_runtime_get_sync()/pm_runtime_put().
Signed-off-by: Hien Dang <hien.dang...@renesas.com>
Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki...@renesas.com>
[uli: edited description for clarity]
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
driver
the sampling point can improve
the error margin and will enable it if so.
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
This revision dumps the sysfs interface and works out the optimal shift
on its own. It also moves setting of the HSSRR register back to its
original location.
On Fri, Mar 16, 2018 at 9:55 AM, Daniel Vetter <dan...@ffwll.ch> wrote:
> On Thu, Mar 15, 2018 at 03:45:36PM +0100, Ulrich Hecht wrote:
>> Hi!
>>
>> I have run the tests on a Renesas R-Car M3-W's DU device, and have found a
>> number of false negatives that mostly
Use union vin_data and VIN_DATA_PIN_GROUP() to reduce redundancies
in pin definitions.
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 308 ---
1 file changed, 72 insertions(+), 236 deletions(-)
diff
Use union vin_data and VIN_DATA_PIN_GROUP() to reduce redundancies
in pin definitions.
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 154 --
1 file changed, 36 insertions(+), 118 deletions(-)
diff
Hi!
This fixes the incorrect RGB666 pin assignments reported by Geert in H3,
M3-W and D3 SoCs. Thank you!
CU
Uli
Ulrich Hecht (3):
pinctrl: sh-pfc: r8a7795: correct VIN4 18-bit pins
pinctrl: sh-pfc: r8a7796: correct VIN4 18-bit pins
pinctrl: sh-pfc: r8a77995: correct VIN4 18-bit pins
RGB666 has a pin assignment that differs from the other formats.
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r
Hi!
This uses union vin_data and VIN_DATA_PIN_GROUP() to reduce redundancy
in the VIN4 pin data on H3, M3-W and D3 SoCs.
CU
Uli
Ulrich Hecht (3):
pinctrl: sh-pfc: r8a7795: deduplicate VIN4 pin definitions
pinctrl: sh-pfc: r8a7796: deduplicate VIN4 pin definitions
pinctrl: sh-pfc
Use union vin_data and VIN_DATA_PIN_GROUP() to reduce redundancies
in pin definitions.
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 308 ---
1 file changed, 72 insertions(+), 236 deletions(-)
diff
RGB666 has a pin assignment that differs from the other formats.
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7799
RGB666 has a pin assignment that differs from the other formats.
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r
Fixes fails on low-memory devices.
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
tests/kms_addfb_basic.c | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/tests/kms_addfb_basic.c b/tests/kms_addfb_basic.c
index cf9ba37..d
Add is_i915_device() requirement to tests using Intel-specific APIs.
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
tests/kms_addfb_basic.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tests/kms_addfb_basic.c b/tests/kms_addfb_basic.c
index 7d8852f..cf9ba37
Fixes failed assertion on non-i915 devices.
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
lib/igt_gt.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index 9cb07c2..825ea52 100644
--- a/lib/igt_gt.c
+++ b/lib/ig
Ignores failure to add DRM_FORMAT_C8 frame buffer; some devices do not
support any 8-bit format.
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
tests/kms_addfb_basic.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/kms_addfb_basic.c b
Fixes false negatives on non-i915 platforms.
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
tests/kms_panel_fitting.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/kms_panel_fitting.c b/tests/kms_panel_fitting.c
index b3cee22..6d0be50 100644
--- a
Fixes false negatives on everything that doesn't happen to be at a
specific hard-coded sysfs path...
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
lib/igt_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/igt_pm.c b/lib/igt_pm.c
index 5
Hi!
I have run the tests on a Renesas R-Car M3-W's DU device, and have found a
number of false negatives that mostly stem from use of Intel-specifics
without checking if that makes sense first. So here's a bunch of fixes for
those, hope they are generic enough for upstreaming.
CU
Uli
Ulrich
Add is_i915_device() requirement to tests using Intel-specific APIs.
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
tests/kms_plane_lowres.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/kms_plane_lowres.c b/tests/kms_plane_lowres.c
index d1e4b3c..8fc7654
Checks if we have an i915 device before using intel_get_drm_devid().
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
lib/igt_gt.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index e630550..9cb07c2
On Tue, Feb 20, 2018 at 2:58 PM, Geert Uytterhoeven
wrote:
> Would there be a use case for vin4_data4 and vin5_data4, or is that
> mode only supported on R-Car H2?
The docs don't mention it, so I would assume it's not supported.
CU
Uli
On Thu, Feb 15, 2018 at 2:12 PM, Wolfram Sang wrote:
>
>> This can be prevented by doing a dummy read of the RX data register.
>
> Just so I understand the issue correctly: We are reading the register to
> throw the content away to prevent it being used in the TTY buffers?
From: Takeshi Kihara <takeshi.kihara...@renesas.com>
This patch adds TMU TCLK{1,2} pins, groups and functions to
the R8A7795 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
drivers/pinctrl/sh
Hi!
Straight from the BSP, TMU pins for r8a7795{,-es1} and r8a7796. Magic
numbers verified according to "pinfunction" document revisions 0.54 (M3-W)
and 0.553 (H3).
CU
Uli
Takeshi Kihara (3):
pinctrl: sh-pfc: r8a7795: Add TMU pins, groups and functions
pinctrl: sh-pfc: r8a7795-es1: Add TMU
From: Takeshi Kihara <takeshi.kihara...@renesas.com>
This patch adds TMU TCLK{1,2} pins, groups and functions to
the R8A7796 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
drivers/pinctrl/sh
From: Takeshi Kihara <takeshi.kihara...@renesas.com>
This patch adds TMU TCLK{1,2} pins, groups and functions to
the R8A7795 ES1.x SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
drivers/
Hi!
Straight from the BSP, HDMI pins for r8a7795{,-es1} and r8a7796. Magic
numbers verified according to "pinfunction" document revisions 0.54 (M3-W)
and 0.553 (H3).
CU
Uli
Takeshi Kihara (3):
pinctrl: sh-pfc: r8a7795: Add HDMI pins, groups and functions
pinctrl: sh-pfc: r8a7795-es1: Add
From: Takeshi Kihara <takeshi.kihara...@renesas.com>
This patch adds HDMI0 CEC pin, group and function to the R8A7796 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
drivers/pinctrl/sh-pfc/
From: Takeshi Kihara <takeshi.kihara...@renesas.com>
This patch adds HDMI0 CEC pin, group and function to the R8A7795 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
[uli: fixed typo in comment]
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
--
User's Manual Rev.0.51E or later.
Fixes: f9aece7344bd ("pinctrl: sh-pfc: Initial R8A7796 PFC support")
Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
drivers/pinct
Fixes: b205914c8f82 ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 ES2.0")
Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 40 ++--
From: Takeshi Kihara <takeshi.kihara...@renesas.com>
This patch adds HDMI0 CEC pin, group and function to
the R8A7795 ES1.x SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
[uli: fixed typo in comment]
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.co
Hi!
This series contains fixes to the PFC register definitions for r8a7795 and
r8a7796 from the BSP that are not upstream yet.
As far as I could tell, these changes check out with the Gen3 datasheet
revision 0.80.
CU
Uli
Takeshi Kihara (3):
pinctrl: sh-pfc: r8a7795: Fix MOD_SEL register pin
OD_SEL register
pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware
User's Manual Rev.0.53E.
Fixes: f9aece7344bd ("pinctrl: sh-pfc: Initial R8A7796 PFC support")
Signed-off-by: Takeshi Kihara <takeshi.kihara...@renesas.com>
Signed-off-by: Ulrich Hecht <ulric
High latencies of classic timers cause performance issues for high-
speed serial transmissions. This patch transforms rx_timer into an
hrtimer to reduce the minimum latency.
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
drivers/tty/serial/sh-sci.
both HSCIF and SCIF ports. Reported for R-Car H3 ES2.0;
reproduced and fixed on H3 ES1.1. Probably affects other R-Car platforms
as well.
Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda...@renesas.com>
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
drivers/tty/serial/
l: sh-pfc: r8a77995: Add DU support") posted earlier
today by kbingham in his "[PATCH 0/8] r8a77995 D3 DU and LVDS support"
series.]
CU
Uli
Ulrich Hecht (4):
pinctrl: sh-pfc: r8a7796: Add VIN4, VIN5 pins, groups and functions
pinctrl: sh-pfc: r8a7795: Add VIN4, VIN5 pins,
This patch adds VIN4 and VIN5 pins, groups and functions for the
R8A7795 SoC.
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 454 +++
1 file changed, 454 insertions(+)
diff --git a/drivers/pinctrl/
This patch adds VIN4 and VIN5 pins, groups and functions for the
R8A7796 SoC.
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 454 +++
1 file changed, 454 insertions(+)
diff --git a/drivers/pinctrl/
This patch adds VIN4 pins, groups and function for the
R8A77995 (D3) SoC.
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 192 ++
1 file changed, 192 insertions(+)
diff --git a/drivers/pinctrl/sh-p
This patch adds DU pins, groups and function for the R8A77995 (D3) SoC.
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
drivers/pinctrl/sh-pfc/pfc-r8a77995.c | 101 ++
1 file changed, 101 insertions(+)
diff --git a/drivers/pinctrl/sh-p
Defines R-Car D3 I2C controllers 0-3.
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
arch/arm64/boot/dts/renesas/r8a77995.dtsi | 67 +++
1 file changed, 67 insertions(+)
diff
On Thu, Nov 16, 2017 at 10:31 AM, Geert Uytterhoeven
wrote:
> If no devices are connected, perhaps it's wise to defer the status update
> to e.g. an overlay that describes what's connected to CN23?
>
> Or do you want it enabled to allow adding devices manually using
>
No devices to add, I2C1 has an external connector only.
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 11 +++
1 file changed, 11 insertions(+)
diff
R-Car D3 (R8A77995) SoC has a R-Car Gen3-compatible I2C controller.
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
Documentation/devicetree/bindings/i2c/i2c-rcar.txt | 1 +
1 file changed, 1 insertion(+)
Enables EEPROM on I2C0 on the Draak board.
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 17 +
1 file changed, 17 insertions(+)
diff --git
Both manufacturer and name variant.
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
---
Documentation/devicetree/bindings/eeprom/at24.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/eeprom/at24.txt
b/Documentation/devicetree/bi
been picked up
- i2c-rcar: patch dropped, redundant
- dtsi: added dmac2 for i2c0-2
- dtsi: fixed internal SCL delays
- dts: fixed EEPROM compatible string
- bindings: added Rohm EEPROM
- bindings: fixed typo in i2c-rcar bindings
Ulrich Hecht (5):
arm64: renesas: r8a77995: add I2C support
arm64
Adds serdev_device_set_parity() and an implementation for ttyport.
The interface uses an enum with the values SERIAL_PARITY_NONE,
SERIAL_PARITY_EVEN and SERIAL_PARITY_ODD.
Signed-off-by: Ulrich Hecht <ulrich.hecht+rene...@gmail.com>
Reviewed-by: Sebastian Reichel <sebas
1 - 100 of 423 matches
Mail list logo