Omg, you are really know to less of hardware.
RXC+/- === Clkin+/-
VSS=GND=ground
VCC=VDD=3.3V power supply
2014-10-11 14:43 GMT+08:00 đeli hađiselimović kelama...@gmail.com:
Yeah I got that, but I still dont know which one is the Clkin+/-, ground and
VDD..
Dana subota, 11. listopada 2014.
A big client will buy thousands of chips once. Are there any relation
between big client and user manual publishing? No. So they don't think it's
necessary to open their private property. When you are a big client, you
are VIP, all document and source code is open to you. And if publish all
On Sat, Oct 11, 2014 at 10:31 AM, jacky lau i900...@gmail.com wrote:
A big client will buy thousands of chips once. Are there any relation
between big client and user manual publishing? No. So they don't think it's
necessary to open their private property. When you are a big client, you are
Keeping so called 'secrets' is really insane. Allwinner overestimated
the value of some little tricks in their chips, or is too lazy to help
their small or potential customers. If they keep act this way, they
will pay the price sometime later. Intel had ever do the same stupid
thing, and now
On 10/11/14 15:31, jacky lau wrote:
A big client will buy thousands of chips once. Are there any relation
between big client and user manual publishing? No. So they don't think
it's necessary to open their private property. When you are a big
client, you are VIP, all document and source code
On Sat, 2014-10-04 at 20:37 +0800, Chen-Yu Tsai wrote:
On later Allwinner SoCs, the watchdog hardware is by all means a
separate hardware block, with its own address range and interrupt
line.
Move the register definitions to a separate file to facilitate
supporting newer SoCs.
On Sat, 2014-10-04 at 20:37 +0800, Chen-Yu Tsai wrote:
The RTC hardware has been moved out of the timer block on sun6i/sun8i.
In addition, there are more watchdogs available.
Also note that the timer block definition is not completely accurate
for sun5i/sun7i. Various blocks are missing or
On Mon, 2014-10-06 at 19:57 +0200, Hans de Goede wrote:
Signed-off-by: Hans de Goede hdego...@redhat.com
I presume that adding GPIO support to SPL isn't a problem size wise?
---
board/sunxi/Kconfig| 26 ++
drivers/mmc/sunxi_mmc.c| 21
On Mon, 2014-10-06 at 19:57 +0200, Hans de Goede wrote:
None of the known sunxi devices actually use mmc1 routed through PH, where
as some devices do actually use mmc1 routed through PG, so change the routing
of mmc1 to PG. If in the future we encounter devices with mmc1 routed through
PH, we
On Mon, 2014-10-06 at 19:57 +0200, Hans de Goede wrote:
Enable the second sdcard slot found on some boards. Note that we do not
set CONFIG_MMC_SUNXI_SLOT_EXTRA for the SPL, as having it there is not useful,
Except for on the Mele-M3 where the second sdcard is an eMMC, from which the
device
On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
The Allwinner A23 SoC has reset controls like the A31 (sun6i).
The FIFO address is also the same as sun6i.
Re-use code added for sun6i.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Ian Campbell i...@hellion.org.uk
---
On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
The basic blocks of the A23 are similar to the A31 (sun6i). Re-use
sun6i code for initial clock, gpio, and uart setup.
Do I take it that sun8i is also in the same position wrt DRAM bring up
code not existing yet and there therefore being no
On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
From: Hans de Goede hdego...@redhat.com
The A31, A23 and later SoCs have an extra pin controller, called CPUs_PIO
or R_PIO, which handles pin banks L and beyond.
Does it also have enough space for 9 banks? Since you overlay a struct
On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
The prcm apb0 controls multiple modules. Allow specifying which
modules to enable clocks and de-assert resets so the function
can be reused.
How come this isn't actually called on sun6i?
(naughty of me not to notice this when it was
On Sat, 2014-10-11 at 17:11 +0100, Ian Campbell wrote:
On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
The prcm apb0 controls multiple modules. Allow specifying which
modules to enable clocks and de-assert resets so the function
can be reused.
How come this isn't actually called
On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
The A23 only has UART0 muxed with MMC0. Some of the boards we
encountered expose R_UART as a set of pads.
Add support for R_UART so we can have a console while using mmc.
I suppose R_UART is the h/w doc name. UARTR would fit the code
On Fri, Oct 10, 2014 at 08:48:53AM -0700, bruce bushby wrote:
So I'm guessing it's those sort of addresses that should now come
from DTS variables? ...are their specific structures that pass
DTS variables to a driver?
For the generic resources (clocks, addresses, interrupts, dma
channels,
On Monday, February 17, 2014 2:27:29 PM UTC-6, darius...@gmail.com wrote:
If you are interested I can send some working code for nrf24l01. I just mixed
all information above with my previous problems with SPI and i have got a
nrf24l01 connected to CB successfully communicating with RPi
Hi Marco,
I am interested in the code that makes spi work.
trying to get my nrf24l01 to work and coming from Arduino world
i thought it would be easier since you are working with full OS!
I was wrong.
thanks
On Monday, February 17, 2014 3:40:53 PM UTC-6, Marco Montesissa wrote:
HI Darius,
More details at http://linux-sunxi.org/MSI_Primo73
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
sys_config/a20/msi_primo73.fex | 1032
1 file changed, 1032 insertions(+)
create mode 100644 sys_config/a20/msi_primo73.fex
diff --git
More details at http://linux-sunxi.org/MSI_Primo81
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
sys_config/a31s/msi_primo81.fex | 1046 +++
1 file changed, 1046 insertions(+)
create mode 100644 sys_config/a31s/msi_primo81.fex
diff --git
On Sat, Oct 11, 2014 at 11:33 PM, Ian Campbell i...@hellion.org.uk wrote:
On Sat, 2014-10-04 at 20:37 +0800, Chen-Yu Tsai wrote:
+#else /* CONFIG_SUN6I || CONFIG_SUN8I || .. */
+ static const struct sunxi_wdog *wdog =
+ ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)-wdog;
+
+
On Sat, Oct 11, 2014 at 11:58 PM, Ian Campbell i...@hellion.org.uk wrote:
On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
The basic blocks of the A23 are similar to the A31 (sun6i). Re-use
sun6i code for initial clock, gpio, and uart setup.
Do I take it that sun8i is also in the same
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