在 2014年8月12日星期二 UTC+8下午11:20:16,anuroop kamu写道:
> Hi Miska, Thanks for that Doc
>
>
> I am still not able to visualize it fully. if this Tsc driver works well,
> which buffer/fifo will the data be available?
> Do I need to make a separate media player app to get this data? Or any
> default med
Hello Maxime,
On Tue, Feb 2, 2016 at 9:17 PM, Maxime Ripard
wrote:
> Hi,
>
> On Sun, Jan 31, 2016 at 09:20:56AM +0800, Vishnu Patekar wrote:
>> AHB1 on A83T is similar to ahb1 on A31, except parents are different.
>> clock index 0b1x is PLL6.
>>
>> Signed-off-by: Vishnu Patekar
>
> If the clock
Hello Wens,
On Tue, Feb 2, 2016 at 3:37 PM, Chen-Yu Tsai wrote:
>
> On Sun, Jan 31, 2016 at 9:21 AM, Vishnu Patekar
> wrote:
> > This patch adds support for Sinovoip BPI-M3 A83T based board.
> >
> > It has 2G LPDDR3, UART, ethernet, USB, HDMI, USB Sata, MIPI DSI,
> > mic, AP6212 Wifi, etc on i
On Wed, Feb 03, 2016 at 11:21:17PM +0100, Krzysztof Adamski wrote:
On Wed, Feb 03, 2016 at 01:35:34PM +0100, Maxime Ripard wrote:
Hi,
I'm not sure what you mean there. The fixed factor clocks only take a
single parent, and you provided two.
True, I that's actually some stupid leftover. As men
APB0 is bearly mentioned in H3 User Manual and it is only setup in the
Allwinners kernel dump for CIR. I have verified experimentally that the
gate for R_PIO exists and works, though. There are probably other gates
there but I don't know their order right now and I don't have access to
their periph
This patch series is extension of my original single patch with the same
subject. It adds support for R_PIO so that GPIO port L can be used in H3
based devices. It was tested on OrangePi PC where PL is connected amount
others to an onboard led, a switch, an IR receiver and some VCC
controllers.
Pa
This patch adds support for APB0 in H3. It seems to be compatible with
earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR,
etc).
Signed-off-by: Krzysztof Adamski
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
drivers/clk/sunxi/clk-simple-gates.c | 2 ++
H3 has additional PIO controller similar to what we can find on A23.
It's a 12 pin port, described in H3 Datasheet rev 1.1, pages 345-350.
Signed-off-by: Krzysztof Adamski
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
drivers/pinctrl/sunxi/Kconfig | 4 +
Add the corresponding device node for R_PIO on H3 to the dtsi. Support
for the controller was added in earlier commit.
Signed-off-by: Krzysztof Adamski
---
arch/arm/boot/dts/sun8i-h3.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm
sunxi_pmx_set accepts pin number and then calculates offset by
subtracting pin_base from it. sunxi_pinctrl_gpio_get, on the other hand,
gets offset so we have to convert it to pin number so we won't get
negative value in sunxi_pmx_set.
This was only used on A10 so far, where there is only one GPIO
On Wed, Feb 03, 2016 at 01:35:34PM +0100, Maxime Ripard wrote:
Hi,
On Tue, Feb 02, 2016 at 10:21:50PM +0100, Krzysztof Adamski wrote:
APB0 is bearly mentioned in H3 User Manual and it is only setup in the
Allwinners kernel dump for CIR. I have verified experimentally that the
gate for R_PIO exi
Hello everybody,
I’m currently building a project on top of an Olimex LIME A20 board.
On sunxi kernel 3.4, ethernet over USB OTG is working, but on vanilla kernel
4.x, nothing works.
Is there any standalone 3.4 patch available for USB OTG I can port to vanilla
4.x ?
I look into 3.4 git reposito
On Wed, Feb 03, 2016 at 02:19:31PM -0600, Rob Herring wrote:
> >> > +Required properties:
> >> > + - compatible: value must be one of:
> >> > +* allwinner,sun5i-a13-display-engine
> >> > + - allwinner,pipelines: list of phandle to the entry points of the
> >> > +pipelines (either to the f
On Sun, Jan 17, 2016 at 01:10:02AM +0800, Chen-Yu Tsai wrote:
> On Thu, Jan 14, 2016 at 11:24 PM, Maxime Ripard
> wrote:
> > The DRAM gates control whether the image / display devices on the SoC have
> > access to the DRAM clock or not.
> >
> > Enable it.
> >
> > Signed-off-by: Maxime Ripard
> >
Hi,
On Sun, Jan 17, 2016 at 01:06:07AM +0800, Chen-Yu Tsai wrote:
> > + compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
> > + reg = <0x01c20118 0x4>;
> > + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
> > +
Hi,
On Sun, Jan 17, 2016 at 12:36:20AM +0800, Chen-Yu Tsai wrote:
> Hi,
>
> On Thu, Jan 14, 2016 at 11:24 PM, Maxime Ripard
> wrote:
> > The TCON is a controller generating the timings to output videos signals,
> > acting like both a CRTC and an encoder.
> >
> > It has two channels depending on
On Sun, Jan 17, 2016 at 12:05:06AM +0800, Chen-Yu Tsai wrote:
> Hi,
>
> On Thu, Jan 14, 2016 at 11:24 PM, Maxime Ripard
> wrote:
> > The A10 SoCs and relatives have a PLL controller to drive the PLL3 and
> > PLL7, clocked from a 3MHz oscillator, that drives the display related
> > clocks (GPU, di
On Wed, Feb 3, 2016 at 1:59 PM, Maxime Ripard
wrote:
> Hi Rob,
>
> On Thu, Jan 14, 2016 at 09:15:15PM -0600, Rob Herring wrote:
>> On Thu, Jan 14, 2016 at 04:25:00PM +0100, Maxime Ripard wrote:
>> > The display pipeline of the Allwinner A10 is involving several loosely
>> > coupled components.
>>
On Sat, Jan 16, 2016 at 11:29:41PM +0800, Chen-Yu Tsai wrote:
> Hi,
>
> On Thu, Jan 14, 2016 at 11:24 PM, Maxime Ripard
> wrote:
> > The A10 SoCs and its relatives has a special clock controller to drive the
> > display engines (both frontend and backend), that have a lot in common with
> > the c
YouTube videos of
U.S. Congress money laundering hearing
of
Saudi Billionaire " Maan Al sanea"
with *bank of America*
and The owner of Saad Hospital and Schools
in the Eastern Province in *Saudi Arabia*
and the Chairman of the Board of Directors of Awal Bank in *Bahrain*
Wit
Hi Rob,
On Thu, Jan 14, 2016 at 09:15:15PM -0600, Rob Herring wrote:
> On Thu, Jan 14, 2016 at 04:25:00PM +0100, Maxime Ripard wrote:
> > The display pipeline of the Allwinner A10 is involving several loosely
> > coupled components.
> >
> > Add a documentation for the bindings.
> >
> > Signed-of
Hi there,
where is awusb kernel driver's primary git repository?
I've found it as a part of Livesuite git repository [1] and also as a part of
allwinner-tools.git.
Wiki page LiveSuit [3] mentions [1] as a git repository.
I think it would be nice to have it as a separate project, which would be u
Thierry
On Wed, Feb 3, 2016 at 6:53 AM, Thierry Reding wrote:
>> A) The software state here is the period and flags (AKA "inverted),
>> right? It does seem possible that you could apply the period and
>> flags while keeping the calculated bootup duty cycle percentage
>> (presuming that the PWM w
On Tue, Feb 02, 2016 at 06:27:39PM +0800, Chen-Yu Tsai wrote:
> The X-Powers AXP809 PMIC has a similar set of regulators as the AXP221,
> though a few LDOs were removed, and a new switch output added. Like the
> AXP221, AXP809 also has DC1SW and DC5LDO, which are internally chained
> to DCDC1 and D
On Mon, Jan 25, 2016 at 10:51:20AM -0800, Doug Anderson wrote:
> Hi,
>
> On Mon, Jan 25, 2016 at 9:08 AM, Thierry Reding
> wrote:
> > I really don't understand this design decision. I presume that the PWM
> > controlling this system-critical logic is driven by the SoC? So if the
> > regulator is
On Tue, Feb 02, 2016 at 10:21:51PM +0100, Krzysztof Adamski wrote:
> H3 has additional PIO controller similar to what we can find on A23.
> It's a 12 pin port, described in H3 Datasheet rev 1.1, pages 345-350.
>
> Signed-off-by: Krzysztof Adamski
Acked-by: Maxime Ripard
Thanks!
Maxime
--
Max
Hi,
On Tue, Feb 02, 2016 at 10:21:50PM +0100, Krzysztof Adamski wrote:
> APB0 is bearly mentioned in H3 User Manual and it is only setup in the
> Allwinners kernel dump for CIR. I have verified experimentally that the
> gate for R_PIO exists and works, though. There are probably other gates
> ther
On 2 February 2016 at 22:17, Maxime Ripard
wrote:
> Hi,
>
> It looks mostly good on my side, a few comments though.
>
> On Tue, Feb 02, 2016 at 03:49:54PM +0100, codekip...@gmail.com wrote:
>> +#ifdef CONFIG_PM
>> +static int sun4i_spdif_runtime_suspend(struct device *dev)
>> +{
>> + struct su
28 matches
Mail list logo