Hi,
You're veering dangerously close to troll territory, but I'll give you
one last response on this.
On Mon, Jul 5, 2021 at 10:18 AM B.R. Oake wrote:
>
> On Fri Jun 04 08:49:28 CEST 2021, Julian Calaby wrote:
> > While I completely sympathise with your points here, the
don't know the circumstances behind those cases.
Git's history is considered immutable once it makes it to an
"official" repository (generally one published publicly) so it's
likely they were oversights that weren't caught until it was too late.
Thanks,
--
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Email: julian.c
ret;
> +
> + val->intval &= !!(reg & AXP813_ACIN_PATH_SEL);
If we only check this bit if ACIN_AVAIL is set, then we don't need the
"&" in the "&=". (I'm assuming that val->intval is an int, not a bool,
otherwise this is t
eeds_mux;
> booldisable_strict_mode;
> - boolhas_io_bias_cfg;
> + int io_bias_cfg_variant;
Shouldn't we be defining this field using the enum rather than as an int?
Thanks,
--
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Email:
default 14779 if MACH_SUN8I_V3S
> default 3881979 if MACH_SUN8I_R40 || MACH_SUN50I_H6
Would it work if these were just re-ordered so the more specific ones
come first?
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-
[i])
> + cfg = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(i);
> + else
> + break;
> + }
> +
> + if (cfg == 0xff) {
> + dev_err(axp20x->dev, "unsuppor
be hard-coded
> to match the panel. That would work against having a generic bridge driver.
To me it seems logical that we'd model it as another step in the graph
between the DSI component and the panel. It's conceivable that some
other manufacturer will probably buy these for their panels
Hi Jernej,
On Sun, May 20, 2018 at 11:57 AM, Julian Calaby <julian.cal...@gmail.com> wrote:
> Hi Jernej,
>
> On Sun, May 20, 2018 at 4:31 AM, Jernej Skrabec <jernej.skra...@siol.net>
> wrote:
>> R40 display pipeline has a lot of possible configurations. HDMI can
}
> +
> +static int sun8i_r40_tcon_tv_set_mux_1(struct sun4i_tcon *tcon,
> + const struct drm_encoder *encoder)
> +{
> + return sun8i_r40_tcon_tv_set_mux(tcon, encoder, 1);
> +}
Are TCON-TOPs going to be a common thing in new SoCs from Allwi
+H3 and A64 HDMI PHY requires additional clocks:
>- pll-0: parent of phy clock
> + - pll-1: second possible phy clock parent (A64 only)
Maybe split this into two:
H3 HDMI PHY ...
- pll-0: ...
A64 HDMI PHY ...
- pll-0: ...
- pll-1: ...
At the moment a quick reading implies th
operty is present then the dai is
> + configured to extend the slot width to the
> + value specified. Min 8, Max 32.
> +
This sounds like something that would be useful for other I2S controllers.
Thanks,
--
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Hi Maxime,
On Tue, Feb 27, 2018 at 6:07 PM, Maxime Ripard
<maxime.rip...@bootlin.com> wrote:
> On Tue, Feb 27, 2018 at 01:29:27PM +1100, Julian Calaby wrote:
>> Hi Jernej,
>>
>> On Tue, Feb 27, 2018 at 3:27 AM, Jernej Škrabec <jernej.skra...@siol.net>
>> w
.net> 写到:
>> >Hi Julian,
>> >
>> >Dne nedelja, 25. februar 2018 ob 09:11:34 CET je Julian Calaby
>> >
>> >napisal(a):
>> >> Hi Jernej,
>> >>
>> >> On Sun, Feb 25, 2018 at 8:45 AM, Jernej Skrabec
>> >
>> &
Hi Icenowy,
On Sun, Feb 25, 2018 at 7:43 PM, Icenowy Zheng <icen...@aosc.io> wrote:
>
>
> 于 2018年2月25日 GMT+08:00 下午4:11:34, Julian Calaby <julian.cal...@gmail.com> 写到:
>>Hi Jernej,
>>
>>On Sun, Feb 25, 2018 at 8:45 AM, Jernej Skrabec
>><jernej
lease add the
necessary bits and pieces to the h2-plus DTSs too?
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To unsu
om the codec side of the chip, which we
> +* properly declare and reference in the devicetree and is
> +* not implemented in any driver right now.
> +* If the clock core looks for the parent of that second
> +* m
gt;>
>> >> [Trimmed lots of non-sunxi-specific mailing lists]
>> >>
>> >> Did support for this board ever get merged?
>> >
>> >It doesn't look like it did.
>>
>> Is there any problem in this patch now except the
>> absense of SP
, I'll try to shepherd this
and it's corresponding u-boot patch upstream.)
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s variant around for compatibility
with existing device trees?
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Hi Maxime,
On Wed, Jan 31, 2018 at 7:36 PM, Maxime Ripard
<maxime.rip...@free-electrons.com> wrote:
> Hi Julian,
>
> On Wed, Jan 31, 2018 at 07:29:13PM +1100, Julian Calaby wrote:
>> Hi Maxime,
>>
>> On Wed, Jan 31, 2018 at 7:21 PM, Maxime Ripard
>> &
ey can always disable the MMC env and
>> enable stuff at their likings, it's just the standard "make
>> .._defconfig; make" process that needs to be fixed with some band-aids
>> for now.
>
> I really don't want to go down the "let's fix each defconfig when
Hi Icenowy,
On Sat, Jan 20, 2018 at 2:10 PM, Icenowy Zheng <icen...@aosc.io> wrote:
>
>
> 于 2018年1月20日 GMT+08:00 上午11:06:40, Julian Calaby <julian.cal...@gmail.com> 写到:
>>Hi Icenowy,
>>
>>On Sat, Jan 20, 2018 at 10:17 AM, Icenowy Zheng <icen...@aosc.io>
gt; +menuconfig ARCH_SUNXI_V5
> + bool "Allwinner SoCs"
That name seems a little too generic. Maybe "Allwinner ARMv5 SoCs"?
Thanks,
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ONTROLLER
> select CLKSRC_MMIO
> select GENERIC_IRQ_CHIP
Shouldn't you remove all the common ARCH_SUNXI selects from ARCH_SUNXI_v7?
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#define AXP22X_CHRG_CTRL1_TGT_4_24V(3 << 5)
Should these be "alphabetical", i.e. AXP20X, AXP22X, AXP813?
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ELPER_NO_SCALING;
if (layer->mixer->cfg->scaler_mask & BIT(layer->id)) {
min_scale = 1;
max_scale = (1UL << 20) - 1;
}
However the compiler will probably sort it all out anyway, so it
probably doesn't matter that much, except for style.
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Email: juli
ds they are on, your
question appears to be WiFi related, so you'll be more likely to get a
useful answer on the linux-wireless list, which I've added to CC.
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..@csie.org>
Thanks!
FWIW this is:
Reviewed-by: Julian Calaby <julian.cal...@gmail.com>
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Hi Chen-Yu,
On Sat, Sep 30, 2017 at 3:58 PM, Chen-Yu Tsai <w...@csie.org> wrote:
> On Sat, Sep 30, 2017 at 1:35 PM, Julian Calaby <julian.cal...@gmail.com>
> wrote:
>> Hi Chen-Yu,
>>
>> On Fri, Sep 29, 2017 at 8:22 PM, Chen-Yu Tsai <w...@csie.org>
rs,
> which
> are only available in TCON0. Other than that, there's nothing else
> shared between
> the two TCONs. So there's no particular reason to look for TCON1 explicitly.
In that case: in the bizarre case where we're trying to use this mux
type and there is no TCON0, shouldn't we fail?
(Also, the c
compatible = "allwinner,sun50i-h5-de2-clk";
> +};
> +
This is what I get for reviewing before reading the full patch set.
Shouldn't this be rolled into the previous patch?
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e-cells = <1>;
> ranges;
>
> + display_clocks: clock@100 {
> + /* compatible is in per SoC .dtsi file */
I don't know device tree very well, but shouldn't this node be
disabled so that it doesn't do anything weird on H5? Or are n
; -#define CLK_PLL_VIDEO1_2X 16
>
> +/* The PLL_VIDEO0_2X is exported for HDMI */
PLL_VIDEO*1*_2X, right?
> /* The CPU clock is exported */
>
> #define CLK_AXI18
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_reg_ops *reg_ops = data->ops;
> + const u32 *prescaler_table = data->prescaler_table;
> u32 prd, dty, val, clk_gate;
> u64 clk_rate, div = 0;
> unsigned int prescaler = 0;
> @@ -319,6 +454,7 @@ static int sun4i_pwm_probe(struct platform_device *pdev
return PTR_ERR(nvmem);
>>
>> - randomness = kzalloc(sizeof(u8) * (size), GFP_KERNEL);
>> + randomness_size = max(size, SUNXI_SID_MAX_RANDOMNESS_SIZE);
>> + randomness = kzalloc(sizeof(u8) * (randomness_size), GFP_KERNEL);
>
> Why is that change needed?
Accordi
e some instructions on using
ESP-03 boards as an SDIO WiFi card on a Raspberry Pi:
https://hackaday.io/project/8678-rpi-wifi
This project eventually evolved into a RasPi hat, however the initial
instructions should be usable with any development board with exposed
SDIO lines by anyone who isn
Hi Chen-Yu,
On Sun, Aug 21, 2016 at 12:11 PM, Chen-Yu Tsai <w...@csie.org> wrote:
> The X-Powers AXP809 is a new PMIC that is paired with Allwinner's A80
> SoC, along with a master AXP809 PMIC.
The first "AXP809" should be "AXP806".
Thanks,
--
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TES;
>
> platform_set_drvdata(pdev, host);
>
> + if (of_device_is_compatible(pdev->dev.of_node,
> + "allwinner,sun6i-a31-spdif")) {
Given how much Allwinner likes to shuffle stuff around with each SoC
generation, would it make sense to add a f
mp;& i == AXP809_DCDC1))
> + (regulators == axp809_regulators && i == AXP809_DCDC1) ||
> + (regulators == axp813_regulators && i == AXP813_DCDC1))
Ditto.
> of_property_read_string(rdev->dev.of_node,
>
Hi Chen-Yu,
On Thu, Jul 28, 2016 at 1:22 PM, Chen-Yu Tsai <w...@csie.org> wrote:
> On Thu, Jul 28, 2016 at 11:20 AM, Julian Calaby <julian.cal...@gmail.com>
> wrote:
>> Hi Onno,
>>
>> On Thu, Jul 28, 2016 at 12:58 AM, Onno Kortmann <o...@gmx.net>
o we can set this for
boards we know have crystals?
(Also, is there equivalent functionality for sun6i-rtc?)
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"l
nd the
hardware itself is capable of receiving data from four analogue
cameras simultaneously, it probably can't encode them fast enough.
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to this binding:
1. clock delay - time from "boot" to clocks being enabled
2. reset delay - time from "boot" to resets being de-asserted
3. boot delay - time from "boot" until the mmc-pwrseq-simple driver
assumes the card is ready to be probed
Where the "boot" time is when t
t; no "module" in DT:nvram filename = brcm/brcmfmac43362-sdio.txt
> > "module=ap6210" in DT:nvram filename =
brcm/brcmfmac43362-ap6210.txt
>
> Just out of curiosity, what does "ap6210" exactly mean? I get that 43362
> is the chip id, but not ap6210. I
t;130>;
> + regulator-boot-on;
> + regulator-type = "voltage";
> +
> + gpios = <_pio 0 6 GPIO_ACTIVE_HIGH>;
> + states = <110 0x0
> + 130 0x1>;
> +
> + startu
--
> 4 files changed, 98 insertions(+), 22 deletions(-)
Shouldn't the .dtsi changes be in a separate patch?
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--
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t;130>;
> + regulator-boot-on;
> + regulator-type = "voltage";
> +
> + gpios = <_pio 0 6 GPIO_ACTIVE_HIGH>;
> + states = <110 0x0
> + 1300000 0x1>;
> +
> + start
Hi Maxime,
On Fri, Jun 17, 2016 at 4:58 PM, Maxime Ripard
<maxime.rip...@free-electrons.com> wrote:
> On Fri, Jun 17, 2016 at 03:58:44PM +1000, Julian Calaby wrote:
>> Hi Maxime,
>>
>> On Fri, Jun 17, 2016 at 3:41 PM, Maxime Ripard
>> <maxime.rip...@free-elect
't the presence of the TV encoder on the R8 (used for the composite
out on the CHIP) a difference between it and the regular A13? Is that
detectable? (However I can't find any reference to it in the
datasheet, so I'm kinda confused here.)
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Hi Michal,
On Tue, Jun 14, 2016 at 4:35 PM, Michal Suchanek <hramr...@gmail.com> wrote:
> Hello,
>
> On 14 June 2016 at 07:45, Julian Calaby <julian.cal...@gmail.com> wrote:
>> Hi Michal,
>>
>> On Tue, Jun 14, 2016 at 3:28 PM, Michal Suchanek <hramr...@g
Hi Michal,
On Tue, Jun 14, 2016 at 3:28 PM, Michal Suchanek <hramr...@gmail.com> wrote:
> On 14 June 2016 at 06:47, Julian Calaby <julian.cal...@gmail.com> wrote:
>> Hi Michal,
>>
>> On Tue, Jun 14, 2016 at 2:34 PM, Michal Suchanek <hramr...@gmail.com> wr
Hi Michal,
On Tue, Jun 14, 2016 at 2:40 PM, Michal Suchanek <hramr...@gmail.com> wrote:
> On 14 June 2016 at 01:45, Julian Calaby <julian.cal...@gmail.com> wrote:
>> Hi Michal,
>>
>> On Tue, Jun 14, 2016 at 3:46 AM, Michal Suchanek <hramr...@gmail.com> wr
Hi Michal,
On Tue, Jun 14, 2016 at 2:34 PM, Michal Suchanek <hramr...@gmail.com> wrote:
> Hello,
>
> On 14 June 2016 at 01:43, Julian Calaby <julian.cal...@gmail.com> wrote:
>> Hi Michal,
>>
>> On Tue, Jun 14, 2016 at 3:46 AM, Michal Suchanek <hramr...@
nterrupts = <11>;
> - clocks = <_gates 21>, <_clk>;
> +spi1: spi@01c69000 {
> + compatible = "allwinner,sun6i-a31-spi";
> + reg = <0x01c69000 0x1000>;
> + interrupts = <0 66 4>;
> + clocks = <_gates 21&
,
> + )) {
> + pr_err(", %s", str);
> + i++;
> + }
> + }
> + ret = -EINVAL;
> + goto er
0x1c
> #define SUNXI_FIFO_STA_RF_CNT_MASK 0x7f
My gut feeling on this is that we have a lot of cases of a definition
of a register offset, then definitions of the bits in that register
with that register encoded into the constant's name. You appear to be
throwing a lot of that informatio
enable-sdio-wakeup;
> +
> + brcmf: bcrmf@1 {
> + reg = <1>;
> + compatible = "brcm,bcm4329-fmac";
> + interrupt-parent = <>;
> + interrupts = <7 15 IRQ_TYPE_LEVEL_LOW>;
> + in
Hi Michal,
On Fri, May 27, 2016 at 3:05 PM, Michal Suchanek <hramr...@gmail.com> wrote:
> On 27 May 2016 at 04:05, Julian Calaby <julian.cal...@gmail.com> wrote:
>> Hi Michal,
>>
>> On Fri, May 27, 2016 at 5:25 AM, Michal Suchanek <hramr...@gmail.com>
o_jiffies(tx_time));
> + end = jiffies;
> if (!timeout) {
> + dev_warn(>dev,
> + "%s: timeout transferring %u bytes@%iHz for
> %i(%i)ms",
> +dev_name(>dev), tfr->len, tfr->speed_hz,
>
> @@ -30,5 +50,8 @@ axp209: pmic@34 {
> usb-power-supply: usb-power-supply {
>compatible = "x-powers,axp202-usb-power-supply";
> + vhold-enable = <0x01>;
> + vhold-set = <0x04>;
>
return -ENODEV;
> @@ -208,6 +309,11 @@ static int axp20x_usb_power_probe(struct
>if (IS_ERR(power->supply))
>return PTR_ERR(power->supply);
> +
> + /* read DT configurations parameters, if available */
> + for
your init cannot find a filesystem to mount. I don't
recognise the messages from init or the directories emitted so I can't
help.
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atus = "okay";
> +};
> +
I believe that the entries in these files should be sorted
alphabetically. You've also added an extra line after the block.
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;
> };
> +
> + can0_pins_a: can0@0 {
> + allwinner,pins = "PH20","PH21";
> + allwinner,function = "can";
> + allwinner,drive = ;
> +
If you're interested in adding support yourself, this is the place to
discuss that.
If you want something out-of-the-box right now then you need to speak
either to Allwinner themselves or the vendor of your device.
Thanks,
Julian Calaby
> thanks.
>
> ___
node)
> +{
> + sunxi_factors_clk_setup(node, _a83t_ahb1_data);
> +}
> +CLK_OF_DECLARE(sun8i_a83t_ahb1, "allwinner,sun8i-a83t-ahb1-clk",
> + sun8i_a83t_ahb1_clk_setup);
> +
> static void __init sun4i_apb1_clk_setup(struct device_node *node)
> {
>
coming from
> a gps.
>
>
>>
>> Have you tried to compile it?
>>
>
> Yes, otherwise we could have never confirmed that the irq's where on mux6
> for the PI ports.
I think Maxime is referring to the fact that your patch removes two
closing parenthesis when one wo
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>>> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>>> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>>> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARIS
1,7 @@ Required properties:
>"allwinner,sun9i-a80-r-pinctrl"
>"allwinner,sun8i-a83t-pinctrl"
>"allwinner,sun8i-h3-pinctrl"
> + "allwinner,sun8i-h3-r-pinctrl"
Shouldn't this change go in the patch that introduces the driver for
this pinctl
> +X-POWERS MULTIFUNCTION PMIC DEVICE DRIVERS
> +M: Chen-Yu Tsai <w...@csie.org>
> +L: linux-ker...@vger.kernel.org
> +S: Maintained
> +N: axp[128]
Should you list the files maintained and this list also?
> +
> X.25 NETWORK LAYER
> M: Andrew Hendry
Hi Joe,
On Wed, Feb 3, 2016 at 12:28 PM, Joe Perches <j...@perches.com> wrote:
> On Wed, 2016-02-03 at 11:19 +1100, Julian Calaby wrote:
>> On Tue, Feb 2, 2016 at 9:27 PM, Chen-Yu Tsai <w...@csie.org> wrote:
>> > Add an entry for X-Powers AXP family PMIC drivers and
onfigured. I'm not sure
your device tree based approach will be as user friendly in this
regard.
2. they list stuff we don't have a driver / hardware for yet
3. the policy on device-tree is to only include stuff we know is
working, which means we have a driver and hardware for that particular
th
I ports. This will help people
making cases for your board.
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WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +#include "sun4i-a10-mk802.dtsi"
> +
> +/ {
> + model = &q
int eccbyte)
> +{
> + if (eccbyte > 23)
> + return -ERANGE;
> +
> + return ((eccbyte / 6) * 16) + 1;
Are you sure this is correct? My reading of this is that we'd get 1
for eccbytes 0 through 5.
Would
((eccbyte / 6) * 16) + (eccbyte % 6) + 1
be more
er, headphones,
a radio and
my ears.
Note that because of missing capturing support I tested only the mixing,
for Mic, Line, and FM.
The patches are on top of
,
branch "sunxi/for-next".
Regards,
Danny
Danny (1):
b/sound/soc/sunxi/sun4i-codec.c | 153 +
Hi Oliver,
On Fri, Dec 4, 2015 at 9:57 AM, Julian Calaby <julian.cal...@gmail.com> wrote:
> Hi Oliver,
>
> On Fri, Dec 4, 2015 at 3:49 AM, Olliver Schinagl <oli...@schinagl.nl> wrote:
>> From: Olliver Schinagl <o.schin...@ultimaker.com>
>>
>> Commit
ccm =
> (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
>
> +#ifdef CONFIG_MACH_SUN7I
> + if (port > 4)
> +#else
> if (port > 2)
> +#endif
Should the number here be a #define somewhere, or even a parameter for
each version of this clock?
Thanks,
-
Hi Marcus,
On Fri, Nov 20, 2015 at 7:45 PM, Marcus Weseloh <mweselo...@gmail.com> wrote:
> Hi Julian,
>
> 2015-11-19 23:59 GMT+01:00 Julian Calaby <julian.cal...@gmail.com>:
>> Should you possibly hide the 3 clock periods from the user?
>>
>> I.e. they se
l to what they ask for.
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== 1 in the get functions when the non-shared
>variant gets called (this is optional but probably a good extra
>check)
>
> 3) Do the whole deassert_count thingy only when the shared bool is true
>
> 4) Make reset_control_reset fail (BUG_ON) if the shared bool is true
>
ve deasserted an initially asserted reset, a
>> reset_control_assert for one of them will silently fail.
>
> Then maybe we can just make it return an error when someone calls
> _assert or _reset on a reset line that has more than one user?
Just to set another cat amongst the pigeo
nsfer has to bounce through the CPU and
this was slow without the MMU for some reason. I'm also guessing that
enabling the MMU has moved the bottleneck elsewhere - possibly the USB
hardware.)
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Profile: http://www.google.com/profiles/jul
Hi Maxime,
On Thu, Nov 5, 2015 at 3:23 AM, Maxime Ripard
<maxime.rip...@free-electrons.com> wrote:
> Hi Julian,
>
> On Wed, Oct 28, 2015 at 10:12:09AM +1100, Julian Calaby wrote:
>> > + of_property_for_each_u32(node, "c
clk_parent = AHB2;
> + else if (index <= 63 || index >= 128)
> + clk_parent = AHB1;
> + else if (index >= 64 && index <= 95)
> + clk_parent = APB1;
> + else if (index >= 96 &&
= clk_name[i];
> - }
>
> base_name[i] = '\0';
> factors.name = base_name;
Thanks,
--
Julian Calaby
Email: julian.cal...@gmail.com
Profile: http://www.google.com/profiles/julian.calaby/
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Hi Boris,
On Fri, Oct 16, 2015 at 4:17 AM, Boris Brezillon
<boris.brezil...@free-electrons.com> wrote:
> Some MLC NANDs are sensible to repeated patterns and require data to be
Do you mean "sensitive" instead of "sensible"?
Thanks,
--
Julian Calaby
Email: ju
t;sensitive" instead of "sensible"?
Thanks,
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Email: julian.cal...@gmail.com
Profile: http://www.google.com/profiles/julian.calaby/
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gt; - AXP288 power management IC (PMIC).
> + If you say Y here you get support for the X-Powers AXP series I2C
> + based power management ICs (PMICs).
> This driver include only the core APIs. You have to select
> individual
> components
Maxime,
On Wed, Oct 7, 2015 at 3:17 AM, Maxime Ripard
<maxime.rip...@free-electrons.com> wrote:
> Hi,
>
> On Tue, Oct 06, 2015 at 12:15:38PM +1100, Julian Calaby wrote:
>> Hi Maxime,
>>
>> On Tue, Oct 6, 2015 at 1:23 AM, Maxime Ripard
>> <maxime.rip...@f
ators.dtsi"
> +
> +#include
> +#include
> +
> +/ {
> + model = "NextThing C.H.I.P.";
> + compatible = "nextthing,chip", "allwinner,sun5i-r8";
> +
> + aliases {
> + i2c0 =
> + i2c1 =
> +
enabling the ohci0 node be a separate patch?
Thanks,
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Julian Calaby
Email: julian.cal...@gmail.com
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tags instead:
>>>> Reviewed-by: Tom Rini <tr...@konsulko.com>
>>>
>>>
>>> This is in essence a partial sync with the kernel tree wrt the dts
>>> files, so no SPDX tags.
>>
>>
>> Really? I'd have sworn that we were doing that even on
written a good driver which is a few tweaks away from
being merged - which is something you should be very proud of. I see
drivers being submitted that have much more serious issues and that
prompt much more debate than yours has. (For instance I've seen some
changes on another mailing list go throug
that
someone's going to use the lack of DTSI as proof that we don't
support the R8 or try to use the tv encoder on an A13.
Thanks,
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Julian Calaby
Email: julian.cal...@gmail.com
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Hi Maxime,
On Tue, Aug 25, 2015 at 3:14 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Tue, Aug 25, 2015 at 10:24:51AM +1000, Julian Calaby wrote:
Hi Maxime,
On Tue, Aug 25, 2015 at 12:26 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Hi,
On Fri, Aug 21, 2015
Hi Maxime,
On Mon, Aug 3, 2015 at 7:34 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Mon, Aug 03, 2015 at 11:03:52AM +0200, Timo Sigurdsson wrote:
Hi again,
Julian Calaby schrieb am 03.08.2015 06:22:
My only real objection here is are there boards that can go down to
0.9v
Hi Chen-Yu,
On Mon, Aug 3, 2015 at 12:37 PM, Chen-Yu Tsai w...@csie.org wrote:
Hi,
On Mon, Aug 3, 2015 at 7:35 AM, Julian Calaby julian.cal...@gmail.com wrote:
Hi Timo,
On Mon, Aug 3, 2015 at 5:23 AM, Timo Sigurdsson
public_tim...@silentcreek.de wrote:
sun7i-a20.dtsi contains an cpufreq
?
(Alternatively, would it make sense to modify the code that uses this
to use frequencies with voltages specified that are lower than can be
supplied with the lowest voltage it can?)
Thanks,
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Julian Calaby
Email: julian.cal...@gmail.com
Profile: http://www.google.com/profiles/julian.calaby
Hi Henrik,
On Mon, Jun 29, 2015 at 10:33 AM, Henrik Nordström
hen...@henriknordstrom.net wrote:
fre 2015-06-26 klockan 01:12 +1000 skrev Julian Calaby:
It's obvious what is required:
1. Datasheets
2. Programming manuals
3. GPL compliant drivers
4. (L)GPL compliant userspace stuff
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