On 14-02-07 04:48 PM, Darren Hart wrote:
On 2/7/14, 13:37, Bruce Ashfield bruce.ashfi...@windriver.com wrote:
On 2/7/2014, 4:24 PM, Darren Hart wrote:
On 2/7/14, 13:16, Tom Zanussi tom.zanu...@intel.com wrote:
On Fri, 2014-02-07 at 12:53 -0800, Darren Hart wrote:
I'm working on adding
On 2/10/14, 8:41, Bruce Ashfield bruce.ashfi...@windriver.com wrote:
On 14-02-07 04:48 PM, Darren Hart wrote:
On 2/7/14, 13:37, Bruce Ashfield bruce.ashfi...@windriver.com wrote:
On 2/7/2014, 4:24 PM, Darren Hart wrote:
On 2/7/14, 13:16, Tom Zanussi tom.zanu...@intel.com wrote:
On Fri,
On 2/10/14, 5:08, rebecca.swee.fun.ch...@intel.com
rebecca.swee.fun.ch...@intel.com wrote:
From: Chang, Rebecca Swee Fun rebecca.swee.fun.ch...@intel.com
Remove PCI mode LPSS deivce configurations. These
configurations are moved into a patch in recipe layer
in order for Valley Island LPSS
On 2/6/14, 17:18, Darren Hart dvh...@linux.intel.com wrote:
This series does some fragment cleanup and adds the two new common BSPs
for the
meta-intel layer: intel-core2-32 and intel-corei7-64. These BSPs currently
include all the corresponding ARCH (32 or 64) BSP descriptions as well as
On Mon, Feb 10, 2014 at 5:47 PM, Darren Hart dvh...@linux.intel.com wrote:
On 2/6/14, 17:18, Darren Hart dvh...@linux.intel.com wrote:
This series does some fragment cleanup and adds the two new common BSPs
for the
meta-intel layer: intel-core2-32 and intel-corei7-64. These BSPs currently
-Original Message-
From: linux-yocto-boun...@yoctoproject.org [mailto:linux-yocto-
boun...@yoctoproject.org] On Behalf Of linux-yocto-
requ...@yoctoproject.org
Sent: Tuesday, February 11, 2014 2:53 AM
To: linux-yocto@yoctoproject.org
Subject: linux-yocto Digest, Vol 20, Issue 8
From: Chang, Rebecca Swee Fun rebecca.swee.fun.ch...@intel.com
Valley Island LPSS I/O device supports PCI and ACPI mode enumeration.
PCI mode configurations are moved into separate scc file for
enumeration mode switching. Mode switching is done in kernel recipe.
Signed-off-by: Chang, Rebecca
From: Chang, Rebecca Swee Fun rebecca.swee.fun.ch...@intel.com
Remove PCI mode LPSS deivce configurations. These
configurations are moved into a patch in recipe layer
in order for Valley Island LPSS devices to support both
ACPI mode and PCI mode enumeration.
Signed-off-by: Chang, Rebecca Swee
From: Chang, Rebecca Swee Fun rebecca.swee.fun.ch...@intel.com
Hi,
This is a pull request for an update on valleyisland-io
cfg and scc files.
Valley Island LPSS devices are supporting both ACPI and
PCI mode enumeration. In order for users to easily enable
ACPI mode enumeration for valleyisland
On 2/10/14, 16:21, Bruce Ashfield bruce.ashfi...@gmail.com wrote:
On Mon, Feb 10, 2014 at 5:47 PM, Darren Hart dvh...@linux.intel.com
wrote:
On 2/6/14, 17:18, Darren Hart dvh...@linux.intel.com wrote:
This series does some fragment cleanup and adds the two new common BSPs
for the
meta-intel
On 2/10/2014, 11:59 PM, Darren Hart wrote:
On 2/10/14, 16:21, Bruce Ashfield bruce.ashfi...@gmail.com wrote:
On Mon, Feb 10, 2014 at 5:47 PM, Darren Hart dvh...@linux.intel.com
wrote:
On 2/6/14, 17:18, Darren Hart dvh...@linux.intel.com wrote:
This series does some fragment cleanup and adds
On 2/10/14, 21:23, Bruce Ashfield bruce.ashfi...@windriver.com wrote:
On 2/10/2014, 11:59 PM, Darren Hart wrote:
On 2/10/14, 16:21, Bruce Ashfield bruce.ashfi...@gmail.com wrote:
On Mon, Feb 10, 2014 at 5:47 PM, Darren Hart dvh...@linux.intel.com
wrote:
On 2/6/14, 17:18, Darren Hart
On 2/11/2014, 12:24 AM, Darren Hart wrote:
On 2/10/14, 21:23, Bruce Ashfield bruce.ashfi...@windriver.com wrote:
On 2/10/2014, 11:59 PM, Darren Hart wrote:
On 2/10/14, 16:21, Bruce Ashfield bruce.ashfi...@gmail.com wrote:
On Mon, Feb 10, 2014 at 5:47 PM, Darren Hart dvh...@linux.intel.com
On 2/10/14, 21:45, Bruce Ashfield bruce.ashfi...@windriver.com wrote:
On 2/11/2014, 12:24 AM, Darren Hart wrote:
On 2/10/14, 21:23, Bruce Ashfield bruce.ashfi...@windriver.com
wrote:
On 2/10/2014, 11:59 PM, Darren Hart wrote:
On 2/10/14, 16:21, Bruce Ashfield bruce.ashfi...@gmail.com wrote:
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