From: Chang Rebecca Swee Fun rebecca.swee.fun.ch...@intel.com
Hi all,
This patch is to enable PCI mode enumeration for Valley Island LPSS
I/O devices. The I/O device drivers that can be PCI enumerated are:-
GPIO, I2C Designware, SPI, DW_DMAC.
Feature branch will be send out next. There will be
From: Chew, Chiau Ee chiau.ee.c...@intel.com
Allow CONFIG_X86_INTEL_LPSS to be set when ACPI
or PCI is set.
Signed-off-by: Chew, Chiau Ee chiau.ee.c...@intel.com
Signed-off-by: Maurice Petallo mauricex.r.peta...@intel.com
---
arch/x86/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1
From: Chang Rebecca Swee Fun rebecca.swee.fun.ch...@intel.com
Hi all,
This is the scenerio 1 that Boon Leong mentioned in the Feature Branch
planning email thread. This will be the feature branch that consists
of all patches that are queuing into 3.10 LTS/LTSI and also the so
called staging
From: Chang Rebecca Swee Fun rebecca.swee.fun.ch...@intel.com
This commit enables the following:
- setup clock tree for PCI mode SPI, DMA and PWM host
as the controller drivers require clock information during
device/driver probe
- register SPI slave
- fix device name string for clkdev
From: Chew, Chiau Ee chiau.ee.c...@intel.com
The pxa2xx pci glue layer only support CE4100 SPI port
by default. To add BYT SPI port support, we make it a
generic PCI glue layer by renaming ce4100_xxx to
pxa2xx_spi_xxx.
This commit is created in reference to Mika's commit
during kernel-3.5
From: Chew, Chiau Ee chiau.ee.c...@intel.com
BYT ACPI mode SPI not read/writing correctly at low speeds
using DMA mode. Fix the issue by changing DMA SRC_MSIZE and
DEST_MSIZE of SPI FIFO side from 16 to 32.
Signed-off-by: Chew, Chiau Ee chiau.ee.c...@intel.com
Signed-off-by: Maurice Petallo
From: Chew, Chiau Ee chiau.ee.c...@intel.com
This is to disable/enable DW_DMAC hw during late suspend/early resume.
Since DMA is providing service to other clients (eg: SPI, HSUART),
we need to ensure DMA suspends after the clients and resume
before the clients are active.
Signed-off-by: Chew,
From: Felipe Balbi ba...@ti.com
usb_gadget_set_state() will call sysfs_notify()
which might sleep. Some users might want to call
usb_gadget_set_state() from the very IRQ handler
which actually changes the gadget state.
Instead of having every UDC driver add their own
workqueue for such a simple
From: Mika Westerberg mika.westerb...@linux.intel.com
Intel Baytrail I2C controllers can be enumerated from PCI as well as from
ACPI. In order to support this add the Baytrail PCI IDs to the driver.
Signed-off-by: Mika Westerberg mika.westerb...@linux.intel.com
Signed-off-by: Wolfram Sang
From: Chew, Chiau Ee chiau.ee.c...@intel.com
Intel BayTrail LPSS consists of two PWM controllers which can
be enumerated from ACPI namespace. This change will cause
platform device objects to be created for Intel BayTrail PWM
controllers which will allow the pwm-lpss driver to bind to them
and
From: Mika Westerberg mika.westerb...@linux.intel.com
Add support for Intel Low Power I/O subsystem PWM controllers found on
Intel BayTrail SoC.
Signed-off-by: Mika Westerberg mika.westerb...@linux.intel.com
Signed-off-by: Chew, Kean Ho kean.ho.c...@intel.com
Signed-off-by: Chang, Rebecca Swee
From: Chew, Kean Ho kean.ho.c...@intel.com
BayTrail GPIO NORTH, SOUTH and SUS clusters use IRQ48,
49 and 50 respectively. On non-ACPI system, we need
to setup IOAPIC RTE for device that use interrupt
beyond IRQ23.
Signed-off-by: Chew, Kean Ho kean.ho.c...@intel.com
Signed-off-by: Chew, Chiau Ee
From: Seth Heasley seth.heas...@intel.com
This patch adds the i801 SMBus Controller DeviceIDs for the Intel Coleto Creek
PCH.
Signed-off-by: Seth Heasley seth.heas...@intel.com
Signed-off-by: Wolfram Sang w...@the-dreams.de
(cherry picked from commit f39901c1befa556bc91902516a3e2e46b4a8)
From: Chew, Chiau Ee chiau.ee.c...@intel.com
This is to disable/enable DW_DMAC hw during late suspend/early resume.
Since DMA is providing service to other clients (eg: SPI, HSUART),
we need to ensure DMA suspends after the clients and resume
before the clients are active.
Signed-off-by: Chew,
From: Mika Westerberg mika.westerb...@linux.intel.com
Intel Baytrail I2C controllers can be enumerated from PCI as well as from
ACPI. In order to support this add the Baytrail PCI IDs to the driver.
Signed-off-by: Mika Westerberg mika.westerb...@linux.intel.com
Signed-off-by: Wolfram Sang
From: Mika Westerberg mika.westerb...@linux.intel.com
Add support for Intel Low Power I/O subsystem PWM controllers found on
Intel BayTrail SoC.
Signed-off-by: Mika Westerberg mika.westerb...@linux.intel.com
Signed-off-by: Chew, Kean Ho kean.ho.c...@intel.com
Signed-off-by: Chang, Rebecca Swee
From: H Hartley Sweeten hartl...@visionengravers.com
Add a simple sysfs interface to the generic PWM framework.
/sys/class/pwm/
`-- pwmchipN/ for each PWM chip
|-- export (w/o) ask the kernel to export a PWM channel
|-- npwm(r/o) number of PWM
From: Adrian Hunter adrian.hun...@intel.com
If the SDHCI irq is shared with another device then the interrupt
handler can get called while SDHCI is runtime suspended. That is
harmless but the warning message is not useful so remove it. Also
returning IRQ_NONE is more appropriate.
From: Chew, Kean Ho kean.ho.c...@intel.com
The requested gpio pin must has the func_pin_mux field set
to GPIO function by BIOS/FW in advanced. Else, the gpio pin
request would fail. This is to ensure that we do not expose
any gpio pins which shall be used for alternate functions,
for eg: wakeup
From: Chew, Kean ho kean.ho.c...@intel.com
Add Device ID of Intel BayTrail SMBus Controller.
Signed-off-by: Chew, Kean ho kean.ho.c...@intel.com
Signed-off-by: Chew, Chiau Ee chiau.ee.c...@intel.com
Reviewed-by: Jean Delvare jdelv...@suse.de
Signed-off-by: Wolfram Sang w...@the-dreams.de
(cherry
From: Chang Rebecca Swee Fun rebecca.swee.fun.ch...@intel.com
This commit enables the following:
- setup clock tree for PCI mode SPI, DMA and PWM host
as the controller drivers require clock information during
device/driver probe
- register SPI slave
- fix device name string for clkdev
From: Chew, Chiau Ee chiau.ee.c...@intel.com
This will enable high speed baud rates namely 1M, 2M, 3M, and 4M
in Intel Baytrail Designware controller.
Signed-off-by: Chew, Chiau Ee chiau.ee.c...@intel.com
Signed-off-by: Maurice Petallo mauricex.r.peta...@intel.com
---
From: Chew, Chiau Ee chiau.ee.c...@intel.com
The pxa2xx pci glue layer only support CE4100 SPI port
by default. To add BYT SPI port support, we make it a
generic PCI glue layer by renaming ce4100_xxx to
pxa2xx_spi_xxx.
This commit is created in reference to Mika's commit
during kernel-3.5
From: Chew, Chiau Ee chiau.ee.c...@intel.com
Allow CONFIG_X86_INTEL_LPSS to be set when ACPI
or PCI is set.
Signed-off-by: Chew, Chiau Ee chiau.ee.c...@intel.com
Signed-off-by: Maurice Petallo mauricex.r.peta...@intel.com
---
arch/x86/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1
From: Chew, Kean Ho kean.ho.c...@intel.com
The requested gpio pin must has the func_pin_mux field set
to GPIO function by BIOS/FW in advanced. Else, the gpio pin
request would fail. This is to ensure that we do not expose
any gpio pins which shall be used for alternate functions,
for eg: wakeup
From: Chew, Kean Ho kean.ho.c...@intel.com
In to_irq() callback, we create the hwirq to linux irq
mapping for the requested GPIO pin. Hence, we unamp
the mapping when the gpio pin is being released.
Signed-off-by: Chew, Kean Ho kean.ho.c...@intel.com
Signed-off-by: Chew, Chiau Ee
From: Chew, Kean Ho kean.ho.c...@intel.com
BayTrail GPIO NORTH, SOUTH and SUS clusters use IRQ48,
49 and 50 respectively. On non-ACPI system, we need
to setup IOAPIC RTE for device that use interrupt
beyond IRQ23.
Signed-off-by: Chew, Kean Ho kean.ho.c...@intel.com
Signed-off-by: Chew, Chiau Ee
From: Chew, Kean Ho kean.ho.c...@intel.com
This is to cater the need for non-ACPI system whereby
a platform device has to be created in order to bind
with the BYT Pinctrl GPIO platform driver.
Signed-off-by: Chew, Kean Ho kean.ho.c...@intel.com
Signed-off-by: Chew, Chiau Ee
On 2014-05-22, 5:18 AM, rebecca.swee.fun.ch...@intel.com wrote:
From: Chang Rebecca Swee Fun rebecca.swee.fun.ch...@intel.com
Hi all,
This patch is to enable PCI mode enumeration for Valley Island LPSS
I/O devices. The I/O device drivers that can be PCI enumerated are:-
GPIO, I2C Designware,
Hi Bruce,
I have run a build test on the latest commits checked-in. The feature branch
was not merge in during build time. I think that the feature branch should be
branching out from commit
3e0a296fae952d8d93eb0f96566bf6d4a978c8ee:minnowboard-keys: Bind MinnowBoard
buttons to arrow keys
On 2014-05-22, 10:56 PM, Chang, Rebecca Swee Fun wrote:
Hi Bruce,
I have run a build test on the latest commits checked-in. The feature branch
was not merge in during build time. I think that the feature branch should be
branching out from commit
On 2014-05-22, 11:04 PM, Bruce Ashfield wrote:
On 2014-05-22, 10:56 PM, Chang, Rebecca Swee Fun wrote:
Hi Bruce,
I have run a build test on the latest commits checked-in. The feature
branch was not merge in during build time. I think that the feature
branch should be branching out from commit
So however you got a merge conflict. Your tree wasn't up to date.
I do not encounter any merge conflicts, is just that the branches is not
merging. By checking my build, I notice that the valleyisland-io-1.0 branch
has
the same HEAD of standard/base (which means I don't see any I/O
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