This patch is for llvm-gcc to make it emit ashr (arithmetic shift right)
and lshr (logical shift right) instructions. It needs to be applied to
llvm-gcc after the SHR.patch is applied to LLVM.
Reid.
Index: gcc/llvm-convert.cpp
===
Changes in directory llvm/lib/CodeGen:
AsmPrinter.cpp updated: 1.115 - 1.116
---
Log message:
Add a printSetLabel that takes two id's.
---
Diffs of the changes: (+13 -0)
AsmPrinter.cpp | 13 +
1 files changed, 13 insertions(+)
Index: llvm/lib/CodeGen/AsmPrinter.cpp
diff -u
Changes in directory llvm/lib/Target/ARM:
ARMAsmPrinter.cpp updated: 1.25 - 1.26
---
Log message:
print null values in bss
---
Diffs of the changes: (+4 -2)
ARMAsmPrinter.cpp |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/ARM/ARMAsmPrinter.cpp
Changes in directory llvm/docs:
ReleaseNotes.html updated: 1.362 - 1.363
---
Log message:
Partial update for Release 1.9
---
Diffs of the changes: (+25 -59)
ReleaseNotes.html | 84 --
1 files changed, 25 insertions(+), 59 deletions(-)
Changes in directory llvm/test/Regression/Transforms/GlobalOpt:
2006-11-01-ShrinkGlobalPhiCrash.ll added (r1.1)
---
Log message:
new testcase that crashes global opt, reduced from chomp
---
Diffs of the changes: (+33 -0)
2006-11-01-ShrinkGlobalPhiCrash.ll | 33
Changes in directory llvm/lib/Transforms/IPO:
GlobalOpt.cpp updated: 1.69 - 1.70
---
Log message:
Fix GlobalOpt/2006-11-01-ShrinkGlobalPhiCrash.ll and McGill/chomp
---
Diffs of the changes: (+14 -8)
GlobalOpt.cpp | 22 ++
1 files changed, 14 insertions(+), 8
Changes in directory llvm/test/Regression/Transforms/ScalarRepl:
phinodepromote.ll updated: 1.2 - 1.3
---
Log message:
extra pass is required now
---
Diffs of the changes: (+1 -1)
phinodepromote.ll |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index:
Changes in directory llvm/lib/CodeGen:
BranchFolding.cpp updated: 1.29 - 1.30
---
Log message:
give branch folding a simple heuristic to decide which block to split so that
it inserts an uncond branch where it is less likely to cause a problem. This
fixes some perf issues on ppc.
---
Diffs
Changes in directory llvm/lib/Analysis:
ScalarEvolution.cpp updated: 1.55 - 1.56
---
Log message:
Make ScalarEvolution actually use a ZeroExtend expression instead of
having SCZeroExtendExpr be equivalent to SCTruncate
---
Diffs of the changes: (+2 -2)
ScalarEvolution.cpp |4 ++--
1
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAGRRList.cpp updated: 1.15 - 1.16
---
Log message:
CopyFromReg starts a live range so its use should not be considered a floater.
---
Diffs of the changes: (+1 -1)
ScheduleDAGRRList.cpp |2 +-
1 files changed, 1 insertion(+),
Changes in directory llvm/lib/Transforms/Scalar:
CondPropagate.cpp updated: 1.6 - 1.7
---
Log message:
Handle PHINode with only one incoming value.
This fixes http://llvm.org/bugs/show_bug.cgi?id=979
---
Diffs of the changes: (+9 -5)
CondPropagate.cpp | 14 +-
1 files
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAGRRList.cpp updated: 1.16 - 1.17
---
Log message:
Clean up.
---
Diffs of the changes: (+11 -5)
ScheduleDAGRRList.cpp | 16 +++-
1 files changed, 11 insertions(+), 5 deletions(-)
Index:
Changes in directory llvm/include/llvm/Target:
TargetInstrInfo.h updated: 1.100 - 1.101
---
Log message:
Added getTiedToSrcOperand() to check for two-address'ness.
---
Diffs of the changes: (+5 -1)
TargetInstrInfo.h |6 +-
1 files changed, 5 insertions(+), 1 deletion(-)
Index:
Changes in directory llvm/lib/Target:
TargetInstrInfo.cpp updated: 1.19 - 1.20
---
Log message:
Added getTiedToSrcOperand() to check for two-address'ness.
---
Diffs of the changes: (+12 -0)
TargetInstrInfo.cpp | 12
1 files changed, 12 insertions(+)
Index:
Changes in directory llvm/utils/TableGen:
CodeGenTarget.cpp updated: 1.70 - 1.71
---
Log message:
Tied-to constraint must be op_with_larger_idx = op_with_smaller_idx or else
throw an exception.
---
Diffs of the changes: (+3 -0)
CodeGenTarget.cpp |3 +++
1 files changed, 3
Changes in directory llvm/lib/CodeGen:
RegAllocSimple.cpp updated: 1.74 - 1.75
TwoAddressInstructionPass.cpp updated: 1.38 - 1.39
VirtRegMap.cpp updated: 1.76 - 1.77
---
Log message:
Two-address instructions no longer have to be A := A op C. Now any pair of dest
/ src operands can be tied
Changes in directory llvm/lib/Transforms/Scalar:
CondPropagate.cpp updated: 1.7 - 1.8
---
Log message:
There can be more than one PHINode at the start of the block.
---
Diffs of the changes: (+4 -5)
CondPropagate.cpp |9 -
1 files changed, 4 insertions(+), 5 deletions(-)
On Oct 31, 2006, at 3:01 PM, Reid Spencer wrote:
Chris,
Here's the patch for conversion of Rem - [USF]Rem instructions.
Please
review at your earliest convenience. This passes dejagnu and llvm-test
suites. I've reviewed and modified this patch to make it as simple to
review as
Changes in directory llvm/include/llvm/Target:
TargetInstrInfo.h updated: 1.101 - 1.102
---
Log message:
Rename
---
Diffs of the changes: (+2 -2)
TargetInstrInfo.h |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/include/llvm/Target/TargetInstrInfo.h
diff -u
Changes in directory llvm/lib/Target:
TargetInstrInfo.cpp updated: 1.20 - 1.21
---
Log message:
Rename
---
Diffs of the changes: (+3 -1)
TargetInstrInfo.cpp |4 +++-
1 files changed, 3 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/TargetInstrInfo.cpp
diff -u
Changes in directory llvm/lib/CodeGen:
RegAllocSimple.cpp updated: 1.75 - 1.76
VirtRegMap.cpp updated: 1.77 - 1.78
---
Log message:
Rename
---
Diffs of the changes: (+2 -2)
RegAllocSimple.cpp |2 +-
VirtRegMap.cpp |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
Index:
On Wed, 2006-11-01 at 15:13 -0800, Chris Lattner wrote:
On Oct 31, 2006, at 3:01 PM, Reid Spencer wrote:
Chris,
Here's the patch for conversion of Rem - [USF]Rem instructions.
Please
review at your earliest convenience. This passes dejagnu and llvm-test
suites. I've reviewed and
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.312 - 1.313
---
Log message:
Allow the getRegForInlineAsmConstraint method to return a register class with
no fixes physreg. Treat this as permission to use any register in the register
class. When this
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.216 - 1.217
PPCISelLowering.h updated: 1.53 - 1.54
---
Log message:
Implement the getRegForInlineAsmConstraint method for PPC. With recent
sdisel changes, this eliminates a ton of copies around common inline asms.
Changes in directory llvm/include/llvm/Target:
TargetLowering.h updated: 1.83 - 1.84
---
Log message:
generalize this api
---
Diffs of the changes: (+8 -2)
TargetLowering.h | 10 --
1 files changed, 8 insertions(+), 2 deletions(-)
Index:
Changes in directory llvm/test/Regression/CodeGen/PowerPC:
inlineasm-copy.ll added (r1.1)
---
Log message:
new testcase
---
Diffs of the changes: (+14 -0)
inlineasm-copy.ll | 14 ++
1 files changed, 14 insertions(+)
Index:
Changes in directory llvm/include/llvm/Support:
PatternMatch.h updated: 1.10 - 1.11
---
Log message:
For PR950: http://llvm.org/PR950 :
Replace the REM instruction with UREM, SREM and FREM.
---
Diffs of the changes: (+14 -2)
PatternMatch.h | 16 ++--
1 files changed, 14
Changes in directory llvm/lib/ExecutionEngine/Interpreter:
Execution.cpp updated: 1.143 - 1.144
---
Log message:
For PR950: http://llvm.org/PR950 :
Replace the REM instruction with UREM, SREM and FREM.
---
Diffs of the changes: (+50 -12)
Execution.cpp | 62
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.313 - 1.314
---
Log message:
For PR950: http://llvm.org/PR950 :
Replace the REM instruction with UREM, SREM and FREM.
---
Diffs of the changes: (+4 -8)
SelectionDAGISel.cpp | 12
1 files
Changes in directory llvm/lib/Target/CBackend:
Writer.cpp updated: 1.276 - 1.277
---
Log message:
For PR950: http://llvm.org/PR950 :
Replace the REM instruction with UREM, SREM and FREM.
---
Diffs of the changes: (+28 -10)
Writer.cpp | 38 --
1 files
Changes in directory llvm/lib/VMCore:
ConstantFolding.cpp updated: 1.95 - 1.96
Constants.cpp updated: 1.168 - 1.169
Instruction.cpp updated: 1.55 - 1.56
Instructions.cpp updated: 1.44 - 1.45
---
Log message:
For PR950: http://llvm.org/PR950 :
Replace the REM instruction with UREM, SREM and
Changes in directory llvm/docs:
LangRef.html updated: 1.159 - 1.160
---
Log message:
For PR950: http://llvm.org/PR950 :
Replace the REM instruction with UREM, SREM and FREM.
---
Diffs of the changes: (+57 -13)
LangRef.html | 70 ---
Changes in directory llvm/lib/Analysis:
ScalarEvolution.cpp updated: 1.56 - 1.57
---
Log message:
For PR950: http://llvm.org/PR950 :
Replace the REM instruction with UREM, SREM and FREM.
---
Diffs of the changes: (+1 -1)
ScalarEvolution.cpp |2 +-
1 files changed, 1 insertion(+), 1
Changes in directory llvm/lib/AsmParser:
Lexer.l updated: 1.80 - 1.81
llvmAsmParser.y updated: 1.271 - 1.272
---
Log message:
For PR950: http://llvm.org/PR950 :
Replace the REM instruction with UREM, SREM and FREM.
---
Diffs of the changes: (+19 -8)
Lexer.l |5 -
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.533 - 1.534
PredicateSimplifier.cpp updated: 1.30 - 1.31
Reassociate.cpp updated: 1.64 - 1.65
---
Log message:
For PR950: http://llvm.org/PR950 :
Replace the REM instruction with UREM, SREM and FREM.
---
Changes in directory llvm/projects/Stacker/lib/compiler:
StackerCompiler.cpp updated: 1.20 - 1.21
---
Log message:
For PR950: http://llvm.org/PR950 :
Replace the REM instruction with UREM, SREM and FREM.
---
Diffs of the changes: (+1 -1)
StackerCompiler.cpp |2 +-
1 files changed, 1
Changes in directory llvm/include/llvm:
Constants.h updated: 1.92 - 1.93
Instruction.def updated: 1.20 - 1.21
---
Log message:
For PR950: http://llvm.org/PR950 :
Replace the REM instruction with UREM, SREM and FREM.
---
Diffs of the changes: (+44 -40)
Constants.h |4 ++
Changes in directory llvm/tools/llvm2cpp:
CppWriter.cpp updated: 1.18 - 1.19
---
Log message:
For PR950: http://llvm.org/PR950 :
Replace the REM instruction with UREM, SREM and FREM.
---
Diffs of the changes: (+9 -3)
CppWriter.cpp | 12 +---
1 files changed, 9 insertions(+), 3
Changes in directory llvm/lib/Bytecode/Reader:
Reader.cpp updated: 1.200 - 1.201
---
Log message:
For PR950: http://llvm.org/PR950 :
Replace the REM instruction with UREM, SREM and FREM.
---
Diffs of the changes: (+13 -8)
Reader.cpp | 21 +
1 files changed, 13
Changes in directory llvm/lib/Target/Alpha:
AlphaISelLowering.cpp updated: 1.71 - 1.72
AlphaInstrInfo.td updated: 1.133 - 1.134
---
Log message:
fix 2006-11-01-vastart.ll
---
Diffs of the changes: (+5 -3)
AlphaISelLowering.cpp |2 +-
AlphaInstrInfo.td |6 --
2 files
Changes in directory llvm/test/Regression/CodeGen/Alpha:
2006-11-01-vastart.ll added (r1.1)
---
Log message:
a regression :(
---
Diffs of the changes: (+18 -0)
2006-11-01-vastart.ll | 18 ++
1 files changed, 18 insertions(+)
Index:
Jim all
The attached patch should now be applied to llvm-gcc because the
corresponding REM patch for LLVM has been applied to CVS. This should
show up in llvm-gcc subversion repository in the next 24 hours. If you
can't wait that long and you're updating to LLVM CVS Head, apply it to
your
Changes in directory llvm/test:
TestRunner.sh updated: 1.12 - 1.13
---
Log message:
Add some documentation about the arguments.
---
Diffs of the changes: (+3 -0)
TestRunner.sh |3 +++
1 files changed, 3 insertions(+)
Index: llvm/test/TestRunner.sh
diff -u
I've applied this. Thanks!
Evan
On Nov 1, 2006, at 7:18 PM, Reid Spencer wrote:
Jim all
The attached patch should now be applied to llvm-gcc because the
corresponding REM patch for LLVM has been applied to CVS. This should
show up in llvm-gcc subversion repository in the next 24 hours. If
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