On Saturday, August 09, 2014 01:18:57 AM Ilia Mirkin wrote:
On Fri, Aug 8, 2014 at 10:10 PM, EdB edb+m...@sigluy.net wrote:
---
src/gallium/state_trackers/clover/api/program.cpp | 3 +++
src/gallium/state_trackers/clover/core/program.cpp | 8
---
src/gallium/state_trackers/clover/api/program.cpp | 4
src/gallium/state_trackers/clover/core/program.cpp | 8
src/gallium/state_trackers/clover/core/program.hpp | 1 +
3 files changed, 13 insertions(+)
diff --git a/src/gallium/state_trackers/clover/api/program.cpp
On Tuesday 04 March 2014, 02:08:58, Marek Olšák wrote:
Could you please do this without changing u_upload_mgr? You can still
use u_upload_alloc to allocate buffer memory in the driver and the map
buffer read/write flags are not important with persistent coherent
buffer mappings anyway.
Since
Acked-by: Marek Olšák marek.ol...@amd.com
Marek
On Sat, Aug 9, 2014 at 7:52 AM, Ilia Mirkin imir...@alum.mit.edu wrote:
So... can I get a review on this? It's the last bit needed for ARB_gs5
(well, except for the actual setting of the extension bit to 1)
The only additional change I have in
You can try to do the allocation of the staging buffer with
pipe_buffer_create instead of u_upload_mgr. You can also use
u_suballocator, which is like a stripped out version of u_upload_mgr.
You would need another instance of u_upload_mgr anyway, because we'd
like to continue using
On closer look, it looks to me like it wouldn't be all that difficult to
make proper sampler array dcls (as you apparently get them quite easily
from glsl) which is really my only problem with it but it's not really
all that important so
Reviewed-by: Roland Scheidegger srol...@vmware.com
Am
On Sat, Aug 9, 2014 at 10:14 AM, Roland Scheidegger srol...@vmware.com wrote:
On closer look, it looks to me like it wouldn't be all that difficult to
make proper sampler array dcls (as you apparently get them quite easily
If you can briefly outline how you think that should be done, I'd be
Am 09.08.2014 16:33, schrieb Ilia Mirkin:
On Sat, Aug 9, 2014 at 10:14 AM, Roland Scheidegger srol...@vmware.com
wrote:
On closer look, it looks to me like it wouldn't be all that difficult to
make proper sampler array dcls (as you apparently get them quite easily
If you can briefly
On Sat, Aug 9, 2014 at 11:12 AM, Roland Scheidegger srol...@vmware.com wrote:
Am 09.08.2014 16:33, schrieb Ilia Mirkin:
On Sat, Aug 9, 2014 at 10:14 AM, Roland Scheidegger srol...@vmware.com
wrote:
On closer look, it looks to me like it wouldn't be all that difficult to
make proper sampler
The lower_vertex_id pass converts uses of the gl_VertexID system value
to the gl_BaseVertex and gl_VertexIDMESA system values. Since
gl_VertexID is no longer accessed, it would not be considered active.
Of course, it should be, since the shader uses gl_VertexID.
v2: Move the var-name
pipe-loader.h will include Xlib.h when HAVE_PIPE_LOADER_XLIB is set in the
build.
---
src/gallium/state_trackers/gbm/Makefile.am | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/state_trackers/gbm/Makefile.am
b/src/gallium/state_trackers/gbm/Makefile.am
index 4d9f3fe..50995b3
On 08/09/2014 10:54 AM, Kenneth Graunke wrote:
The lower_vertex_id pass converts uses of the gl_VertexID system value
to the gl_BaseVertex and gl_VertexIDMESA system values. Since
gl_VertexID is no longer accessed, it would not be considered active.
Of course, it should be, since the shader
I realize it hasn't even been a week yet, but my remaining 2 weeks until
my sabbatical have just filled up, so if anyone needs me to rework this,
the sooner you let me know the better.
On Mon, Aug 04, 2014 at 12:24:00PM -0700, Ben Widawsky wrote:
The patch commit messages and comments within the
On Monday, August 04, 2014 12:24:01 PM Ben Widawsky wrote:
While working in this part of the code I had a great deal of trouble
understanding what it was trying to do, and matching it with the spec.
(mostly due bad wording in the PRM). To help future people, I've cleaned
up the wording and
On Monday, August 04, 2014 12:24:04 PM Ben Widawsky wrote:
On GEN8, a change in scissor state does not effect anything for the
clipper/sf hardware state. The hardware will always do the right thing
once the viewport extents are programmed. We can therefore remove the
unecessary state emission.
On Monday, August 04, 2014 12:24:03 PM Ben Widawsky wrote:
The goal of guardband clipping is to try to avoid 3d clipping because it
is an expensive operation. When guardband clipping is disabled, all
geometry that intersects the viewport is to the FF 3d clipper. Objects
On Monday, August 04, 2014 12:24:02 PM Ben Widawsky wrote:
Viewport extents are a 3rd rectangle that defines which pixels get
discarded as part of the rasterization process. This can potentially
improve performance by reducing cache usage, and freeing up PS cycles.
I'm not sure about cache
On Thu, Aug 7, 2014 at 4:06 PM, Alex Deucher alexdeuc...@gmail.com wrote:
On Wed, Aug 6, 2014 at 5:49 PM, Marek Olšák mar...@gmail.com wrote:
From: Marek Olšák marek.ol...@amd.com
R600-R700 don't support virtual memory.
For consistency, it might be nice to use gpu_address here as well, but
Hi Bruno,
Sorry, I fixed the warnings by myself before I saw your patch.
Marek
On Thu, Aug 7, 2014 at 12:07 PM, Bruno Jiménez brunoji...@gmail.com wrote:
I have followed the following convention:
- Positions in the pool are now 'int' (start_in_dw and related)
- Sizes are 'unsigned'
From: Marek Olšák marek.ol...@amd.com
Point util_memcpy_cpu_to_le32 to a buffer storage directly.
---
src/gallium/drivers/radeonsi/si_descriptors.c | 15 +++
1 file changed, 3 insertions(+), 12 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c
On Sat, Aug 09, 2014 at 12:07:58PM -0700, Ben Widawsky wrote:
I realize it hasn't even been a week yet, but my remaining 2 weeks until
my sabbatical have just filled up, so if anyone needs me to rework this,
the sooner you let me know the better.
Hi Ken. Thanks a lot for reviewing it. I meant
The last big piece of ARB_gpu_shader5!
This series adds support for using dynamically uniform expressions
in sampler array indexing, as required by ARB_gpu_shader5. Gen7 is
supported (including Haswell's high samplers). Gen8 support would
be a straightforward addition for someone who has access
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/glsl/ast_array_index.cpp | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/glsl/ast_array_index.cpp b/src/glsl/ast_array_index.cpp
index 50f9987..f8dca80 100644
--- a/src/glsl/ast_array_index.cpp
+++
If the array index is not a constant expression, the existing support
will assume a zero offset (giving us the sampler index of the base of
the array).
For dynamically uniform indexing of sampler arrays, we need both that
and the indexing expression.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
For now, assume that the addressed sampler can be in any of the
16-sampler banks. If we preserved range information this far, we
could avoid emitting these instructions if the sampler were known
to be contained within one bank.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 52 +++-
1 file changed, 51 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index
---
src/mesa/drivers/dri/i965/brw_vec4.h | 2 +-
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 53 +++---
2 files changed, 49 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
b/src/mesa/drivers/dri/i965/brw_vec4.h
index
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 47 +---
1 file changed, 25 insertions(+), 22 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_eu.h | 5
src/mesa/drivers/dri/i965/brw_eu_emit.c | 35
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 17 +---
3 files changed, 41 insertions(+), 16
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 52 +-
1 file changed, 51 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs.h | 4 +-
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 60
2 files changed, 55 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 17 +
1 file changed, 1 insertion(+), 16 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 47 ++
1 file changed, 25 insertions(+), 22 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index
On Saturday, August 09, 2014 06:15:34 PM Ben Widawsky wrote:
On Sat, Aug 09, 2014 at 12:07:58PM -0700, Ben Widawsky wrote:
I realize it hasn't even been a week yet, but my remaining 2 weeks until
my sabbatical have just filled up, so if anyone needs me to rework this,
the sooner you let me
The ARB_gpu_shader5 extension is made up of a lot of small sub-parts.
Instead of adding PIPE_CAP's for each of these, just rely on the GLSL
version reported by the pipe driver. The remaining extensions lend
themselves naturally to being checked through a single CAP.
Signed-off-by: Ilia Mirkin
On 10.08.2014 06:54, Marek Olšák wrote:
From: Marek Olšák marek.ol...@amd.com
Point util_memcpy_cpu_to_le32 to a buffer storage directly.
---
src/gallium/drivers/radeonsi/si_descriptors.c | 15 +++
1 file changed, 3 insertions(+), 12 deletions(-)
diff --git
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
docs/GL3.txt | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/docs/GL3.txt b/docs/GL3.txt
index 65facf5..29535ec 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -94,18 +94,18 @@ GL 4.0, GLSL 4.00:
Broadwell is going to use the brw_eu_emit.c code soon. We want to get
the fake MRF handling and URB HWord channel mask handling.
We don't need the CMP thread switch workaround, though.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 4 ++--
1
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 0a66d0c..9d7b4a5 100644
---
When we combine the Gen4-7 and Gen8+ generators, we'll need to handle
half float packing/unpacking functions somehow. The Gen8+ generator
code today just emulates the behavior of the Gen7 F32TO16/F16TO32
instructions, including the align16 mode bugs.
Rather than messing with
Broadwell adds UIP on ELSE instructions.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index
Until now, it's been off implicitly: we never call the compactor
function. When we merge the generators, we'll start calling it, so we
should make it do nothing.
Matt will enable instruction compaction properly later.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
[Applies on top of the dynamically uniform UBO indexing and sampler
indexing series sent to the list recently]
All the pieces are now in place for ARB_gpu_shader5 on
Ivybridge/Baytrail/Haswell, and Broadwell is close.
___
mesa-dev mailing list
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 038bfc6..822c73c 100644
---
Hello,
This is a series of preparatory work for getting Broadwell to use the
brw_eu_emit.c code generator rather than gen8_generator. The hope is
to drop the separate Gen8+ code completely. We couldn't do this
originally because the old code was centered around a struct describing
the Gen4-7
Different generations of hardware measure jump distances in different
units. Previously, every function that needed to set a jump target open
coded this scaling, or made a hardcoded assumption (i.e. just used 2).
Most functions start with the number of instructions to jump, and scale
up to the
See gen8_generator::CMP().
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 8
1 file changed, 8 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 5e14ba5..33684d4 100644
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
docs/relnotes/10.3.html | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/docs/relnotes/10.3.html b/docs/relnotes/10.3.html
index f023ca6..c237601 100644
--- a/docs/relnotes/10.3.html
+++ b/docs/relnotes/10.3.html
@@ -44,21
It has Gen6+ knowledge baked in, and indeed is only called for Gen6+,
but it wasn't immediately obvious that this was the case.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/intel_extensions.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index 4ee8636..04a47af 100644
---
Broadwell measures jump distances in bytes, so we need to scale by 16.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
Requires GLSL 1.50 or higher, which we only support in the core profile.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/main/extensions.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/main/extensions.c b/src/mesa/main/extensions.c
index 9ac8377..7a9214e
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 2e11eca..214ff0a 100644
---
+ if (align16) {
+ /* Emulate the Gen7 zeroing bug (see comments in vec4_visitor's
+ * emit_pack_half_2x16 method.)
+ */
+ brw_MOV(p, retype(dst, BRW_REGISTER_TYPE_UD), brw_imm_ud(0u));
+ }
+ return brw_MOV(p, retype(dst,
For the series:
Reviewed-by: Chris Forbes chr...@ijw.co.nz
On Sun, Aug 10, 2014 at 9:28 AM, Kenneth Graunke kenn...@whitecape.org wrote:
Hello,
This is a series of preparatory work for getting Broadwell to use the
brw_eu_emit.c code generator rather than gen8_generator. The hope is
to drop
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