On Mon, Aug 19, 2019 at 11:25:38PM +0200, Lionel Landwerlin wrote:
> On 19/08/2019 21:28, Rafael Antognolli wrote:
> > This param is only available starting on kernel 4.16. Use a default
> > value of 0 if it is not found instead.
>
>
> I trace the p
This commit might also need a:
Fixes: 96e1c945f2b ("i965: Move device info initialization to common
code")
On Mon, Aug 19, 2019 at 12:28:55PM -0700, Rafael Antognolli wrote:
> This param is only available starting on kernel 4.16. Use a default
> value of 0 if
This param is only available starting on kernel 4.16. Use a default
value of 0 if it is not found instead.
Cc: Jordan Justen
Cc: Mark Janes
---
src/intel/dev/gen_device_info.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/dev/gen_device_info.c
14, 2019 at 5:45 PM Rafael Antognolli
>
> wrote:
>
> I failed to initialize it on the other cases in GEN11 and it was causing
> a segfault when going through anv_DestroyDevice, if compiled with
> valgrind.
>
> Fixes: 7bc022b4bbc ("anv/g
I failed to initialize it on the other cases in GEN11 and it was causing
a segfault when going through anv_DestroyDevice, if compiled with
valgrind.
Fixes: 7bc022b4bbc ("anv/gen11: Emit SLICE_HASH_TABLE when pipes are
unbalanced.)
---
src/intel/vulkan/genX_state.c | 4 ++--
1
On Tue, Aug 13, 2019 at 05:50:30PM +0200, Mauro Rossi wrote:
> Instead of "genX_bits.h" use "genxml/genX_bits.h"
> as already done in other similar cases
>
> Besides being more correct, it also fixes building error in Android.
Ugh, sorry for that.
Reviewed
On Wed, Apr 17, 2019 at 09:04:09AM -0700, Kenneth Graunke wrote:
> On Wednesday, April 17, 2019 7:16:28 AM PDT Topi Pohjolainen wrote:
> > From: Rafael Antognolli
> >
> > Fixes MCS fast clear gpu hangs with Vulkan CTS on ICL in CI.
> >
> > CC: Anuj Phogat
&g
Depth fast clears were unrestricted, meaning they were enabled on every
hardware generation. However, gen11+ requires some extra code to make it
work properly.
---
src/gallium/drivers/iris/iris_clear.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/gallium/drivers/iris/iris_clear.c
It seems pretty useless nowadays.
---
src/mesa/drivers/dri/i965/brw_blorp.c | 36 +--
1 file changed, 12 insertions(+), 24 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 97a5f6a9937..e09a8cef762 100644
---
On Tue, Mar 05, 2019 at 07:50:24PM +, Chris Wilson wrote:
> Quoting Rafael Antognolli (2019-03-05 19:33:03)
> > On Tue, Mar 05, 2019 at 09:40:20AM +, Chris Wilson wrote:
> > > Not all commands support being preempted as they execute, and for those
> > >
ves.
>
> Cc: Jari Tahvanainen ,
> Cc: Rafael Antognolli
> Cc: Kenneth Graunke
> ---
> Always double check before you hit send.
> ---
> src/mesa/drivers/dri/i965/brw_defines.h | 1 +
> src/mesa/drivers/dri/i965/brw_draw.c| 7 +++
> 2 files changed, 8 insert
On Tue, Feb 05, 2019 at 12:09:45PM +, Emil Velikov wrote:
> From: Emil Velikov
>
> Cc: Rafael Antognolli
> Cc: Jason Ekstrand
> Cc: Dylan Baker
> Fixes: 927ba12b53c ("anv/tests: Adding test for the state_pool padding.")
> Signed-off-by: Emil Velikov
Move the pln emul code to the fs_visitor, so we get some optimizations
that don't happen at the fs_generator level, mainly better scheduling.
One big caveat of this change is that we don't use NF types and the
accumulator anymore, but apparently we don't need the extra precision.
Accessing bo->map and then pool->center_bo_offset without a lock is
racy. One way of avoiding such race condition is to store the bo->map +
center_bo_offset into pool->map at the time the block pool is growing,
which happens within a lock.
v2: Only set pool->map if not using softpin (Jason).
v3:
On Wed, Jan 23, 2019 at 06:08:50PM -0600, Jason Ekstrand wrote:
> On Wed, Jan 23, 2019 at 5:26 PM Rafael Antognolli
>
> wrote:
>
> Accessing bo->map and then pool->center_bo_offset without a lock is
> racy. One way of avoiding such race condition
Accessing bo->map and then pool->center_bo_offset without a lock is
racy. One way of avoiding such race condition is to store the bo->map +
center_bo_offset into pool->map at the time the block pool is growing,
which happens within a lock.
v2: Only set pool->map if not using softpin (Jason).
Cc:
Accessing bo->map and then pool->center_bo_offset without a lock is
racy. One way of avoiding such race condition is to store the bo->map +
center_bo_offset into pool->map at the time the block pool is growing,
which happens within a lock.
Cc: Jason Ekstrand
Reported-by: Ian Romanick
Bugzilla:
Reviewed-by: Rafael Antognolli
On Fri, Jan 18, 2019 at 05:01:58PM +, Lionel Landwerlin wrote:
> Doesn't save us a great deal of lines but at least they get decoded in
> aubinators.
>
> Signed-off-by: Lionel Landwerlin
> ---
> src/intel/genxml/gen10.xml | 2 ++
&
the details of how, though.
Anyway, this looks better, and I assume it doesn't break anything.
Reviewed-by: Rafael Antognolli
> Fixes: 92eb5bbc68d7 "intel/blorp: Only copy clear color when doing..."
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107728
> Cc: Rafael
On Wed, Oct 31, 2018 at 04:27:31PM -0700, Kenneth Graunke wrote:
> On Wednesday, October 31, 2018 11:15:28 AM PDT Rafael Antognolli wrote:
> > On Tue, Oct 30, 2018 at 04:32:54PM -0700, Kenneth Graunke wrote:
> > > On Monday, October 29, 2018 10:19:54 AM PDT Rafael Antognolli
On Mon, Dec 10, 2018 at 01:49:43PM -0600, Jason Ekstrand wrote:
> On Fri, Dec 7, 2018 at 6:06 PM Rafael Antognolli
> wrote:
>
> We now have multiple BOs in the block pool, but sometimes we still
> reference only the first one in some instructions, and use relative
>
e missing some flushes in the states allocated in
anv_shader_bin_create(). I added them there and apparently I don't need
this patch anymore.
> On Fri, Dec 7, 2018 at 6:06 PM Rafael Antognolli
> wrote:
>
> TODO: This is just flushing the entire dynamic states on every execbuf.
On Mon, Dec 10, 2018 at 11:10:02PM -0600, Jason Ekstrand wrote:
>
>
> On Mon, Dec 10, 2018 at 5:48 PM Rafael Antognolli
>
> wrote:
>
> On Mon, Dec 10, 2018 at 04:56:40PM -0600, Jason Ekstrand wrote:
> > On Fri, Dec 7, 2018 at 6:06 PM Rafael Antogn
On Mon, Dec 10, 2018 at 04:56:40PM -0600, Jason Ekstrand wrote:
> On Fri, Dec 7, 2018 at 6:06 PM Rafael Antognolli
> wrote:
>
> This commit tries to rework the code that split and returns chunks back
> to the state pool, while still keeping the same logic.
>
>
On Mon, Dec 10, 2018 at 12:45:00PM -0600, Jason Ekstrand wrote:
> On Fri, Dec 7, 2018 at 6:06 PM Rafael Antognolli
> wrote:
>
> We will need specially the anv_block_pool_map, to find the
> map relative to some BO that is not at the start of the block pool.
> --
We now have multiple BOs in the block pool, but sometimes we still
reference only the first one in some instructions, and use relative
offsets in others. So we must be sure to add all the BOs from the block
pool to the validation list when submitting commands.
---
Add a structure to hold anv_states. This table will initially be used to
recicle anv_states, instead of relying on a linked list implemented in
GPU memory. Later it could be used so that all anv_states just point to
the content of this struct, instead of making copies of anv_states
everywhere.
If softpin is supported, create new BOs for the required size and add the
respective BO maps. The other main change of this commit is that
anv_block_pool_map() now returns the map for the BO that the given
offset is part of. So there's no block_pool->map access anymore (when
softpin is used.
---
Usage of anv_state_table_add is really annoying, see comment on the
previous commit.
---
src/intel/vulkan/anv_allocator.c | 96 +---
src/intel/vulkan/anv_private.h | 4 +-
2 files changed, 67 insertions(+), 33 deletions(-)
diff --git
So far we use only one BO (the last one created) in the block pool. When
we switch to not use the userptr API, we will need multiple BOs. So add
code now to store multiple BOs in the block pool.
This has several implications, the main one being that we can't use
pool->map as before. For that
---
src/intel/vulkan/anv_allocator.c | 32 ++--
src/intel/vulkan/anv_private.h | 2 +-
2 files changed, 19 insertions(+), 15 deletions(-)
diff --git a/src/intel/vulkan/anv_allocator.c b/src/intel/vulkan/anv_allocator.c
index 5f0458afd77..2171a97970b 100644
---
Change block_pool->bo to be a pointer, and update its usage everywhere.
This makes it simpler to switch it later to a list of BOs.
---
src/intel/vulkan/anv_allocator.c | 31 +++---
src/intel/vulkan/anv_batch_chain.c | 8
src/intel/vulkan/anv_blorp.c | 2
TODO: This is just flushing the entire dynamic states on every execbuf.
Maybe it's too much. However, in theory we should be already flushing
the states as needed, but I think we didn't hit any bug due to the
coherence implied by userptr.
---
src/intel/vulkan/anv_batch_chain.c | 4
1 file
This commit tries to rework the code that split and returns chunks back
to the state pool, while still keeping the same logic.
The original code would get a chunk larger than we need and split it
into pool->block_size. Then it would return all but the first one, and
would split that first one
We will need specially the anv_block_pool_map, to find the
map relative to some BO that is not at the start of the block pool.
---
src/intel/vulkan/anv_allocator.c | 23 ---
src/intel/vulkan/anv_batch_chain.c | 5 +++--
src/intel/vulkan/anv_private.h | 7 +++
It's possible that we still have some space left in the block pool, but
we try to allocate a state larger than that state. This means such state
would start somewhere within the range of the old block_pool, and end
after that range, within the range of the new size.
That's fine when we use
They won't be true anymore once we add support for multiple BOs with
non-userptr.
---
src/intel/vulkan/genX_gpu_memcpy.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/src/intel/vulkan/genX_gpu_memcpy.c
b/src/intel/vulkan/genX_gpu_memcpy.c
index 1bee1c6dc17..e20179fa675 100644
---
Maybe we should already rename anv_free_list2 -> anv_free_list since the
old one is gone.
---
src/intel/vulkan/anv_allocator.c | 55
src/intel/vulkan/anv_private.h | 11 ---
2 files changed, 66 deletions(-)
diff --git a/src/intel/vulkan/anv_allocator.c
The test was checking whether -1 was smaller than an unsigned int, which
is always false. So it was exiting early and never running until the
end, since it would reach the condition (thread_max == -1).
However, just fixing that is not enough. The test is currently getting
the highest block on
new tests for
some new cases we have now), but the series seems reasonable imho to
start getting some review already.
Cc: Jason Ekstrand
Rafael Antognolli (14):
anv/tests: Fix block_pool_no_free test.
anv/allocator: Add anv_state_table.
anv/allocator: Use anv_state_table on anv_state_
On Tue, Oct 30, 2018 at 04:32:54PM -0700, Kenneth Graunke wrote:
> On Monday, October 29, 2018 10:19:54 AM PDT Rafael Antognolli wrote:
> > Gen9 hardware requires some workarounds to disable preemption depending
> > on the type of primitive being emitted.
> >
> > We imp
On Mon, Oct 29, 2018 at 05:29:10PM +, Chris Wilson wrote:
> Quoting Rafael Antognolli (2018-10-29 17:19:53)
> > +void
> > +brw_enable_obj_preemption(struct brw_context *brw, bool enable)
> > +{
> > + const struct gen_device_info *devinfo = >screen->devinfo;
Set bit when initializing context.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_context.h | 2 ++
src/mesa/drivers/dri/i965/brw_defines.h | 5
src/mesa/drivers/dri/i965/brw_state.h| 3 ++-
src/mesa/drivers/dri/i965/brw_state_upload.c | 25
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen10.xml | 8
src/intel/genxml/gen11.xml | 8
src/intel/genxml/gen9.xml | 8
3 files changed, 24 insertions(+)
diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml
index abd5da297d6..acded759335
Re-sending the series, this time adding preemption support only to i965,
since We still don't have vulkan tests for this.
The proposed piglit test for this series can be found here:
https://gitlab.freedesktop.org/rantogno/piglit/commits/review/context_preemption_v2
Cc: Kenneth Graunke
Rafael
ignore blorp. The only primitive it emits is
3DPRIM_RECTLIST, and since it's not listed in the workarounds, we can
safely leave preemption enabled when it happens. Or it will be disabled
by a previous 3DPRIMITIVE, which should be fine too.
Signed-off-by: Rafael Antognolli
Cc: Kenneth Graunke
On Wed, Oct 17, 2018 at 06:08:34PM +0300, Danylo Piliaiev wrote:
> Signed-off-by: Danylo Piliaiev
> ---
> src/intel/tools/intel_sanitize_gpu.c | 38 +++-
> 1 file changed, 20 insertions(+), 18 deletions(-)
>
> diff --git a/src/intel/tools/intel_sanitize_gpu.c
>
uld be fine.
As an extra thing, I think the test could additionally check that
everything rendered correctly (check some colors from the framebuffer).
Anyway, just some ideas.
Thanks,
Rafael
> Regards,
> Andrii.
> On Mon, Oct 8, 2018 at 11:46 PM Rafael Antognolli
>
> wrote:
On Wed, Oct 10, 2018 at 05:00:33PM -0700, Jordan Justen wrote:
> On 2018-10-10 14:38:23, Rafael Antognolli wrote:
> > On Wed, Oct 10, 2018 at 02:04:11PM -0700, Jordan Justen wrote:
> > > On 2018-10-10 13:45:13, Rafael Antognolli wrote:
> > > > On Wed, Oct 10, 20
ISL_AUX_USAGE_NONE happens to be the same as "false", but let's do the
right thing and use the enum.
v2: fix intel_miptree_finish_depth too (Caio)
Reviewed-by: Dylan Baker
Reviewed-by: Caio Marcelo de Oliveira Filho
Reviewed-by: Jason Ekstrand
---
I just added the finish_depth() fix in the
On Wed, Oct 10, 2018 at 02:04:11PM -0700, Jordan Justen wrote:
> On 2018-10-10 13:45:13, Rafael Antognolli wrote:
> > On Wed, Oct 10, 2018 at 01:39:25PM -0700, Jordan Justen wrote:
> > > Ref: 263b584d5e4 "i965/skl: Emit extra zeros in STATE_BASE_ADDRESS on
> >
OUT_BATCH(0);
>}
> + if (devinfo->gen >= 10) {
> + OUT_BATCH(1);
> + OUT_BATCH(0);
> + OUT_BATCH(0);
> + }
Reviewed-by: Rafael Antognolli
>ADVANCE_BATCH();
> } else if (devinfo->gen >= 6) {
>
On Wed, Oct 10, 2018 at 01:39:25PM -0700, Jordan Justen wrote:
> Ref: 263b584d5e4 "i965/skl: Emit extra zeros in STATE_BASE_ADDRESS on
> Skylake."
> Signed-off-by: Jordan Justen
> ---
> src/intel/vulkan/genX_cmd_buffer.c | 12
> 1 file changed, 12 insertions(+)
>
> diff --git
Please ignore this patch, Jordan's version is the correct one.
On Wed, Oct 10, 2018 at 01:30:52PM -0700, Rafael Antognolli wrote:
> Starting in gen11, we have 3 more dwords used for Bindless Sampler State
> pointer and size.
>
> Cc: Anuj Phogat
>
> ---
> src/
Starting in gen11, we have 3 more dwords used for Bindless Sampler State
pointer and size.
Cc: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_misc_state.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
ISL_AUX_USAGE_NONE happens to be the same as "false", but let's do the
right thing and use the enum.
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
On Tue, Oct 02, 2018 at 07:16:01PM +0300, asimiklit.w...@gmail.com wrote:
> From: Andrii Simiklit
>
> I guess that when we calculating the width0, height0, depth0
> to use for function 'intel_miptree_create' we need to consider
> the 'base level' like it is done in the
On Wed, Aug 08, 2018 at 11:11:11PM +0100, Lionel Landwerlin wrote:
> On 08/08/18 20:07, Rafael Antognolli wrote:
> > On Tue, Aug 07, 2018 at 06:35:18PM +0100, Lionel Landwerlin wrote:
> > > When we map a PPGTT buffer into a continous address space of aubinator
> > > t
Hopefully it's a little more descriptive, and more accurate.
Cc: Lionel Landwerlin
---
src/intel/tools/aub_write.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/tools/aub_write.c b/src/intel/tools/aub_write.c
index e92bdaf5ed4..5d59b4ef28a 100644
---
It looks like we can't rely on the simulator to always translate virtual
addresses to physical ones correctly. So let's use physical everywhere.
Since our current GGTT maps virtual to physical addresses in a 1:1 way,
no further changes are required.
Additionally, we have other address spaces not
On Tue, Aug 14, 2018 at 03:36:18PM +0100, Lionel Landwerlin wrote:
> On 14/08/18 12:55, asimiklit.work wrote:
> > Hi Lionel,
> > > Hi Andrii,
> > >
> > > Again sorry, I don't think this is the right fix.
> > > I'm sending another patch to fix the parsing of
> > > MI_BATCH_BUFFER_START which seems
else so it seemed reasonable to check for that, considering we
can return -1, but I agree that printing "unknown instruction" would be
better.
> -
> Lionel
>
>
> On 10/08/18 16:48, Rafael Antognolli wrote:
> > On Thu, Aug 09, 2018 at 03:00:30PM +0300, andrey simikli
FFE0U and it looks like unexpected behavior for
> me:
> iter_group_offset_bits(iter, iter->group_iter + 1) < 0xFFE0U;
That's fine, I think the original commit message is good enough to
understand this change. Feel free to add this extra bit too if you want,
but I don't think it's n
t; + char label[40];
> + snprintf(label, sizeof(label), "%s: ", stage_names[s]);
> + draw_list->AddText(alloc_pos, ImGui::GetColorU32(ImGuiCol_Text),
> label);
> +
> + float r, g, b;
> + bool hovered;
> +
> + /* U
I'm not that familiar with this code yet, so take this review with a
grain of salt, but it looks good to me.
Reviewed-by: Rafael Antognolli
Just a few comments below but nothing really important.
On Tue, Aug 07, 2018 at 06:35:21PM +0100, Lionel Landwerlin wrote:
> Signed-off-by: Lio
On Tue, Aug 07, 2018 at 06:35:18PM +0100, Lionel Landwerlin wrote:
> When we map a PPGTT buffer into a continous address space of aubinator
> to be able to inspect it, we currently add it to the list of BOs to
> unmap once we're finished. An optimization we can apply it to look up
> that list
Reviewed-by: Rafael Antognolli
On Tue, Aug 07, 2018 at 06:35:16PM +0100, Lionel Landwerlin wrote:
> Signed-off-by: Lionel Landwerlin
> ---
> src/intel/tools/meson.build | 14 --
> 1 file changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/src/intel/tools
On Tue, Aug 07, 2018 at 06:35:13PM +0100, Lionel Landwerlin wrote:
> v2: Add helper to make iterators more readable (Rafael)
> Fix rev iterator bug (Rafael)
>
> Signed-off-by: Lionel Landwerlin
Reviewed-by: Rafael Antognolli
> ---
> src/u
On Tue, Aug 07, 2018 at 06:35:20PM +0100, Lionel Landwerlin wrote:
> A graphical user interface version of aubinator.
> Allows you to :
>
>- simultaneously look at multiple points in the aub file (using all
> the goodness of the existing decoding in aubinator)
>
>- edit an aub file
and 14 are:
Acked-by: Rafael Antognolli
On Thu, Aug 02, 2018 at 10:39:25AM +0100, Lionel Landwerlin wrote:
> A graphical user interface version of aubinator.
> Allows you to :
>
>- simultaneously look at multiple points in the aub file (using all
> the goodness of the ex
Ugh, I just replied with the whole message without cutting it out, so in
case it doesn't reach the ML, this is what I wanted to say:
On Mon, Aug 06, 2018 at 11:19:20AM -0700, Rafael Antognolli wrote:
> I would change the commit summary line to make it clear we are importing
> imgui code, i
urn page ?
> + (struct gen_batch_decode_bo) { .map = page->data, .addr =
> page->phys_addr, .size = 4096 } :
Looks like we are starting to use gen_batch_decode_bo as a generic
address pointer now (to both physical, virtual or aub data memory), so
maybe at some point we might wan
This also looks like a harmless and useful refactory.
Reviewed-by: Rafael Antognolli
On Thu, Aug 02, 2018 at 10:39:21AM +0100, Lionel Landwerlin wrote:
> Signed-off-by: Lionel Landwerlin
> ---
> src/intel/tools/aub_mem.c | 391
> src
Reviewed-by: Rafael Antognolli
On Thu, Aug 02, 2018 at 10:39:22AM +0100, Lionel Landwerlin wrote:
> ---
> src/intel/tools/aub_write.h | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/src/intel/tools/aub_write.h b/src/intel/tools/aub_write.h
> index b42167
On Thu, Aug 02, 2018 at 10:39:20AM +0100, Lionel Landwerlin wrote:
> Signed-off-by: Lionel Landwerlin
> ---
> src/util/rb_tree.h | 36
> 1 file changed, 36 insertions(+)
>
> diff --git a/src/util/rb_tree.h b/src/util/rb_tree.h
> index
Looks like no functional change, and it's needed by the ui tool, so
Reviewed-by: Rafael Antognolli
On Thu, Aug 02, 2018 at 10:39:19AM +0100, Lionel Landwerlin wrote:
> Signed-off-by: Lionel Landwerlin
> ---
> src/intel/tools/aub_read.c | 307 ++
>
On Thu, Aug 02, 2018 at 10:39:13AM +0100, Lionel Landwerlin wrote:
> Up to now we've been lucky that the buffer returned was always exactly
> at the address we requested.
Looks like this needs to land, even if the rest of the series doesn't.
Reviewed-by: Rafael Antognolli
> Fixes: 144
On Mon, Jul 30, 2018 at 04:28:37PM +0100, Lionel Landwerlin wrote:
> Gen10+ has an additional bit in MI_BATCH_BUFFER_END to signal the end
> of the context image.
Cool, I see you are also adding a couple missing commands and noops into
the gen10+ contexts.
Reviewed-by: Rafael Antognolli
Hi Vadym,
Ken and Ian explained a bit the situation on this one to me, and it
looks like neither of them are really against this patch. So unless
someone else raise any concern, I'll ack and push the patch later today.
Thanks for fixing this.
Rafael
On Thu, Jul 26, 2018 at 04:04:29PM +0300,
onfiguration through a temporary file that is
> deleted once the command line passes to intel_dump_gpu has exited.
Nice, I noticed this weird behavior too, thanks for fixing.
Reviewed-by: Rafael Antognolli
> Signed-off-by: Lionel Landwerlin
> ---
> src/intel/tools/intel_dump_gpu
t;
> Suggested-by: Rafael Antognolli
> Signed-off-by: Lionel Landwerlin
Reviewed-by: Rafael Antognolli
> ---
> src/intel/tools/intel_dump_gpu.in | 19 ---
> 1 file changed, 16 insertions(+), 3 deletions(-)
>
> diff --git a/src/intel/tools/in
I was thinking about the patch. I didn't look deeply into the one that
removes the command execution stuff, but for the rest of the series,
Acked-by: Rafael Antognolli
Sorry for being ambiguous :P
On Thu, Jul 19, 2018 at 10:12:57AM +0100, Lionel Landwerlin wrote:
> Was that for the wh
On Thu, Jul 19, 2018 at 10:14:32AM +0100, Lionel Landwerlin wrote:
> On 18/07/18 21:58, Rafael Antognolli wrote:
> > On Wed, Jul 18, 2018 at 06:21:32PM +0100, Lionel Landwerlin wrote:
> > > Signed-off-by: Lionel Landwerlin
> > > ---
> > >
On Wed, Jul 18, 2018 at 06:21:32PM +0100, Lionel Landwerlin wrote:
> Signed-off-by: Lionel Landwerlin
> ---
> src/intel/tools/aub_write.c | 45 ++---
> 1 file changed, 32 insertions(+), 13 deletions(-)
>
> diff --git a/src/intel/tools/aub_write.c
Reviewed-by: Rafael Antognolli
On Thu, Jul 12, 2018 at 11:46:12AM -0700, Eric Anholt wrote:
> ---
> src/intel/tools/intel_dump_gpu.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/src/intel/tools/intel_dump_gpu.c
> b/src/intel/tools/intel_dump_gpu.c
&g
Using -vv will increase the verbosity, by printing the ppgtt mappings as
they get written into the aub file.
Cc: Lionel Landwerlin
---
src/intel/tools/intel_dump_gpu.c | 25 -
src/intel/tools/intel_dump_gpu.in | 6 ++
2 files changed, 30 insertions(+), 1
Reviewed-by: Rafael Antognolli
On Fri, Jul 06, 2018 at 11:02:05AM +0100, Lionel Landwerlin wrote:
> We were not properly writing page tables when the virtual address
> range spans multiple subtrees of the tables.
>
> Signed-off-by: Lionel Landwerlin
> ---
> src/intel/tool
Patches 14-16 are
Reviewed-by: Rafael Antognolli
On Thu, Jun 21, 2018 at 05:29:13PM +0100, Lionel Landwerlin wrote:
> Signed-off-by: Lionel Landwerlin
> ---
> src/intel/dev/gen_device_info.c | 47 ++---
> src/intel/dev/gen_device_info.h | 5
>
to help explain this patch. Assuming
those comments make sense and are correct, this patch is
Reviewed-by: Rafael Antognolli
>
> v2: Fix handling of `end` index in map_ppgtt
>
> v3: Correctly mark GGTT entry as present (Rafael)
>
> Signed-off-by: Scott D Phillips
> Signed-off
This patch is
Reviewed-by: Rafael Antognolli
On Thu, Jun 21, 2018 at 05:29:05PM +0100, Lionel Landwerlin wrote:
> We use memfd to store physical pages as they get read/written to and
> the GGTT entries translating virtual address to physical pages.
>
> Based on a commit by Sc
On Tue, Jun 19, 2018 at 02:45:28PM +0100, Lionel Landwerlin wrote:
> From: Scott D Phillips
>
> For gen8+, write out PPGTT tables in aub files so that full 48-bit
> addresses can be serialized.
>
> v2: Fix handling of `end` index in map_ppgtt
>
> Signed-off-by: Scott D Phillips
>
diff -u --ignore-all-space shows that this and the original file are
roughly the same, except for some macros, some includes and how we check
for hardware gen.
Acked-by: Rafael Antognolli
On Tue, Jun 19, 2018 at 02:45:27PM +0100, Lionel Landwerlin wrote:
> Signed-off-by: Lionel Landwer
E_DWORD(2 << 16)
> +
> +#define AUB_MEM_TRACE_REGISTER_SPACE_MASK0xf000
> +#define AUB_MEM_TRACE_REGISTER_SPACE_MMIO(0 << 28)
> +
> +/* DW3 */
> +
> +#define AUB_MEM_TRACE_MEMORY_ADDRESS_SPACE_MASK 0xf000
> +#define AUB_MEM_TRACE_M
On Wed, Jun 20, 2018 at 12:01:28PM -0700, Rafael Antognolli wrote:
> On Wed, Jun 20, 2018 at 11:03:32AM +0100, Lionel Landwerlin wrote:
> > On 20/06/18 01:00, Rafael Antognolli wrote:
> > > On Tue, Jun 19, 2018 at 02:45:22PM +0100, Lionel Landwerlin wrote:
> > &g
On Wed, Jun 20, 2018 at 11:03:32AM +0100, Lionel Landwerlin wrote:
> On 20/06/18 01:00, Rafael Antognolli wrote:
> > On Tue, Jun 19, 2018 at 02:45:22PM +0100, Lionel Landwerlin wrote:
> > > From: Scott D Phillips
> > >
> > > v2: by Lionel
> > >
On Tue, Jun 19, 2018 at 02:45:21PM +0100, Lionel Landwerlin wrote:
> We use memfd to store physical pages as they get read/written to and
> the GGTT entries translating virtual address to physical pages.
>
> Based on a commit by Scott Phillips.
>
> Signed-off-by: Lionel Landwerlin
> ---
>
On Tue, Jun 19, 2018 at 02:45:22PM +0100, Lionel Landwerlin wrote:
> From: Scott D Phillips
>
> v2: by Lionel
> Fix memfd_create compilation issue
> Fix pml4 address stored on 32 instead of 64bits
> Return no buffer if first ppgtt page is not mapped
>
> Signed-off-by: Lionel
Patch is
Reviewed-by: Rafael Antognolli
On Tue, Jun 19, 2018 at 02:45:19PM +0100, Lionel Landwerlin wrote:
> Now that we're softpinning the address of our BOs in anv & i965, the
> addresses selected start at the top of the addressing space. This is a
> problem for the current i
On Tue, Jun 19, 2018 at 11:40:30AM -0700, Rafael Antognolli wrote:
> On Tue, Jun 19, 2018 at 02:45:17PM +0100, Lionel Landwerlin wrote:
> > Now that we rely on mmap of the data to parse, we can't process the
> > standard input anymore.
>
> Didn't we rely on mmap of the data
For some reason I always have trouble finding the docs about this.
Still, it looks correct according to the docs, and it also seems to be
matching what I see in aubdump since "tools/intel_aubdump: Simulate
"enhanced execlist" submission for gen11+".
Reviewed-by: Rafael Antogno
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