Re: [Mesa-dev] [PATCH v2 2/2] glsl: update default precision qualifier when it is set in the shader

thor: Samuel Iglesias Gonsálvez <sigles...@igalia.com> mesa/program: Add _mesa_symbol_table_replace_symbol() - commit 0e742926c6895dcaf8bdbe43022c8a0bc74fdd96 Author: Samuel Iglesias Gonsálvez <sigles...@igalia.com> glsl: update default precision quali

[Mesa-dev] [PATCH v2 2/2] glsl: update default precision qualifier when it is set in the shader

Default precision qualifier for a data type could be set several times inside a shader. This patch allows to update the default precision qualifier for the given type that is saved in the symbol table. If it is not in the symbol table, just add it. Signed-off-by: Samuel Iglesias Gonsálvez

[Mesa-dev] [PATCH v2 1/2] mesa/program: Add _mesa_symbol_table_replace_symbol()

This function allows to modify an existing symbol. v2: - Remove namespace usage now that it was deleted. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/program/symbol_table.c | 14 ++ src/mesa/program/symbol_table.h | 4 2 files chang

Re: [Mesa-dev] [PATCH] glsl/mesa: remove unused namespace support from the symbol table

I have just minor comments. With those fixed and assuming no CI regressions: Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On 21/10/16 23:07, Timothy Arceri wrote: > Namespace support seems to have been unused for a very long time. > > Previously the hash table

Re: [Mesa-dev] [PATCH 2/2] glsl: update default precision qualifiers when they are set in the shader

On 21/10/16 07:48, Timothy Arceri wrote: > On Thu, 2016-10-20 at 12:39 +0200, Samuel Iglesias Gonsálvez wrote: >> For that, we use gls_symbol_table::set_default_precision_qualifier() >> that >> can update an existing definition or add a new one if it doesn't >> e

[Mesa-dev] [PATCH 2/2] glsl: update default precision qualifiers when they are set in the shader

For that, we use gls_symbol_table::set_default_precision_qualifier() that can update an existing definition or add a new one if it doesn't exist. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97804 Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/compile

[Mesa-dev] [PATCH 1/2] mesa/program: Add _mesa_symbol_table_replace_symbol()

This function allows to modify an existing symbol. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/program/symbol_table.c | 35 +++ src/mesa/program/symbol_table.h | 3 +++ 2 files changed, 38 insertions(+) diff --git a/sr

[Mesa-dev] [PATCH 1/2] glsl: move intrastage_match() after interstage_member_mismatch()

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- I did the move as interstage_member_mismatch() is the next function after intrastage_match() but I don't mind to either keep this patch or replace it with a change adding the interstage_member_mismatch() function prototype

[Mesa-dev] [PATCH 2/2] glsl/es31: precision qualifier doesn't need to match in shader interface block members

: https://bugs.freedesktop.org/show_bug.cgi?id=98243 Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/compiler/glsl/link_interface_blocks.cpp | 7 +-- src/compiler/glsl/linker.cpp| 10 +- 2 files changed, 14 insertions(+), 3 deletion

[Mesa-dev] [PATCH 0/2] glsl/es31: precision qualifier doesn't need to match in shader interface block members

.functional.shaders.linkage.uniform.block.differing_precision [1] https://bugs.freedesktop.org/show_bug.cgi?id=98243 Samuel Iglesias Gonsálvez (2): glsl: move intrastage_match() after interstage_member_mismatch() glsl/es31: precision qualifier doesn't need to match in shader interface block members src/compiler/glsl

Re: [Mesa-dev] [PATCH] i965/hsw: Enable ARB_ES3_1_compatibility extension

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On 27/08/16 23:18, Jordan Justen wrote: > Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> > Acked-by: Kenneth Graunke <kenn...@whitecape.org> > --- > docs/features.txt

Re: [Mesa-dev] [PATCH] i965: Include VUE handles for GS with invocations > 1.

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On 21/07/16 03:04, Kenneth Graunke wrote: > We always resort to the pull model for instanced GS inputs. So, we'd > better include the VUE handles, or else we can't actually pull anything. > > Cc: mesa-sta...@lis

Re: [Mesa-dev] Required Mako version? (WAS: mesa from git fails to compile)

On 14/07/16 18:34, Eric Engestrom wrote: > On Thu, Jul 14, 2016 at 04:01:13PM +0100, Eric Engestrom wrote: >> Oh right, there's already check for the Mako version, but the minimum is >> currently set to 0.3.4 (configure.ac:92). >> >> Emil, you were the one to mention 0.8.0; is that the actual

Re: [Mesa-dev] [PATCH 3/3] i965/fs: emit DIM instruction to load 64-bit immediates in HSW

On 14/07/16 03:46, Matt Turner wrote: > On Wed, Jul 13, 2016 at 5:06 PM, Matt Turner <matts...@gmail.com> wrote: >> On Tue, Jul 12, 2016 at 11:42 PM, Samuel Iglesias Gonsálvez >> <sigles...@igalia.com> wrote: >>> Signed-off-by: Samuel Iglesias Gonsálvez <

Re: [Mesa-dev] [PATCH 1/3] i965: enable the emission of the DIM instruction

On 14/07/16 02:04, Matt Turner wrote: > On Tue, Jul 12, 2016 at 11:42 PM, Samuel Iglesias Gonsálvez > <sigles...@igalia.com> wrote: >> Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> >> --- >> src/mesa/drivers/dri/i965/brw_defines.h

[Mesa-dev] [PATCH 1/3] i965: enable the emission of the DIM instruction

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/drivers/dri/i965/brw_defines.h | 2 +- src/mesa/drivers/dri/i965/brw_eu.c | 2 +- src/mesa/drivers/dri/i965/brw_eu.h | 1 + src/mesa/drivers/dri/i965/brw_eu_emit.c | 1

[Mesa-dev] [PATCH 2/3] i965/eu: set DF imm value to the source of DIM

mediate 64-bit DF value to the source of a DIM instruction even when it is of float type encoding. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/drivers/dri/i965/brw_eu_emit.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mesa/

[Mesa-dev] [PATCH 3/3] i965/fs: emit DIM instruction to load 64-bit immediates in HSW

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 12 1 file changed, 12 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp index a65c273..bf32dfd

Re: [Mesa-dev] [PATCH v2 1/6] i965/fs: add a helper function to create double immediates

On 11/07/16 14:54, Kenneth Graunke wrote: > On Monday, July 11, 2016 1:37:46 PM PDT Samuel Iglesias Gonsálvez wrote: >> From: Iago Toral Quiroga <ito...@igalia.com> >> >> Gen7 hardware does not support double immediates so these need >> to be moved in 32-bit

[Mesa-dev] [PATCH v2 3/6] i965/fs/gen7: split instructions that run into exec masking bugs

From: Iago Toral Quiroga In fp64 we can produce code like this: mov(16) vgrf2<2>:UD, vgrf3<2>:UD That our simd lowering pass would typically split in instructions with a width of 8, writing to two consecutive registers each. Unfortunately, gen7 hardware has a bug affecting

[Mesa-dev] [PATCH v2 6/6] i965/fs: do d2x lowering before simd splitting

So that we can have gen7 split large writes produced by this lowering pass. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/drivers/dri/i965/brw_fs.cpp | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_

[Mesa-dev] [PATCH v2 5/6] i965/fs: do pack lowering before simd splitting

From: Iago Toral Quiroga So that we can have gen7 split large writes produced by the pack lowering. Reviewed-by: Francisco Jerez --- src/mesa/drivers/dri/i965/brw_fs.cpp | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git

[Mesa-dev] [PATCH v2 4/6] i965/fs: do not require force_writemask_all with exec_size 4

So far we only used instructions with this size in situations where we did not operate per-channel and we wanted to ignore the execution mask, but gen7 fp64 will need to emit code with a width of 4 that needs normal execution masking. v2: - Modify the assert instead of deleting it (Curro)

[Mesa-dev] [PATCH v2 2/6] i965/fs: use the new helper function to create double immediates

From: Iago Toral Quiroga Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp

[Mesa-dev] [PATCH v2 0/6] i965/fs: fix Haswell support for doubles

pack lowering before simd splitting Samuel Iglesias Gonsálvez (2): i965/fs: do not require force_writemask_all with exec_size 4 i965/fs: do d2x lowering before simd splitting src/mesa/drivers/dri/i965/brw_fs.cpp | 48 -- src/mesa/drivers/dri/i965/brw_fs.h

[Mesa-dev] [PATCH v2 1/6] i965/fs: add a helper function to create double immediates

ending on the hardware generation. v2: - Define setup_imm_df() as an independent function (Curro) - Create a specific builder to get rid of some instruction field assignments (Curro). Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Reviewed-by: Kenneth Graunke <kenn..

Re: [Mesa-dev] [PATCH 2/6] i965/fs: use the new helper function to create double immediates

On 06/07/16 22:32, Kenneth Graunke wrote: > On Wednesday, July 6, 2016 12:09:58 PM PDT Samuel Iglesias Gonsálvez wrote: >> From: Iago Toral Quiroga <ito...@igalia.com> >> >> --- >> src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 6 +++--- >> 1 file changed, 3 i

Re: [Mesa-dev] [PATCH 1/6] i965/fs: add a helper function to create double immediates

On 08/07/16 00:27, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > >> From: Iago Toral Quiroga <ito...@igalia.com> >> >> Gen7 hardware does not support double immediates so these need >> to be moved in 32-bit

Re: [Mesa-dev] [PATCH 4/6] i965/fs: do not require force_writemask_all with exec_size 4

On 07/07/16 23:38, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > >> So far we only used instructions with this size in situations where we >> did not operate per-channel and we wanted to ignore the execution mask, >> but ge

Re: [Mesa-dev] [PATCH 6/6] i965/fs: don't copy propagate if the instruction writes to more than two adjacent GRFs

On 08/07/16 04:49, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > >> This is not allowed by the HW and copy propagation can hide this issue to >> lower_simd_width pass, which is going to fix it. >> >> Signed-off-b

Re: [Mesa-dev] [PATCH 2/6] i965/fs: use the new helper function to create double immediates

On 06/07/16 22:32, Kenneth Graunke wrote: > On Wednesday, July 6, 2016 12:09:58 PM PDT Samuel Iglesias Gonsálvez wrote: >> From: Iago Toral Quiroga <ito...@igalia.com> >> >> --- >> src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 6 +++--- >> 1 file changed, 3 i

[Mesa-dev] [PATCH 3/6] i965/fs/gen7: split instructions that run into exec masking bugs

From: Iago Toral Quiroga In fp64 we can produce code like this: mov(16) vgrf2<2>:UD, vgrf3<2>:UD That our simd lowering pass would typically split in instructions with a width of 8, writing to two consecutive registers each. Unfortunately, gen7 hardware has a bug affecting

[Mesa-dev] [PATCH 6/6] i965/fs: don't copy propagate if the instruction writes to more than two adjacent GRFs

This is not allowed by the HW and copy propagation can hide this issue to lower_simd_width pass, which is going to fix it. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp | 1 + 1 file changed, 1 insertion(+) diff

[Mesa-dev] [PATCH 2/6] i965/fs: use the new helper function to create double immediates

From: Iago Toral Quiroga --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp index 268c847..d805d95 100644 ---

[Mesa-dev] [PATCH 5/6] i965/fs: do pack lowering before simd splitting

From: Iago Toral Quiroga So that we can have gen7 split large writes produced by the pack lowering. --- src/mesa/drivers/dri/i965/brw_fs.cpp | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp

[Mesa-dev] [PATCH 4/6] i965/fs: do not require force_writemask_all with exec_size 4

So far we only used instructions with this size in situations where we did not operate per-channel and we wanted to ignore the execution mask, but gen7 fp64 will need to emit code with a width of 4 that needs normal execution masking. --- src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 1 - 1

[Mesa-dev] [PATCH 1/6] i965/fs: add a helper function to create double immediates

From: Iago Toral Quiroga Gen7 hardware does not support double immediates so these need to be moved in 32-bit chunks to a regular vgrf instead. Instead of doing this every time we need to create a DF immediate, create a helper function that does the right thing depending on

[Mesa-dev] [PATCH 0/6] i965/fs: fix Haswell support for doubles

lit instructions that run into exec masking bugs i965/fs: do pack lowering before simd splitting Samuel Iglesias Gonsálvez (2): i965/fs: do not require force_writemask_all with exec_size 4 i965/fs: don't copy propagate if the instruction writes to more than two adjacent GRFs src/mesa/driv

Re: [Mesa-dev] [PATCH] i965: consolidate generation check

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On 06/07/16 05:14, Timothy Arceri wrote: > --- > src/mesa/drivers/dri/i965/brw_vs.c | 12 ++-- > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/src/mesa/drivers/dri/i965/brw_vs.c >

Re: [Mesa-dev] [PATCH] i965: make more effective use of SamplersUsed

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On 05/07/16 09:10, Timothy Arceri wrote: > --- > src/mesa/drivers/dri/i965/brw_cs.c | 3 +-- > src/mesa/drivers/dri/i965/brw_gs.c | 4 +--- > src/mesa/drivers/dri/i965/brw_program.h | 1 - > src/

Re: [Mesa-dev] [PATCH] glsl: stop allocating memory for UBOs during linking

On 02/07/16 12:02, Timothy Arceri wrote: > This just stops counting and assigning a storage location for > these uniforms, the count is only used to create the uniform storage. > > This uniform types don't use this storage. s/This/These Reviewed-by: Samuel Iglesias Gonsá

Re: [Mesa-dev] [PATCH] glsl: mark link_uniform_blocks_are_compatible() as static

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On 02/07/16 05:36, Timothy Arceri wrote: > Missed this when doing 6d1a59d15b. > --- > src/compiler/glsl/link_uniform_blocks.cpp | 2 +- > src/compiler/glsl/linker.h| 4 > 2 files chang

Re: [Mesa-dev] [PATCH] mesa: stop copying SamplerUnits twice

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On 03/07/16 11:16, Timothy Arceri wrote: > The call to _mesa_update_shader_textures_used() already takes > care of copying for us. > --- > src/mesa/main/uniform_query.cpp | 4 > 1 file changed, 4 deletio

Re: [Mesa-dev] [PATCH] mesa: remove remaining tabs in api_validate.c

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On 17/06/16 07:12, Timothy Arceri wrote: > --- > src/mesa/main/api_validate.c | 22 +++--- > 1 file changed, 11 insertions(+), 11 deletions(-) > > diff --git a/src/mesa/main/api_valid

Re: [Mesa-dev] [PATCH v3] i965/fs: indirect addressing with doubles is not supported in CHV/BSW/BXT

On 17/06/16 11:12, Kenneth Graunke wrote: > On Friday, June 17, 2016 11:10:28 AM PDT Samuel Iglesias Gonsálvez wrote: [...] >> What do you think Kenneth? >> >> Sam > > This sounds great to me. I like v4 (your suggestion above) the best. > Thanks for fixing this, a

Re: [Mesa-dev] [PATCH v3] i965/fs: indirect addressing with doubles is not supported in CHV/BSW/BXT

On 17/06/16 10:43, Samuel Iglesias Gonsálvez wrote: > From the Cherryview's PRM, Volume 7, 3D Media GPGPU Engine, Register Region > Restrictions, page 844: > > "When source or destination datatype is 64b or operation is integer DWord >multiply, indirect address

[Mesa-dev] [PATCH v3] i965/fs: indirect addressing with doubles is not supported in CHV/BSW/BXT

e by using subscript() and not creating a new num_components variable (Kenneth). Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Cc: "12.0" <mesa-sta...@lists.freedesktop.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95462 --- src/mesa/driv

Re: [Mesa-dev] [PATCH 2/2] i965/fs: indirect addressing with doubles is not supported in CHV/BSW

On 17/06/16 08:57, Kenneth Graunke wrote: > On Wednesday, June 15, 2016 9:25:45 AM PDT Samuel Iglesias Gonsálvez wrote: >> From the Cherryview's PRM, Volume 7, 3D Media GPGPU Engine, Register Region >> Restrictions, page 844: >> >> "When source or destinat

[Mesa-dev] [PATCH v2 1/2] i965/fs: Fix single-precision to double-precision conversions for CHV/BSW/BXT

From: Iago Toral Quiroga From the Cherryview PRM, Volume 7, 3D Media GPGPU Engine, Register Region Restrictions: "When source or destination is 64b (...), regioning in Align1 must follow these rules: 1. Source and destination horizontal stride must be aligned to

[Mesa-dev] [PATCH v2 2/2] i965/fs: indirect addressing with doubles is not supported in CHV/BSW/BXT

From the Cherryview's PRM, Volume 7, 3D Media GPGPU Engine, Register Region Restrictions, page 844: "When source or destination datatype is 64b or operation is integer DWord multiply, indirect addressing must not be used." v2: - Fix it for Broxton too. Signed-off-by: Samue

[Mesa-dev] [PATCH 2/2] i965/fs: indirect addressing with doubles is not supported in CHV/BSW

From the Cherryview's PRM, Volume 7, 3D Media GPGPU Engine, Register Region Restrictions, page 844: "When source or destination datatype is 64b or operation is integer DWord multiply, indirect addressing must not be used." Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@i

[Mesa-dev] [PATCH 1/2] i965/fs: Fix single-precision to double-precision conversions for CHV/BSW

From: Iago Toral Quiroga From the Cherryview PRM, Volume 7, 3D Media GPGPU Engine, Register Region Restrictions: "When source or destination is 64b (...), regioning in Align1 must follow these rules: 1. Source and destination horizontal stride must be aligned to

Re: [Mesa-dev] [PATCH 0/2] fix load of unpacked double vector input varyings

On 02/06/16 07:43, Timothy Arceri wrote: > On Thu, 2016-06-02 at 07:22 +0200, Samuel Iglesias Gonsálvez wrote: >> On 26/05/16 07:56, Samuel Iglesias Gonsálvez wrote: >>> >>> Hello, >>> >>> Timothy found that tests with unpacked double vector i

Re: [Mesa-dev] [PATCH 0/2] fix load of unpacked double vector input varyings

On 26/05/16 07:56, Samuel Iglesias Gonsálvez wrote: > Hello, > > Timothy found that tests with unpacked double vector input varyings > were failing in i965 driver. For example, this is happening when > using explicit locations because Mesa disables varying packing

Re: [Mesa-dev] [PATCH 1/5] mesa: Fix bogus strncmp

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On Tue, 2016-05-31 at 11:52 -0700, Ian Romanick wrote: > From: Ian Romanick <ian.d.roman...@intel.com> > > The string "[0]\0" is the same as "[0]" as far as the C string > datatype > is c

Re: [Mesa-dev] [PATCH 0/2] fix load of unpacked double vector input varyings

On 31/05/16 02:26, Timothy Arceri wrote: > On Mon, 2016-05-30 at 15:46 +0200, Samuel Iglesias Gonsálvez wrote: >> >> On 27/05/16 08:39, Samuel Iglesias Gonsálvez wrote: >>> >>> >>> >>> On 26/05/16 09:46, Timothy Arceri wrote: >>>&g

Re: [Mesa-dev] [PATCH 0/2] fix load of unpacked double vector input varyings

On 27/05/16 08:39, Samuel Iglesias Gonsálvez wrote: > > > On 26/05/16 09:46, Timothy Arceri wrote: >> On Thu, 2016-05-26 at 17:44 +1000, Timothy Arceri wrote: >>> On Thu, 2016-05-26 at 07:56 +0200, Samuel Iglesias Gonsálvez wrote: >>>> >>&g

[Mesa-dev] [PATCH 3/2] i965/gs/scalar: Fix load input for doubles

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 72 1 file changed, 54 insertions(+), 18 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_n

Re: [Mesa-dev] [PATCH 0/2] fix load of unpacked double vector input varyings

On 26/05/16 09:46, Timothy Arceri wrote: > On Thu, 2016-05-26 at 17:44 +1000, Timothy Arceri wrote: >> On Thu, 2016-05-26 at 07:56 +0200, Samuel Iglesias Gonsálvez wrote: >>> >>> Hello, >>> >>> Timothy found that tests with unpacked double vector i

[Mesa-dev] [PATCH 2/2] i965/fs: fix FS_OPCODE_CINTERP for unpacked double input varyings

Data starts at suboffet 3 in 32-bit units (12 bytes), so it is not 64-bit aligned and the current implementation fails to read the data properly. Instead, when there is is a double input varying, read it as vector of floats with twice the number of components. Signed-off-by: Samuel Iglesias

[Mesa-dev] [PATCH 1/2] i965/fs: fix offset when loading double vector input varyings

but offset() is multiplying it by destination type size units. When operating with double input varyings, const_index value could be not aligned to 64 bits. To fix it, we load the double vector as if it was a float based vector with twice the number of components. Signed-off-by: Samuel Iglesias Gonsálvez

[Mesa-dev] [PATCH 0/2] fix load of unpacked double vector input varyings

/execution/vs-fs-explicit-locations Samuel Iglesias Gonsálvez (2): i965/fs: fix offset when loading double vector input varyings i965/fs: fix FS_OPCODE_CINTERP for unpacked double input varyings src/mesa/drivers/dri/i965/brw_fs.cpp | 13 - src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 22

Re: [Mesa-dev] [PATCH] glsl: handle implicit sized arrays in ssbo

 !fields[i].implicit_sized_array) { >      const int *const max_ifc_array_access = > ir->get_max_ifc_array_access(); >   > diff --git a/src/compiler/glsl/link_uniform_blocks.cpp > b/src/compiler/glsl/link_uniform_blocks.cpp > index ac415b5..3cb1a68 1006

Re: [Mesa-dev] [PATCH] i965/fs: Fix off-by-one region overlap comparison in copy propagation.

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On 24/05/16 05:34, Francisco Jerez wrote: > This was introduced in cf375ae54a01462f192202d609436e5fbec8 but > the blame is mine because the pseudocode I sent in my review comment > for the original patch suggesti

Re: [Mesa-dev] [PATCH 00/59] Initial arb_gpu_shader_fp64 support to the i965 scalar backend

On 30/04/16 09:52, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > >> Hello, >> >> This patch series continues adding arb_gpu_shader_fp64 support to the >> Intel driver. Specifically, this targets the i965 scalar backend

Re: [Mesa-dev] [PATCH v2 00/30] Finishing arb_gpu_shader_fp64 support to the i965 scalar backend

-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 On 16/05/16 11:04, Samuel Iglesias Gonsálvez wrote: > > > On 13/05/16 11:56, Iago Toral wrote: >> On Thu, 2016-05-12 at 13:35 +0200, Samuel Iglesias Gonsálvez >> wrote: >>> Hi, >>> >>> this versi

Re: [Mesa-dev] Mesa 11.3.0/12.0.0 release plan

-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 On 14/05/16 17:05, Emil Velikov wrote: > On 29 April 2016 at 14:07, Iago Toral wrote: >> On Fri, 2016-04-29 at 14:01 +0100, Emil Velikov wrote: >>> On 29 April 2016 at 13:19, Iago Toral >>> wrote: On

Re: [Mesa-dev] [PATCH v2 00/30] Finishing arb_gpu_shader_fp64 support to the i965 scalar backend

-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 On 13/05/16 11:56, Iago Toral wrote: > On Thu, 2016-05-12 at 13:35 +0200, Samuel Iglesias Gonsálvez > wrote: >> Hi, >> >> this version includes all the feedback received to v1 plus a few >> new patches (22-27) that d

Re: [Mesa-dev] [PATCH v2 15/30] i965/fs: support doubles with UBO loads

On 15/05/16 00:13, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > >> On 14/05/16 01:16, Francisco Jerez wrote: >>> Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: >>> >>>> From: Iago

Re: [Mesa-dev] [PATCH v2 15/30] i965/fs: support doubles with UBO loads

On 14/05/16 01:16, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > >> From: Iago Toral Quiroga <ito...@igalia.com> >> >> UBO loads with constant offset use the UNIFORM_PULL_CONSTANT_LOAD >> instruction, which r

Re: [Mesa-dev] [PATCH] i965: Fix undefined df bits in brw_reg comparisons.

-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 With Curro's comment addressed, Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On 14/05/16 02:44, Kenneth Graunke wrote: > Commit 5310bca024f77da40ea6f4c275455f9cb0528f9e added a new "double > df" field to the

[Mesa-dev] [PATCH 2/2] i965: initialize the alignment related bits in struct brw_reg

==by 0xAA3B068: brw_fs_precompile (brw_wm.c:637) This patch adds an explicit padding and initializes it to zero. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- This patch replaces the following one: [PATCH 2/2] i965: check each field separately in backend_end::equals(

Re: [Mesa-dev] [PATCH v2 19/30] i965/fs: add shuffle_64bit_data_for_32bit_write helper

-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 On 13/05/16 05:05, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > >> From: Iago Toral Quiroga <ito...@igalia.com> >> >> This does the inverse operation of >> shuf

Re: [Mesa-dev] [PATCH v2 09/30] i965/fs: fix copy/constant propagation regioning checks

-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 On 13/05/16 07:11, Samuel Iglesias Gonsálvez wrote: > > > On 13/05/16 02:42, Francisco Jerez wrote: >> Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: >> >>> From: Iago Toral Quiroga <ito...@igal

Re: [Mesa-dev] [PATCH v2 03/30] i965/fs: Fix copy propagation of load payload for double operands

-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 On 13/05/16 07:09, Samuel Iglesias Gonsálvez wrote: > > > On 13/05/16 01:52, Francisco Jerez wrote: >> Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: >> >>> From: Iago Toral Quiroga <ito...@igal

Re: [Mesa-dev] [PATCH 2/2] i965: check each field separately in backend_end::equals()

-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 On 13/05/16 05:38, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > >> Extra bits required to make room for the df field of the union >> don't get initialized in all codepaths, so backend

Re: [Mesa-dev] [PATCH v2 09/30] i965/fs: fix copy/constant propagation regioning checks

On 13/05/16 02:42, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > >> From: Iago Toral Quiroga <ito...@igalia.com> >> >> We were not accounting for subreg_offset in the check for the start >> of the region. >

Re: [Mesa-dev] [PATCH v2 03/30] i965/fs: Fix copy propagation of load payload for double operands

On 13/05/16 01:52, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > >> From: Iago Toral Quiroga <ito...@igalia.com> >> >> Specifically, consider the size of the data type of the operand to compute >> the number of r

[Mesa-dev] [PATCH v2 22/30] i965/vec4: handle doubles in type_size_vec4()

From: Iago Toral Quiroga The scalar backend uses this to check URB input sizes. --- src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp

[Mesa-dev] [PATCH v2 18/30] i965/fs: support doubles with SSBO loads

From: Iago Toral Quiroga --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 9 ++--- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp index 73b9082..ae95448 100644 ---

[Mesa-dev] [PATCH v2 27/30] i965/tes/scalar: Fix load input for doubles

From: Iago Toral Quiroga --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp index 2160127..57ab020 100644 ---

[Mesa-dev] [PATCH v2 15/30] i965/fs: support doubles with UBO loads

lement in a vector. v2 (Sam): - Adapt the code to use component() (Curro). Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 52 +++- 1 file chan

[Mesa-dev] [PATCH v2 28/30] i965: Enable ARB_gpu_shader_fp64 for gen8+

From: Iago Toral Quiroga Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/intel_extensions.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c

[Mesa-dev] [PATCH v2 30/30] i965: Expose OpenGL 4.0 for gen8+

From: Iago Toral Quiroga ARB_gpu_shader_fp64 was the only feature missing. Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/intel_extensions.c | 4 +++- src/mesa/drivers/dri/i965/intel_screen.c | 2 +- 2 files changed, 4 insertions(+), 2

[Mesa-dev] [PATCH v2 29/30] docs: Mark ARB_gpu_shader_fp64 as done for i965/gen8+

From: Iago Toral Quiroga Reviewed-by: Kenneth Graunke --- docs/GL3.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/GL3.txt b/docs/GL3.txt index e2dabea..c957604 100644 --- a/docs/GL3.txt +++ b/docs/GL3.txt @@ -124,7 +124,7

[Mesa-dev] [PATCH v2 19/30] i965/fs: add shuffle_64bit_data_for_32bit_write helper

From: Iago Toral Quiroga This does the inverse operation of shuffle_32bit_load_result_to_64bit_data and we will use it when we need to write 64-bit data in the layout expected by untyped write messages. v2 (curro): - Use subscript() instead of stride() - Assert on the input

[Mesa-dev] [PATCH v2 26/30] i965/tcs/scalar: fix store output for doubles

From: Iago Toral Quiroga --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 117 +-- 1 file changed, 96 insertions(+), 21 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp index

[Mesa-dev] [PATCH v2 21/30] i965/fs: support doubles with shared variable stores

From: Iago Toral Quiroga This is pretty much the same we do with SSBOs. --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 37 +++- 1 file changed, 32 insertions(+), 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp

[Mesa-dev] [PATCH v2 25/30] i965/tcs/scalar: fix load input for doubles

From: Iago Toral Quiroga --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 96 +++- 1 file changed, 71 insertions(+), 25 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp index

[Mesa-dev] [PATCH v2 23/30] i965/fs: fix number of output components for doubles

From: Iago Toral Quiroga --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 13 + 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp index 419f940..cf5cdab 100644 ---

[Mesa-dev] [PATCH v2 11/30] i965/fs: add shuffle_32bit_load_result_to_64bit_data helper

From: Iago Toral Quiroga There will be a few places where we need to shuffle the result of a 32-bit load into valid 64-bit data, so extract this logic into a separate helper that we can reuse. The shuffling needs to operate with WE_all set because we are changing the layout

[Mesa-dev] [PATCH v2 16/30] i965/fs: Add do_untyped_vector_read helper

From: Iago Toral Quiroga We are going to need the same logic for anything that reads doubles via untyped messages (CS shared variables and SSBOs). Add a helper function with that logic so that we can reuse it. Reviewed-by: Kenneth Graunke ---

[Mesa-dev] [PATCH v2 24/30] i965/fs: fix nir_intrinsic_store_output for doubles

From: Iago Toral Quiroga --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 15 ++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp index cf5cdab..bf6375b 100644 ---

[Mesa-dev] [PATCH v2 13/30] i965/fs: Fix and document component().

viewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/drivers/dri/i965/brw_ir_fs.h | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_ir_fs.h b/src/mesa/drivers/dri/i965/brw_ir_fs.h index 305d91c..3d47b0c 100644 --- a/src/mesa

[Mesa-dev] [PATCH v2 17/30] i965/fs: support double with shared variable loads

From: Iago Toral Quiroga Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 10 ++ 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp

[Mesa-dev] [PATCH v2 20/30] i965/fs: support doubles with ssbo stores

From: Iago Toral Quiroga --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 39 1 file changed, 35 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp index

[Mesa-dev] [PATCH v2 14/30] i965/fs: fix pull constant load component selection for doubles

ed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/drivers/dri/i965/brw_fs.cpp | 3 ++- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 13 +++-- 2 files changed, 5 insertions(+), 11 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/driv

[Mesa-dev] [PATCH v2 09/30] i965/fs: fix copy/constant propagation regioning checks

From: Iago Toral Quiroga We were not accounting for subreg_offset in the check for the start of the region. Also, fs_reg::regs_read() already takes the stride into account, so we should not multiply its result by the stride again. This was making copy-propagation fail to

[Mesa-dev] [PATCH v2 12/30] i965/fs: Fix fs_visitor::VARYING_PULL_CONSTANT_LOAD for doubles

From: Iago Toral Quiroga Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_fs.cpp | 19 +-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp

[Mesa-dev] [PATCH v2 10/30] i965/fs: Stop using the LOAD_PAYLOAD instruction in lower_simd_width.

From: Francisco Jerez Instead of using the LOAD_PAYLOAD instruction (emitted through the emit_transpose() helper that is no longer useful and this commit removes) which had to be marked force_writemask_all in some cases, emit a series of moves to apply proper channel

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