On Mon, 2015-09-21 at 07:49 -0700, Kenneth Graunke wrote:
> On Monday, September 21, 2015 09:46:24 AM Mark Janes wrote:
> > This series hits an assertion on ILK and G45:
> >
> > src/mesa/drivers/dri/i965/brw_eu_emit.c:150: brw_set_dest: Assertion
> > `dest.nr < (devinfo->gen == 6 ? 24 : 16)' faile
other platform I guess
that's a good sign, but I'll let Ken make that call.
Iago
> thanks,
>
> Mark
>
> Iago Toral Quiroga writes:
>
> > There are some bug reports about shaders failing to compile in gen6
> > because MRF 14 is used when we need to spi
On Wed, 2015-09-16 at 12:32 -0700, Kenneth Graunke wrote:
> On Wednesday, September 16, 2015 11:17:53 AM Iago Toral Quiroga wrote:
> > It seems that we have some bugs where we fail to compile shaders in gen6
> > because we do not having enough MRF registers available (see bugs 8646
On Tue, 2015-09-22 at 08:10 +0200, Iago Toral wrote:
> Hi Mark,
>
> On Mon, 2015-09-21 at 17:45 -0700, Mark Janes wrote:
> > Hi Iago,
> >
> > According to my tests, this patch series fixes the gles2/gles3
> > "functional.uniform_api.random.23" tests i
ession from commit:
>04e201d0c02cd30ace5c6fe80e9f021ebb733682
>
> Additions in v2 also fix following failing deqp test:
>dEQP-GLES[2|3].functional.negative_api.shader.shader_source
Nice! I wasn't expecting that :)
Reviewed-by: Iago Toral Quiroga
> v2: cleanup function, do
On Tue, 2015-09-22 at 14:00 +0200, Iago Toral Quiroga wrote:
> Originally, these could conflict with our spills, but now that we moved the
> latter to MRFs 21..23, that is no longer the case. Still, in gen6 we
> now use MRFs 1..15 for URB writes, so we probably want to make our pull
&
ction
counts may not be the best thing to do. However, if ffma operations are
more expensive that fadd, a higher instruction count should always lead
to worse performance, so that should be ok.
Reviewed-by: Iago Toral Quiroga
> src/glsl/nir/nir_opt_peephole_ffma.c | 20 ---
On Wed, 2015-09-23 at 14:07 +0200, Eduardo Lima Mitev wrote:
> On 09/23/2015 10:42 AM, Marta Lofstedt wrote:
> > From: Marta Lofstedt
> >
> > Signed-off-by: Marta Lofstedt
> > ---
> > docs/GL3.txt | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/docs/GL3.txt b/doc
On Wed, 2015-09-23 at 14:34 +, Lofstedt, Marta wrote:
> > -Original Message-
> > From: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] On
> > Behalf Of Iago Toral
> > Sent: Wednesday, September 23, 2015 3:18 PM
> > To: Eduardo Lima Mitev
> >
On Wed, 2015-09-23 at 10:38 -0700, Kristian Høgsberg wrote:
> On Wed, Sep 23, 2015 at 12:06 AM, Samuel Iglesias Gonsálvez
> wrote:
> >
> >
> > On 19/09/15 01:56, Kristian Høgsberg wrote:
> >> On Thu, Sep 10, 2015 at 03:35:16PM +0200, Iago Toral Quiroga wrote:
On Mon, 2015-09-21 at 09:21 -0700, Matt Turner wrote:
> On Mon, Sep 21, 2015 at 8:00 AM, Iago Toral wrote:
> > On Mon, 2015-09-21 at 07:49 -0700, Kenneth Graunke wrote:
> >> On Monday, September 21, 2015 09:46:24 AM Mark Janes wrote:
> >> > This series hi
On Fri, 2015-09-25 at 21:15 -0400, Ilia Mirkin wrote:
> Hi Samuel,
>
> It seems like there's only a single atomic_min intrinsic for ssbo
> (same for max), but the ssbo spec actually calls for both signed and
> unsigned semantics:
>
> uint atomicMin(inout uint mem, uint data);
> in
Ian, you wrote the original code, so you might want to have a look at
this one just in case I missed something even if piglit does not
complain. In any case, I guess that either the code or the comment
should be fixed.
Iago
On Mon, 2015-09-28 at 12:59 +0200, Iago Toral Quiroga wrote:
>
CCing Ian...
On Mon, 2015-09-28 at 13:02 +0200, Iago Toral wrote:
> Ian, you wrote the original code, so you might want to have a look at
> this one just in case I missed something even if piglit does not
> complain. In any case, I guess that either the code or the comment
> sho
On Mon, 2015-09-28 at 13:13 +0300, Francisco Jerez wrote:
> Iago Toral Quiroga writes:
>
> > From: Kristian Høgsberg
> >
> > ---
> > src/glsl/ast_to_hir.cpp | 6 +++---
> > 1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/s
On Mon, 2015-09-28 at 13:45 +0200, Iago Toral wrote:
> On Mon, 2015-09-28 at 13:13 +0300, Francisco Jerez wrote:
> > Iago Toral Quiroga writes:
> >
> > > From: Kristian Høgsberg
> > >
> > > ---
> > > src/glsl/ast_to_hir.cpp | 6 +++---
On Mon, 2015-09-28 at 15:23 +0300, Francisco Jerez wrote:
> Iago Toral writes:
>
> > On Mon, 2015-09-28 at 13:13 +0300, Francisco Jerez wrote:
> >> Iago Toral Quiroga writes:
> >>
> >> > From: Kristian Høgsberg
> >> >
> >>
Reviewed-by: Iago Toral Quiroga
On Tue, 2015-09-29 at 12:42 +1000, Timothy Arceri wrote:
> ---
> src/glsl/ast_to_hir.cpp | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
> index a9696dc..2fd4443 10064
; --- a/src/mesa/drivers/dri/i965/brw_vec4_gs_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_nir.cpp
> @@ -72,6 +72,9 @@
> vec4_gs_visitor::nir_setup_system_value_intrinsic(nir_intrinsic_instr *instr)
> dst_reg *reg;
>
> switch (instr->intrinsic) {
>
Hi ilia,
On Tue, 2015-09-29 at 03:53 -0400, Ilia Mirkin wrote:
> Hi Samuel, and any other onlookers,
>
> I was wondering why the decision was made to stick SSBO's onto the
> same list as constbufs. Seems like they're entirely separate entities,
> no? Perhaps I'm missing something?
The reason for
On Tue, 2015-09-29 at 11:19 -0400, Ilia Mirkin wrote:
> On Tue, Sep 29, 2015 at 4:33 AM, Iago Toral wrote:
> > Hi ilia,
> >
> > On Tue, 2015-09-29 at 03:53 -0400, Ilia Mirkin wrote:
> >> Hi Samuel, and any other onlookers,
> >>
> >> I was wonderin
On Wed, 2015-09-30 at 02:34 -0400, Ilia Mirkin wrote:
> On Wed, Sep 30, 2015 at 2:26 AM, Iago Toral wrote:
> > On Tue, 2015-09-29 at 11:19 -0400, Ilia Mirkin wrote:
> >> On Tue, Sep 29, 2015 at 4:33 AM, Iago Toral wrote:
> >> > Hi ilia,
> >> >
>
On Tue, 2015-09-29 at 18:41 +0300, Francisco Jerez wrote:
> Ilia Mirkin writes:
>
> > On Tue, Sep 29, 2015 at 4:33 AM, Iago Toral wrote:
> >> Hi ilia,
> >>
> >> On Tue, 2015-09-29 at 03:53 -0400, Ilia Mirkin wrote:
> >>> Hi Samuel, and any o
On Wed, 2015-09-30 at 11:54 +0300, Francisco Jerez wrote:
> Iago Toral writes:
>
> > On Tue, 2015-09-29 at 18:41 +0300, Francisco Jerez wrote:
> >> Ilia Mirkin writes:
> >>
> >> > On Tue, Sep 29, 2015 at 4:33 AM, Iago Toral wrote:
> >> >
On Wed, 2015-09-30 at 11:27 -0400, Ilia Mirkin wrote:
> On Wed, Sep 30, 2015 at 3:18 AM, Iago Toral wrote:
> > On Wed, 2015-09-30 at 02:34 -0400, Ilia Mirkin wrote:
> >> On Wed, Sep 30, 2015 at 2:26 AM, Iago Toral wrote:
> >> > On Tue, 2015-09-29 at 11:19 -0400, Ili
On Thu, 2015-10-01 at 09:13 +0300, Tapani Pälli wrote:
>
> On 09/29/2015 05:38 PM, Iago Toral Quiroga wrote:
> > Since we store both in UniformBlocks, we can't just compute the index by
> > subtracting the array address start, we need to count the number of
> > b
On Thu, 2015-10-01 at 02:18 -0400, Ilia Mirkin wrote:
> On Thu, Oct 1, 2015 at 2:12 AM, Iago Toral wrote:
> > However, I think this can be a problem in your case, because you can't
> > remap the block index if you don't know how many blocks in UniformBlocks
> > be
On Thu, 2015-10-01 at 02:30 -0400, Ilia Mirkin wrote:
> On Thu, Oct 1, 2015 at 2:24 AM, Iago Toral wrote:
> > On Thu, 2015-10-01 at 02:18 -0400, Ilia Mirkin wrote:
> >> On Thu, Oct 1, 2015 at 2:12 AM, Iago Toral wrote:
> >> > However, I think this can be a problem i
mponents in the writemask, saving some
> store instructions plus avoid storing wrong data on each disabled
> component.
Reviewed-by: Iago Toral Quiroga
> Signed-off-by: Samuel Iglesias Gonsalvez
> ---
> src/glsl/lower_ubo_reference.cpp | 6 ++
> 1 file changed, 6 inserti
On Thu, 2015-10-01 at 08:28 +0300, Tapani Pälli wrote:
> Patch adds missing type (used with NV_read_depth) so that it gets
> handled correctly. Also add type to _mesa_problem output to aid
> debugging.
>
> Signed-off-by: Tapani Pälli
> ---
> src/mesa/main/pack.c | 4 +++-
> 1 file changed, 3 ins
On Wed, 2015-09-30 at 18:41 -0700, Jason Ekstrand wrote:
> Previously, we had a bunch of code in each stage to figure out how many
> slots we needed in stage_prog_data.param. This code was mostly identical
> across the stages and had been copied and pasted around. Unfortunately,
> this meant that
Reviewed-by: Iago Toral Quiroga
On Wed, 2015-09-30 at 18:41 -0700, Jason Ekstrand wrote:
> That way, if we do the usual thing of multiplying vector_elements by
> matrix_columns we get the actual number of components in the type as per
> component_slots().
>
> While we're a
Reviewed-by: Iago Toral Quiroga
On Wed, 2015-09-30 at 18:41 -0700, Jason Ekstrand wrote:
> The next commit will add code to codegen_vs_prog that requires the NIR
> shader to be there in all cases. It doesn't hurt anything to just move it
> from brw_vs_emit to its only caller.
>
On Thu, 2015-10-01 at 07:58 -0700, Jason Ekstrand wrote:
> On Thu, Oct 1, 2015 at 7:52 AM, Iago Toral wrote:
> > On Wed, 2015-09-30 at 18:41 -0700, Jason Ekstrand wrote:
> >> Previously, we had a bunch of code in each stage to figure out how many
> >> slots we need
On Thu, 2015-10-01 at 14:01 -0400, Ilia Mirkin wrote:
> On Thu, Oct 1, 2015 at 7:09 AM, Iago Toral Quiroga wrote:
> > These arrays provide backends with separate index spaces for UBOS and SSBOs.
> > ---
> > src/glsl/linker.cpp
Reviewed-by: Iago Toral Quiroga
On Thu, 2015-10-01 at 20:19 -0400, Ilia Mirkin wrote:
> Signed-off-by: Ilia Mirkin
> ---
> src/mesa/program/hash_table.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/src/mesa/program/hash_table.h b/src/mesa/program/hash_table
if (num_uniforms == 0)
>return;
>
> - /* assign hidden uniforms a slot id */
> - hiddenUniforms->iterate(assign_hidden_uniform_slot_id, &uniform_size);
> - delete hiddenUniforms;
> -
I suppose there is no much gain in simply adding the delete statement
Reviewed-by: Iago Toral Quiroga
On Thu, 2015-10-01 at 20:27 -0400, Ilia Mirkin wrote:
> Signed-off-by: Ilia Mirkin
> ---
> src/mesa/drivers/dri/i965/brw_program.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_program.c
> b/src/
gt; + case BRW_OPCODE_DP2:
> +readmask = 0x3;
> +break;
I don't know if there are other opcodes that could also be
special-handled like these, but if there are we are only missing the
opportunity to do tighter packing for them (which we are not doing now
a
Reviewed-by: Iago Toral Quiroga
On Wed, 2015-09-30 at 18:41 -0700, Jason Ekstrand wrote:
> The uniform_vector_size array was only ever used by pack_uniform_registers
> which no longer needs it.
> ---
> src/mesa/drivers/dri/i965/brw_vec4.cpp| 1 -
> src/mesa/d
+ static const gl_constant_value zero = { 0 };
> +
> + for (unsigned i = 0; i < n; ++i)
> + params[i] = &values[i];
> +
> + for (unsigned i = n; i < 4; ++i)
> + params[i] = &zero;
> +}
I actually liked the version that received an offset in
On Fri, 2015-10-02 at 10:29 +0200, Iago Toral wrote:
> On Wed, 2015-09-30 at 18:41 -0700, Jason Ekstrand wrote:
> > I tried to do this once before but Curro pointed out that having it in
> > backend_shader meant it could use the setup_vec4_uniform_values helper
> > which di
Reviewed-by: Iago Toral Quiroga
On Wed, 2015-09-30 at 18:41 -0700, Jason Ekstrand wrote:
> It's not used by anything anymore
> ---
> src/mesa/drivers/dri/i965/brw_fs.cpp | 14 --
> src/mesa/drivers/dri/i965/brw_fs.h | 4
> src/m
> @@ -197,6 +194,7 @@ vec4_visitor::nir_setup_uniform(nir_variable *var)
> * order we'd walk the type, so walk the list of storage and find anything
> * with our name, or the prefix of a component that starts with our name.
> */
> +unsigned index = var->
nt
> - * constants; matrices and other larger types should have been
> broken
> - * down earlier.
> - */
> - assert(plist->Parameters[p].Size <= 4);
> + brw_nir_setup_arb_uniforms(shader, prog, stage_prog_data);
>
> -
unsigned vector_count = (MAX2(storage->array_elements, 1) *
> + storage->type->matrix_columns);
> + unsigned vector_size = storage->type->vector_elements;
> +
> + for (unsigned s = 0; s < vector_count; s++
Reviewed-by: Iago Toral Quiroga
On Wed, 2015-09-30 at 18:41 -0700, Jason Ekstrand wrote:
> ---
> src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 19 ---
> src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 21 -
> 2 files changed, 16 insertions(+),
I think this never got a review, anyone willing to take it?
Iago
On Mon, 2015-09-14 at 13:49 +0200, Iago Toral Quiroga wrote:
> When we find indirect indexing into an array, the current implementation
> of the array spliiting optimization pass does not look further into the
> expres
Hi Markus,
I noticed that you did not reply to mesa-dev in your original e-mail so
I am CCing the list now so we keep the discussion here.
On Mon, 2015-10-05 at 08:07 +0200, Iago Toral wrote:
> Hi Markus,
>
> On Sun, 2015-10-04 at 18:15 +0200, Markus Wick wrote:
> > Hi Iago,
>
On Mon, 2015-10-05 at 13:08 +0300, Francisco Jerez wrote:
> Iago Toral Quiroga writes:
>
> > We need a virtual destructor when at least one of the class' methods is
> > virtual.
> > Failure to do so leads to undefined behavior when destructing derived
> &g
On Fri, 2015-10-02 at 17:43 -0400, Connor Abbott wrote:
> On Fri, Oct 2, 2015 at 5:37 PM, Connor Abbott wrote:
> > The heuristic we're using is rather lame, since it assumes everything is
> > non-uniform and loops execute 50 times, but it should be enough for
> > measuring improvements in the sche
Hi,
On Tue, 2015-09-29 at 09:25 +0200, Iago Toral Quiroga wrote:
> NIR is typeless so this is the only way to keep track of the
> type to select the proper atomic to use.
>
> v2:
> - Use imin,imax,umin,umax for the intrinsic names (Connor Abbott)
> - Change message for
x27;t very useful).
>
> While we're at it, improve the explanation in the comments.
>
> v2: Actually do what I said (caught by Ilia).
Reviewed-by: Iago Toral Quiroga
> Signed-off-by: Kenneth Graunke
> ---
> src/mesa/drivers/dri/i965/brw_vs.c | 12 +++-
> 1 fil
; - if (brw_is_front_buffer_reading(ctx->ReadBuffer)) {
> + if (_mesa_is_front_buffer_reading(ctx->ReadBuffer)) {
>struct brw_context *const brw = brw_context(ctx);
>
>/* If we might be front-buffer reading on this buffer for the first
> diff --git
; + if (ctx->Light.ShadeModel != GL_FLAT ||
> + !TNL_CONTEXT(ctx)->vb.AttribPtr[_TNL_ATTRIB_COLOR0]->stride) {
>LOCAL_VARS;
>const unsigned dmasz = GET_SUBSEQUENT_VB_MAX_VERTS() & ~1;
>unsigned currentsz;
> @@ -364,6 +356,8 @@ static void TAG(
/
> + const bool is_global_declaration = state->current_function == NULL;
> + if (state->es_shader &&
> + is_global_declaration &&
> + var->data.has_initializer &&
> + var->constant_initializer == NULL)
> + _mesa_glsl_error(&
Hi Ken,
I think this never got reviewed. Could you have a quick look at least to
patch 1? That looks like something we want to fix since we currently
have a hard-coded array size for 16 MRFs registers which won't do for
SNB.
Iago
On Tue, 2015-09-22 at 14:00 +0200, Iago Toral Quiroga
On Thu, 2015-10-08 at 09:53 +1100, Timothy Arceri wrote:
> On Wed, 2015-10-07 at 09:21 +0200, Samuel Iglesias Gonsalvez wrote:
> > Return the number of values written.
> >
> > Signed-off-by: Samuel Iglesias Gonsalvez
>
> Reviewed-by: Timothy Arceri
>
> Are you guys going to split SSBO into the
On Thu, 2015-10-08 at 03:01 -0400, Ilia Mirkin wrote:
> On Thu, Oct 8, 2015 at 2:56 AM, Iago Toral wrote:
> > On Thu, 2015-10-08 at 09:53 +1100, Timothy Arceri wrote:
> >> On Wed, 2015-10-07 at 09:21 +0200, Samuel Iglesias Gonsalvez wrote:
> >> > Retur
> + for (i = 0; i < n; i++) {
> +GLuint z = (GLuint) (depthSpan[i] * scale);
> +assert(z <= 0xff);
> +dst[i] = (z << 8);
> + }
> + if (dstPacking->SwapBytes) {
> +_mesa_swap4( (GLuint
On Wed, 2015-10-07 at 14:34 -0700, Ian Romanick wrote:
> From: Ian Romanick
>
> Right now we're also setting for uniforms, and that doesn't seem to hurt
> things. The next patch will make general global variables in GLSL ES,
> and those definitely should not have constant_value set!
I think thi
On Wed, 2015-10-07 at 14:34 -0700, Ian Romanick wrote:
> From: Ian Romanick
>
> Fixes:
> ES3-CTS.shaders.negative.constant_sequence
>
> spec/glsl-es-3.00/compiler/global-initializer/from-sequence.vert
> spec/glsl-es-3.00/compiler/global-initializer/from-sequence.frag
>
> Signed-off-
Well, this is weird this patch makes this crash:
INTEL_DEBUG=vs glxgears
because that uses a vertex program, so &vs->base is a NULL pointer
dereference in this call:
brw_dump_ir("vertex", prog, &vs->base, &vp->program.Base);
The surprising part is that this is the same without this patch (!
On Thu, 2015-10-08 at 12:32 +0100, Chris Wilson wrote:
> On Thu, Oct 08, 2015 at 01:23:27PM +0200, Iago Toral wrote:
> > Well, this is weird this patch makes this crash:
> >
> > INTEL_DEBUG=vs glxgears
> >
> > because that uses a vertex program, so &vs-&g
Moe than moving, this patch is duplicating it... wouldn't it be better
if we moved it for real? Seems like it would only be a matter of adding
#include "util/debug.h" s/driParseDebugString/parse_debug_string/ in the
following files:
./src/mesa/drivers/dri/radeon/radeon_debug.c
./src/mesa/drivers/d
n.c
> > +++ b/src/mesa/drivers/dri/i965/intel_screen.c
> > @@ -1421,7 +1421,19 @@ __DRIconfig **intelInitScreen2(__DRIscreen *psp)
> > if (!intelScreen->devinfo)
> >return false;
> >
> > - brw_process_intel_debug_variable(intelScreen);
> >
On Thu, 2015-10-08 at 11:19 -0700, Kristian Høgsberg wrote:
> On Thu, Oct 8, 2015 at 4:42 AM, Iago Toral wrote:
> > On Thu, 2015-10-08 at 12:32 +0100, Chris Wilson wrote:
> >> On Thu, Oct 08, 2015 at 01:23:27PM +0200, Iago Toral wrote:
> >> > Well, this is weird..
On Fri, 2015-10-09 at 08:36 +0100, Chris Wilson wrote:
> On Fri, Oct 09, 2015 at 08:09:20AM +0200, Iago Toral Quiroga wrote:
> > For the VS and FS stages that use ARB_vertex_program or
> > ARB_fragment_program we don't have a shader program, however,
> > when de
Hi Jason,
On Thu, 2015-10-01 at 18:50 -0700, Jason Ekstrand wrote:
> This commit also adds code to glsl_to_nir and prog_to_nir to fill it out.
> ---
> src/glsl/nir/glsl_to_nir.cpp | 18 ++
> src/glsl/nir/nir.c | 1 +
> src/glsl/nir/nir.h | 34 ++
On Fri, 2015-10-09 at 15:23 +0200, Iago Toral Quiroga wrote:
> See the rationale for this in [1], no piglit regressions observed in my
> IvyBridge laptop.
>
> Patch 1: Renames {Num}UniformBlocks to {Num}BufferInterfaceBlocks. This is
> more consistent with the current implementati
On Thu, 2015-12-31 at 11:20 -0800, Jordan Justen wrote:
> v2:
> * Fill UboInterfaceBlockIndex and SsboInterfaceBlockIndex in
>split_ubos_and_ssbos (Iago)
>
> Cc: Samuel Iglesias Gonsálvez
> Cc: Iago Toral
> Signed-off-by: Jordan Justen
> Reviewed-by: Juha-Pekk
i?id=93322
> Cc: Samuel Iglesias Gonsálvez
> Cc: Iago Toral
> Cc: Tapani Pälli
> Signed-off-by: Jordan Justen
> Reviewed-by: Juha-Pekka Heikkila
Reviewed-by: Iago Toral Quiroga
> ---
>
> Notes:
> Maybe the GL_ARB_program_interface_query support code should
#x27;options->lower_bitfield_insert'),
> + (('uadd_carry', a, b), ('ult', ('iadd', a, b), a),
> 'options->lower_uadd_carry'),
> + (('usub_borrow', a, b), ('ult', a, b), 'options->lower_usub_borrow
Reviewed-by: Iago Toral Quiroga
On Wed, 2016-01-06 at 15:30 -0800, Jason Ekstrand wrote:
> We don't need these for GLSL or ARB, but we need them for SPIR-V
> ---
> src/mesa/drivers/dri/i965/brw_shader.cpp | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/sr
Reviewed-by: Iago Toral Quiroga
On Mon, 2016-01-11 at 09:36 -0800, Matt Turner wrote:
> ---
> .../drivers/dri/i965/brw_fs_combine_constants.cpp | 21
> -
> 1 file changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/src/mes
Reviewed-by: Iago Toral Quiroga
On Mon, 2016-01-11 at 14:48 -0800, Matt Turner wrote:
> NIR's bfm, like Intel/AMD's hardware instructions and GLSL IR's
> ir_binop_bfm takes as src0 and as src1.
> ---
> src/glsl/nir/nir_opcodes.py | 2 +-
> 1 file chang
On Mon, 2016-01-11 at 09:36 -0800, Matt Turner wrote:
> A shader in Unreal4 uses the result of divide by zero in its color
> output, producing NaN and triggering this assertion since NaN is not
> equal to itself.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93560
> ---
> src/mesa/dr
Makes sense,
Reviewed-by: Iago Toral Quiroga
On Mon, 2016-01-11 at 16:15 -0800, Kenneth Graunke wrote:
> .length() on an unsized SSBO variable doesn't actually read any data
> from the SSBO, and is allowed on variables marked 'writeonly'.
>
> Fixes compute shad
Looks good to me, FWIW I built radeonsi and llvmpipe with this change
just in case and I saw no issues.
Reviewed-by: Iago Toral Quiroga
On Mon, 2016-01-11 at 14:48 -0800, Matt Turner wrote:
> From: Kenneth Graunke
>
> TGSI doesn't use these - it just translates ir_quadop_b
On Tue, 2016-01-12 at 10:29 -0500, Ilia Mirkin wrote:
> IIRC this should come out as b2i + i2d. You should be able to test
> this with llvmpipe/softpipe, which support fp64.
I see, thanks for the quick reply, I'll check this on intel.
Iago
> On Jan 12, 2016 9:49 AM, "
On Tue, 2016-01-12 at 11:53 -0800, Matt Turner wrote:
> On Tue, Jan 12, 2016 at 1:41 AM, Iago Toral wrote:
> > On Mon, 2016-01-11 at 09:36 -0800, Matt Turner wrote:
> >> A shader in Unreal4 uses the result of divide by zero in its color
> >> output, producing NaN an
On Tue, 2016-01-12 at 12:41 -0500, Ilia Mirkin wrote:
> On Tue, Jan 12, 2016 at 12:33 PM, Ian Romanick wrote:
> > On 01/12/2016 07:29 AM, Ilia Mirkin wrote:
> >> IIRC this should come out as b2i + i2d. You should be able to test this
> >> with llvmpipe/softpipe, which support fp64.
> >
> > Either
Reviewed-by: Iago Toral Quiroga
On Mon, 2016-01-18 at 06:02 -0800, Kenneth Graunke wrote:
> I have a patch that writes shaders as .shader_test files, and it uses
> this function to create the headers (i.e. [vertex shader]).
>
> [tess ctrl shader] isn't a valid shader_run
e intrinsics.
This patch is
Reviewed-by: Iago Toral Quiroga
It does not add the NIR implementation so if someone wants to use this
with NIR we will have to add the glsl_to_nir code to read this last
parameter and update the ssbo intrinsics in NIR to include it as well.
Iago
> Signed-off-
extract the specific
field access information from there instead.
>
> Signed-off-by: Ilia Mirkin
> Reviewed-by: Marek Olšák (v1)
> Reviewed-by: Iago Toral Quiroga (v1)
>
> v1 -> v2: add tracking of struct field
> ---
>
> (Only resent these two patches... not t
On Tue, 2016-01-19 at 01:50 -0500, Ilia Mirkin wrote:
> Interfaces can have image properties set in case they are buffer
> interfaces. Make sure not to lose this information.
Looks good to me,
Reviewed-by: Iago Toral Quiroga
> Signed-off-by: Ilia Mirkin
> ---
> src/glsl/builti
You probably want to get confirmation from others before pushing this
since I imagine that re-enabling blend_func for Unigine affects other
drivers as well, but from my side at least this is:
Reviewed-by: Iago Toral Quiroga
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=922
Right, we had to do the same for buffer variables to prevent losing
writes to the underlying buffer.
Reviewed-by: Iago Toral Quiroga
On Thu, 2016-01-21 at 16:47 -0800, Jordan Justen wrote:
> Fixes: dEQP-GLES31.functional.compute.basic.shared_atomic_op_multiple_groups
>
> Fr
Reviewed-by: Iago Toral Quiroga
On Thu, 2016-01-21 at 23:35 -0800, Jordan Justen wrote:
> Signed-off-by: Jordan Justen
> ---
>
> I tested a release build. I think v1 produced comparable code to
> before the patch, but it was a bit larger. I found that this v2 code
> would
On Sun, 2016-01-24 at 11:46 -0500, Ilia Mirkin wrote:
> On Thu, Jan 21, 2016 at 3:27 AM, Iago Toral wrote:
> >> *offset = new(mem_ctx) ir_constant(0u);
> >> *row_major = is_dereferenced_thing_row_major(deref);
> >> *matrix_columns
Reviewed-by: Iago Toral Quiroga
On Sun, 2016-01-24 at 13:59 -0500, Ilia Mirkin wrote:
> Currently any access params (coherent/volatile/restrict) are being lost
> when lowering to the ssbo load/store intrinsics. Keep track of the
> variable being used, and bake its access params in as
Patches 1 to 4 are,
Reviewed-by: Iago Toral Quiroga
I intend to review the remaining patches tomorrow as well if nobody else
beats me to it.
Iago
On Mon, 2016-01-25 at 15:18 -0800, Matt Turner wrote:
> This series adds NIR support for lowering pack/unpack opcodes and
> switches i965 o
I think it would be a good idea to change the shortlog so it is clear
that we are only talking about the scalarization aspect. There is still
GLSL IR lowering for un/packHalf2x16 that remains in use after this
patch, as made clear by the last hunk in this patch.
On Mon, 2016-01-25 at 15:18 -0800,
Eric said he would like to keep these opcodes so I guess we don't want
to do this. In any case this is:
Reviewed-by: Iago Toral Quiroga
On Mon, 2016-01-25 at 15:18 -0800, Matt Turner wrote:
> i965/fs was the only consumer, and we're now doing the lowering in NIR.
> ---
&g
242,6 +242,22 @@ optimizations = [
> ('bcsel', ('ult', 31, 'bits'), 'value',
>('ubfe', 'value', 'offset', 'bits')),
> 'options->lower_bitfield_extract'),
> +
> + (('
Reviewed-by: Iago Toral Quiroga
On Mon, 2016-01-25 at 15:18 -0800, Matt Turner wrote:
> The vec4 backend will lower it.
> ---
> src/mesa/drivers/dri/i965/brw_defines.h| 12
> src/mesa/drivers/dri/i965/brw_fs_cse.cpp | 2 ++
> src/mesa/d
On Wed, 2016-01-27 at 12:29 -0800, Matt Turner wrote:
> On Wed, Jan 27, 2016 at 5:22 AM, Iago Toral wrote:
> > I think it would be a good idea to change the shortlog so it is clear
> > that we are only talking about the scalarization aspect. There is still
> > GLSL IR lowerin
On Mon, 2016-01-25 at 15:18 -0800, Matt Turner wrote:
> ---
> src/glsl/nir/nir.h | 4
> src/glsl/nir/nir_lower_alu_to_scalar.c | 32
> src/glsl/nir/nir_opcodes.py| 10 ++
> src/glsl/nir/nir_opt_algebraic.py | 20 ++
On Mon, 2016-01-25 at 15:18 -0800, Matt Turner wrote:
> ---
> src/glsl/nir/nir.h| 4
> src/glsl/nir/nir_opt_algebraic.py | 28
> 2 files changed, 32 insertions(+)
>
> diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
> index bbd5b1a..3b90b51 1
Reviewed-by: Iago Toral Quiroga
On Mon, 2016-01-25 at 15:18 -0800, Matt Turner wrote:
> And mark nir_op_pack_uvec4_to_uint unreachable, since it's only produced
> by lowering pack[SU]norm4x8 which the vec4 backend does not need.
> ---
> src/mesa/drivers/dri/i965/brw_
601 - 700 of 3167 matches
Mail list logo
