[Mesa-dev] [PATCH] nir: cleanup oversized arrays in nir_swizzle calls

There are no fixed sized array arguments in C, those are simply pointers to unsized arrays and as the size is passed in anyway, just rely on that. where possible calls are replaced by nir_channel and nir_channels. Signed-off-by: Karol Herbst --- src/amd/vulkan/radv_meta_blit2d.c | 9

Re: [Mesa-dev] [PATCH] nir: cleanup oversized arrays in nir_swizzle calls

On Fri, Jul 13, 2018 at 4:04 AM, Jason Ekstrand wrote: > On Thu, Jul 12, 2018 at 6:48 PM Karol Herbst wrote: >> >> There are no fixed sized array arguments in C, those are simply pointers >> to unsized arrays and as the size is passed in anyway, just rely on that. >&

[Mesa-dev] [PATCH 2/6] nir/spirv: implement BuiltInWorkDim

From: Rob Clark Signed-off-by: Karol Herbst --- src/compiler/nir/nir.c | 2 ++ src/compiler/nir/nir_intrinsics.py | 1 + src/compiler/shader_enums.c| 1 + src/compiler/shader_enums.h| 1 + src/compiler/spirv/vtn_variables.c | 4 5 files changed, 9 insertions

[Mesa-dev] [PATCH 6/6] nir/spirv: handle functions with scalar and vector params

Signed-off-by: Karol Herbst --- src/compiler/spirv/vtn_cfg.c | 25 ++--- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/src/compiler/spirv/vtn_cfg.c b/src/compiler/spirv/vtn_cfg.c index ed1ab5d1c2c..2b01ede6f81 100644 --- a/src/compiler/spirv/vtn_cfg.c +++ b

[Mesa-dev] [PATCH 0/6] More OpenCL preparation for nir

This time all of the patches can be reviewed independently. Karol Herbst (5): nir/spirv: print id for unsupported builtins nir: add builtin builder nir: fix printing of vec16 type nir: prepare for bumping up max components to 16 nir/spirv: handle functions with scalar and vector params

[Mesa-dev] [PATCH 1/6] nir/spirv: print id for unsupported builtins

Signed-off-by: Karol Herbst --- src/compiler/spirv/vtn_variables.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/compiler/spirv/vtn_variables.c b/src/compiler/spirv/vtn_variables.c index c86416495b6..67b4d59b9fe 100644 --- a/src/compiler/spirv/vtn_variables.c +++ b/src

[Mesa-dev] [PATCH 4/6] nir: fix printing of vec16 type

Fixes: 2f181c8c183cc8b4d0450789bb20c2be48d32db3 "glsl_types: vec8/vec16 support" Signed-off-by: Karol Herbst --- src/compiler/nir/nir_print.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/nir/nir_print.c b/src/compiler/nir/nir_print.c index 18860db0058..4

[Mesa-dev] [PATCH 0/6] Some trivial patches for OpenCL support in vtn

most of the patches can be reviewed independently, this are just some smaller patches I think we can upstream already. Karol Herbst (4): compiler: add missing entries to gl_system_value_name nir: move lowering of SYSTEM_VALUE_LOCAL_GROUP_SIZE into a function nir/vtn: implement

[Mesa-dev] [PATCH 1/6] nir/vtn: Use imov where we might have 8 bit types

From: Rob Clark Otherwise nir_validate may complain about 8 bit floats, which do not exist. Reviewed-by: Karol Herbst Signed-off-by: Karol Herbst --- src/compiler/spirv/spirv_to_nir.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/spirv_to_nir.c b

[Mesa-dev] [PATCH 5/6] nir/vtn: implement BuiltInGlobalSize

Signed-off-by: Karol Herbst --- src/compiler/nir/nir_lower_system_values.c | 7 +++ src/compiler/shader_enums.c| 1 + src/compiler/shader_enums.h| 1 + src/compiler/spirv/vtn_variables.c | 4 4 files changed, 13 insertions(+) diff --git a/src

[Mesa-dev] [PATCH 2/6] nir/vtn: print extension name in fail msg

From: Rob Clark Reviewed-by: Karol Herbst Signed-off-by: Karol Herbst --- src/compiler/spirv/spirv_to_nir.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index aad4c713f9e..413fbf481c1 100644

[Mesa-dev] [PATCH 4/6] nir: move lowering of SYSTEM_VALUE_LOCAL_GROUP_SIZE into a function

we already have this code duplicated and we will need it for the global group size as well Signed-off-by: Karol Herbst --- src/compiler/nir/nir_lower_system_values.c | 29 +++--- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/src/compiler/nir

[Mesa-dev] [PATCH 6/6] vtn: handle OpConstantComposites with OpUndef members

Signed-off-by: Karol Herbst --- src/compiler/spirv/spirv_to_nir.c | 15 +-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index 413fbf481c1..235003e872a 100644 --- a/src/compiler/spirv

[Mesa-dev] [PATCH 3/6] compiler: add missing entries to gl_system_value_name

also reorder to match the gl_system_value enum. It is weird that the STATIC_ASSERT doesn't trigger though. Signed-off-by: Karol Herbst --- src/compiler/shader_enums.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/compiler/shader_enums.c b/src/compiler

[Mesa-dev] [PATCH 5/6] nir: prepare for bumping up max components to 16

OpenCL knows vector of size 8 and 16. Signed-off-by: Karol Herbst --- src/compiler/nir/nir.c| 14 src/compiler/nir/nir.h| 34 ++- src/compiler/nir/nir_builder.h| 18 ++ src/compiler/nir

[Mesa-dev] [PATCH 3/6] nir: add builtin builder

also move some of the GLSL builtins over we will need for implementing some OpenCL builtins Signed-off-by: Karol Herbst --- src/compiler/Makefile.sources | 2 + src/compiler/nir/meson.build | 2 + src/compiler/nir/nir_builtin_builder.c | 67 ++ src

Re: [Mesa-dev] [PATCH v2] nvc0: implement multisampled images on Maxwell+

it passes all the CTS tests, which is good :) Thanks! Reviewed-by: Karol Herbst On Wed, Jul 4, 2018 at 11:21 AM, Rhys Perry wrote: > Changes in v2: > - make loadSuInfo32() protected without making the rest protected > - move NVC0_SU_INFO_* into nv50_ir_lowering_nvc0.h instead of du

Re: [Mesa-dev] [PATCH v2 00/22] Introducing SPIR-V support to clover

On Tue, Jan 23, 2018 at 11:46 PM, Francisco Jerez <curroje...@riseup.net> wrote: > Pierre Moreau <pierre.mor...@free.fr> writes: > >> On 2018-01-23 — 14:02, Francisco Jerez wrote: >>> Karol Herbst <kher...@redhat.com> writes: >>> >>> > th

Re: [Mesa-dev] [PATCH v4 20/20] clover: Implement clCreateProgramWithIL from OpenCL 2.1

Reviewed-by: Karol Herbst <kher...@redhat.com> On Thu, Mar 8, 2018 at 1:21 AM, Pierre Moreau <pierre.mor...@free.fr> wrote: > Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> > --- > > Notes: > v3: Remove the const from the length argument of clCre

Re: [Mesa-dev] [PATCH v4 19/20] clover: Advertise cl_khr_il_program

Reviewed-by: Karol Herbst <kher...@redhat.com> On Thu, Mar 8, 2018 at 1:21 AM, Pierre Moreau <pierre.mor...@free.fr> wrote: > Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> > --- > > Notes: > Changes in v4: do not advertise SPIR-V support if CLO

Re: [Mesa-dev] [PATCH v4 04/20] clover: Remove the TGSI backend as unused

Reviewed-by: Karol Herbst <kher...@redhat.com> On Thu, Mar 8, 2018 at 1:21 AM, Pierre Moreau <pierre.mor...@free.fr> wrote: > Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> > --- > src/gallium/state_trackers/clover/Makefile.am | 11 +- > src

Re: [Mesa-dev] [PATCH v4 13/20] configure.ac, meson: Check for SPIRV-Tools and llvm-spirv

I think it would be valuable to put some comment on what kind of llvm-spirv we really need. I know the situation isn't perfect. Link to your branch or something should be good enough. With that: Reviewed-by: Karol Herbst <kher...@redhat.com> On Thu, Mar 8, 2018 at 1:21 AM, Pierre

Re: [Mesa-dev] [PATCH v4 18/20] clover/api: Implement CL_DEVICE_IL_VERSION

Reviewed-by: Karol Herbst <kher...@redhat.com> On Thu, Mar 8, 2018 at 1:21 AM, Pierre Moreau <pierre.mor...@free.fr> wrote: > Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> > --- > > Notes: > Changes in v4: Use the core define instead of the extension

Re: [Mesa-dev] [PATCH v4 05/20] clover: Add an helper for checking if an IR is supported

Reviewed-by: Karol Herbst <kher...@redhat.com> On Thu, Mar 8, 2018 at 1:21 AM, Pierre Moreau <pierre.mor...@free.fr> wrote: > Reviewed-by: Aaron Watry <awa...@gmail.com> > Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> > --- > > Notes: > v3:

Re: [Mesa-dev] [PATCH v4 06/20] clover/device: Replace usage of "1 << PIPE_SHADER_IR_*" with supports_ir

Reviewed-by: Karol Herbst <kher...@redhat.com> On Thu, Mar 8, 2018 at 1:21 AM, Pierre Moreau <pierre.mor...@free.fr> wrote: > Reviewed-by: Aaron Watry <awa...@gmail.com> > Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> > --- > src/gallium/state

Re: [Mesa-dev] [PATCH 05/13] nir: expose 'C' wrappers for std430 size/alignment

it isn't yet. But you would use it in your driver when calculating your memory offsets for kernel arguments. In OpenCL things are aligned in memory by the size of the type and we would use those functions to calculate those. On Wed, Feb 28, 2018 at 10:39 PM, Jason Ekstrand

Re: [Mesa-dev] [PATCH 01/13] nir: allow 64 bit shifts

; you want. We picked 32 because it's been the GL default for a long time. > Well the thing is we ended up with a shift in spirv having two 64 bit parameters. Maybe we could just put a convert in it for such cases? > On Wed, Feb 28, 2018 at 11:51 AM, Rob Clark <robdcl...@gmail.

Re: [Mesa-dev] [PATCH 05/13] nir: expose 'C' wrappers for std430 size/alignment

true, then std430 is not what you want. >> >> On Wed, Feb 28, 2018 at 1:44 PM, Karol Herbst <kher...@redhat.com> wrote: >>> >>> it isn't yet. But you would use it in your driver when calculating >>> your memory offsets for kernel arguments. In OpenCL t

Re: [Mesa-dev] [PATCH 0/5] Fix meson omx compilation

Tested-by: Karol Herbst <kher...@redhat.com> On Wed, Mar 7, 2018 at 3:38 PM, Julien Isorce <julien.iso...@gmail.com> wrote: > Thanks a lot for the fixes. > There is small issue, if fails to build with meson with 'auto' if tizonia is > installed but not bellagio because E

[Mesa-dev] [PATCH v2 01/18] compiler: int8/uint8 support

OpenCL kernels also have int8/uint8. v2: remove changes in nir_search as Jason posted a patch for that Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> Signed-off-by: Rob Clark <robdcl...@gmail.com> Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/bui

[Mesa-dev] [PATCH v2 02/18] nir/vtn: Use imov where we might have 8 bit types

From: Rob Clark <robdcl...@gmail.com> Otherwise nir_validate may complain about 8 bit floats, which do not exist. Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/spirv/spirv_to_nir.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/co

[Mesa-dev] [PATCH v2 05/18] nir: add load/store_global intrinsics

on the memory model). Signed-off-by: Rob Clark <robdcl...@gmail.com> Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/nir/nir_intrinsics.h | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/compiler/nir/nir_intrinsics.h b/src/

[Mesa-dev] [PATCH v2 03/18] vtn: handle SpvExecutionModelKernel

Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/spirv/spirv_to_nir.c | 3 +++ src/compiler/spirv/vtn_private.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index 48ade2c1ca..c5c4da853e

[Mesa-dev] [PATCH v2 04/18] nir: kernel entrypoints can have arguments

From: Rob Clark <robdcl...@gmail.com> This assert is not valid for OpenCL kernels. TODO can we somehow conditionally assert based on glsl vs cl?? Signed-off-by: Rob Clark <robdcl...@gmail.com> Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/nir/nir.h | 1 -

[Mesa-dev] [PATCH v2 10/18] nir/vtn: print extension name in fail msg

From: Rob Clark <robdcl...@gmail.com> Signed-off-by: Rob Clark <robdcl...@gmail.com> Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/spirv/spirv_to_nir.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/spirv_to_nir

[Mesa-dev] [PATCH v2 11/18] nir/vtn: implement BuiltInGlobalSize

Signed-off-by: Rob Clark <robdcl...@gmail.com> Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/nir/nir_lower_system_values.c | 8 src/compiler/shader_enums.c| 1 + src/compiler/shader_enums.h| 2 ++ src/compiler/spirv/vtn

[Mesa-dev] [PATCH v2 07/18] nir/vtn: handle WorkGroupSize for kernels

From: Rob Clark <robdcl...@gmail.com> Unlike glsl/vk compute shaders, this isn't a builtin constant. Signed-off-by: Rob Clark <robdcl...@gmail.com> Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/spirv/vtn_variables.c | 6 +++--- 1 file changed, 3 insertio

[Mesa-dev] [PATCH v2 08/18] nir/vtn: add OpLifetime*

From: Rob Clark <robdcl...@gmail.com> These are just hints so we can ignore them. Signed-off-by: Rob Clark <robdcl...@gmail.com> Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/spirv/spirv_to_nir.c | 4 1 file changed, 4 insertions(+) diff --git a/

[Mesa-dev] [PATCH v2 16/18] RFC glsl: add cl_size and cl_alignment

Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/glsl_types.cpp | 48 + src/compiler/glsl_types.h | 10 ++ src/compiler/nir_types.cpp | 12 src/compiler/nir_types.h| 4 4 files changed, 74 inse

[Mesa-dev] [PATCH v2 12/18] nir: use load_local_group_size

From: Rob Clark <robdcl...@gmail.com> If local_size is not known at compile time, which is the case with clover, use the load_local_group_size intrinsic instead. Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/nir/nir_lower_system_values.c | 23 ---

[Mesa-dev] [PATCH v2 15/18] glsl: add glsl_base_get_byte_size

Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/glsl_types.h | 34 ++ src/compiler/nir_types.h | 30 +- 2 files changed, 35 insertions(+), 29 deletions(-) diff --git a/src/compiler/glsl_types.h b/src/co

[Mesa-dev] [PATCH v2 13/18] RFC: nir/vtn: "raw" pointer support

ed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/spirv/spirv_to_nir.c | 77 ++ src/compiler/spirv/vtn_private.h | 19 +++- src/compiler/spirv/vtn_variables.c | 208 + 3 files changed, 264 insertions(+), 40 deletions(-) diff

[Mesa-dev] [PATCH v2 09/18] nir/vtn: add OpConvertPtrToU

From: Rob Clark <robdcl...@gmail.com> Signed-off-by: Rob Clark <robdcl...@gmail.com> Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/spirv/vtn_alu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.

[Mesa-dev] [PATCH v2 14/18] glsl: add packed for struct types

We need this for OpenCL kernels because we have to apply C rules for alignment and padding inside structs and for this we also have to know if a struct is packed or not. Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/glsl_types.cpp | 17 +++-- src/co

[Mesa-dev] [PATCH v2 17/18] nir: add load_kernel_param

OpenCL kernels have parameters (see pipe_grid_info::input), and so we need a way to access them. The offset source is the offset of the parameter to load in the kernel input buffer. v2: improve commit message remove BASE split lower_io changes into separate commit Signed-off-by: Karol

[Mesa-dev] [PATCH v2 18/18] RFC nir/lower_io: lower kernel entry param load_vars to load_kernel_param

functions. Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/nir/nir_lower_io.c | 39 --- 1 file changed, 36 insertions(+), 3 deletions(-) diff --git a/src/compiler/nir/nir_lower_io.c b/src/compiler/nir/nir_lower_io.c index df91febd68..ed8e361651

[Mesa-dev] [PATCH v2 06/18] nir/vtn: implement SpvOpCopyMemorySized

From: Rob Clark <robdcl...@gmail.com> I think a new intrinsic is the easiest way to do this. We can lower this to a sequence of load/stores after vtn. Signed-off-by: Rob Clark <robdcl...@gmail.com> Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/nir/nir_

[Mesa-dev] [PATCH v2 00/18] nir/vtn/compiler: first batch of compute support

source. Rob still wants to rework his pointer support patch afaik. One of the biggest problems we currently have is handling of pointers into Function Memory to load struct members. Karol Herbst (9): compiler: int8/uint8 support vtn: handle SpvExecutionModelKernel nir: add load/store_global

Re: [Mesa-dev] [PATCH v2] nv50/ir: make a copy of tex src if it's referenced multiple times

I guess this fixes a bug somewhere? On Tue, Apr 10, 2018 at 6:11 AM, Ilia Mirkin wrote: > For nv50 we coalesce the srcs and defs into a single node. As such, we > can end up with impossible constraints if the source is referenced > after the tex operation (which, due to the

[Mesa-dev] [PATCH] glsl: properly handle bindless sampler and image parameters

fixes a piglit test I sent to the list: spec@arb_bindless_texture@execution@samplers@basic-arithmetic-func-call-uvec2-texture2D Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/glsl/opt_function_inlining.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[Mesa-dev] [PATCH v2 2/3] nir: add support for bindless_texture samplers

v2: add both texture and sampler handles Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/glsl/glsl_to_nir.cpp | 17 +++-- src/compiler/nir/nir.h| 2 ++ src/compiler/nir/nir_print.c | 6 ++ 3 files changed, 23 insertions(+), 2 del

[Mesa-dev] [PATCH v2 3/3] glsl/nir: fix variable type for image intrinsics and ubos

If the bindless image is passed through a struct we ended up getting the glsl_type of the struct, not the image. variable_referenced points to the declaration of the struct, so it won't work for bindless images. So just drop it. Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/co

[Mesa-dev] [PATCH v2 0/3] nir: add support for ARB_bindless_texture texture handles

With this it should be possible to add support for texture handles for backends using NIR. changes since v2: * dropped patch for image handles, still need to work on that Karol Herbst (3): nir/split_var_copies: handle IMAGE and SAMPLER for bindless vars nir: add support for bindless_texture

[Mesa-dev] [PATCH v2 1/3] nir/split_var_copies: handle IMAGE and SAMPLER for bindless vars

v2: fix assertion for bindless to non bindless assignments Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/nir/nir_split_var_copies.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/compiler/nir/nir_split_var_copies.c b/src/compil

Re: [Mesa-dev] [PATCH v2 1/3] nir/split_var_copies: handle IMAGE and SAMPLER for bindless vars

and things just seem to work out. I wasn't able to hit any other issues. > On Tue, Apr 10, 2018 at 8:05 AM, Karol Herbst <kher...@redhat.com> wrote: >> >> v2: fix assertion for bindless to non bindless assignments >> >> Signed-off-by: Karol Herbst

Re: [Mesa-dev] [PATCH v2 3/3] glsl/nir: fix variable type for image intrinsics and ubos

On Tue, Apr 10, 2018 at 5:11 PM, Jason Ekstrand <ja...@jlekstrand.net> wrote: > On Tue, Apr 10, 2018 at 8:05 AM, Karol Herbst <kher...@redhat.com> wrote: >> >> If the bindless image is passed through a struct we ended up getting the >> glsl_

Re: [Mesa-dev] [PATCH v2 1/3] nir/split_var_copies: handle IMAGE and SAMPLER for bindless vars

On Tue, Apr 10, 2018 at 6:01 PM, Jason Ekstrand <ja...@jlekstrand.net> wrote: > On Tue, Apr 10, 2018 at 8:35 AM, Karol Herbst <kher...@redhat.com> wrote: >> >> On Tue, Apr 10, 2018 at 5:12 PM, Jason Ekstrand <ja...@jlekstrand.net> >> wrote: >> >

Re: [Mesa-dev] [PATCH 2/4] nir: add support for bindless_texture samplers

On Wed, Apr 4, 2018 at 2:16 AM, Jason Ekstrand <ja...@jlekstrand.net> wrote: > On Tue, Apr 3, 2018 at 6:21 AM, Karol Herbst <kher...@redhat.com> wrote: >> >> Signed-off-by: Karol Herbst <kher...@redhat.com> >> --- >> src/compiler/glsl/glsl_to_nir.cp

Re: [Mesa-dev] [PATCH 1/4] nir/split_var_copies: handle IMAGE and SAMPLER for bindless vars

the crashes I encounter there at least. More piglit tests might be useful as well. Sadly I don't see any bindless_textures tests in the CTS :( > > On Tue, Apr 3, 2018 at 6:21 AM, Karol Herbst <kher...@redhat.com> wrote: >> >> Signed-off-by: Karol Herbst <kher...@redhat.com>

Re: [Mesa-dev] [PATCH v2 2/3] nir: add support for bindless_texture samplers

On Tue, Apr 10, 2018 at 5:10 PM, Jason Ekstrand <ja...@jlekstrand.net> wrote: > On Tue, Apr 10, 2018 at 8:05 AM, Karol Herbst <kher...@redhat.com> wrote: >> >> v2: add both texture and sampler handles >> >> Signed-off-by: Karol Herbst <kher..

Re: [Mesa-dev] [PATCH v2 2/3] nir: add support for bindless_texture samplers

On Thu, Apr 12, 2018 at 6:33 PM, Jason Ekstrand <ja...@jlekstrand.net> wrote: > On Thu, Apr 12, 2018 at 7:36 AM, Karol Herbst <kher...@redhat.com> wrote: >> >> On Tue, Apr 10, 2018 at 5:10 PM, Jason Ekstrand <ja...@jlekstrand.net> >> wrote: >> > On

[Mesa-dev] [PATCH] RFC gallium: add 64 bit integer formats

I should add another flag for 64 bit ints. Or rework what Doubles mean in gl_array_attributes. Or Rename that to is64Bit and rework all users of Doubles. Any suggestions? Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/gallium/drivers/svga/svga_format.c | 8 src/gallium/i

Re: [Mesa-dev] [PATCH] RFC gallium: add 64 bit integer formats

On Tue, Apr 10, 2018 at 2:43 AM, Ilia Mirkin <imir...@alum.mit.edu> wrote: > On Mon, Apr 9, 2018 at 8:39 PM, Karol Herbst <kher...@redhat.com> wrote: >> unsigneds are needed by ARB_bindless_texture 64 bit vertex attribs, both for >> NV_vertex_attrib_integer64. >>

[Mesa-dev] [PATCH v7 09/35] nvir/nir: run some passes to make the conversion easier

v2: add constant_folding v6: print non final NIR only for verbose debugging Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 39 ++ 1 file changed, 39 insertions(+) diff --git a/src/gallium/drivers/nouveau/c

[Mesa-dev] [PATCH v7 25/35] nvir/nir: implement nir_instr_type_tex

reference in convert(glsl_sampler_dim&, bool, bool) fix tg4 component selection v5: fill up coords args with scratch values if coords provided is less than TexTarget.getArgCount() v7: prepare for bindless_texture support Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drive

[Mesa-dev] [PATCH v7 22/35] nvir/nir: implement intrinsic_discard(_if)

Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 14 ++ 1 file changed, 14 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_n

[Mesa-dev] [PATCH v7 34/35] nvir/nir: implement load_per_vertex_output

v4: use smarter getIndirect helper use new getSlotAddress helper v5: use loadFrom helper Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 23 ++ 1 file changed, 23 insertions(+) diff --git a/src/gallium/d

[Mesa-dev] [PATCH v7 23/35] nvir/nir: implement loading system values

v2: support more sys values fixed a bug where for multi component reads all values ended up in x v3: add load_patch_vertices_in v4: add subgroup stuff v5: add helper invocation v6: fix loading 64 bit system values Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/n

[Mesa-dev] [PATCH v7 21/35] nvir/nir: implement load_(interpolated_)input/output

-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 134 + 1 file changed, 134 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp

[Mesa-dev] [PATCH v7 31/35] nvir/nir: implement ssbo intrinsics

v4: use loadFrom helper v5: support indirect buffer access Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 90 ++ 1 file changed, 90 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_n

[Mesa-dev] [PATCH v7 19/35] nvir/nir: implement nir_intrinsic_load_uniform

v2: use new getIndirect helper fixes symbols for 64 bit types v4: use smarter getIndirect helper simplify address calculation use loadFrom helper Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 10 ++

[Mesa-dev] [PATCH v7 27/35] nvir/nir: implement vote and ballot

v2: add vote_eq support use the new subop intrinsic helper add ballot v3: add read_(first_)invocation Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 42 ++ 1 file changed, 42 insertions(+) diff --git

[Mesa-dev] [PATCH v7 20/35] nvir/nir: implement nir_intrinsic_store_(per_vertex_)output

v3: add workaround for RA issues indirects have to be multiplied by 0x10 fix indirect access v4: use smarter getIndirect helper use storeTo helper v5: don't use const_offset directly Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_n

[Mesa-dev] [PATCH v7 26/35] nvir/nir: add getOperation for intrinsics

v7: don't assert in default case Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 22 ++ 1 file changed, 22 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/d

[Mesa-dev] [PATCH v7 18/35] nvir/nir: implement nir_alu_instr handling

Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 489 - 1 file changed, 488 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/c

[Mesa-dev] [PATCH v7 35/35] nvir/nir: implement intrinsic shader_clock

Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 8 1 file changed, 8 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp

[Mesa-dev] [PATCH v7 32/35] nvir/nir: implement images

v3: fix compiler warnings v4: use loadFrom helper v5: fix signed min/max v6: set tex mask add support for indirect image access set cache mode v7: make compatible with 884d27bcf688d36c3bbe01bceca525595add3b33 rework the whole deref thing to prepare for bindless Signed-off-by: Karol

[Mesa-dev] [PATCH v7 17/35] nvir/nir: add skeleton for nir_intrinsic_instr

Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp| 17 + 1 file changed, 17 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_n

[Mesa-dev] [PATCH v7 28/35] nvir/nir: implement variable indexing

with indirects aren't guarenteed to be aligned to 0x10 anymore. v3: use fixed size vec4 arrays until we fix MemoryOpt v4: fix for 64 bit types v5: use loadFrom helper Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 58 +++

[Mesa-dev] [PATCH v7 29/35] nvir/nir: implement geometry shader nir_intrinsics

v4: use smarter getIndirect helper use new getSlotAddress helper use loadFrom helper Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 27 ++ 1 file changed, 27 insertions(+) diff --git a/src/gallium/d

[Mesa-dev] [PATCH v7 24/35] nvir/nir: implement nir_ssa_undef_instr

v2: use mkOp Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 13 + 1 file changed, 13 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/c

[Mesa-dev] [PATCH v7 30/35] nvir/nir: implement nir_intrinsic_load_ubo

v4: use loadFrom helper Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 14 ++ 1 file changed, 14 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/n

[Mesa-dev] [PATCH v7 33/35] nvir/nir: add memory barriers

v5: add more barrier intrinsics Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 19 +++ 1 file changed, 19 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/d

[Mesa-dev] [PATCH v7 04/35] nvir: move common converter code in base class

v2: remove TGSI related bits Signed-off-by: Karol Herbst <kher...@redhat.com> Reviewed-by: Pierre Moreau <pierre.mor...@free.fr> --- src/gallium/drivers/nouveau/Makefile.sources | 2 + .../nouveau/codegen/nv50_ir_from_common.cpp| 107 + .../dri

[Mesa-dev] [PATCH v7 06/35] nouveau: add support for nir

of the nir shader merge: use the lowering helper v6: include TGSI debug header for proper assert call add nv50 support v7: fix Automake build Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/gallium/drivers/nouveau/Automake.inc | 3 + src/gallium/drivers/n

[Mesa-dev] [PATCH v7 03/35] nvir: print the shader type when dumping headers

this makes debugging the shader header a little easier Signed-off-by: Karol Herbst <kher...@redhat.com> Acked-by: Pierre Moreau <pierre.mor...@free.fr> --- src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/

[Mesa-dev] [PATCH v7 00/35] Nouveau NIR support

follow up patches to add support for: * 4 constant offsets in TG4 * bindless_texture support for samplers and images Review is important for patches 1-8, all the other paches touch the from_nir file only. Connor Abbott (1): nv50/ir/ra: Fix copying compound for moves Karol Herbst (34): st

[Mesa-dev] [PATCH v7 02/35] nv50/ir/ra: Fix copying compound for moves

so we don't know which is which. I took the approach of calling copyCompound() inside coalesceValues(), instead of afterwards. Cc: Ilia Mirkin <imir...@alum.mit.edu> Cc: Karol Herbst <kher...@redhat.com> Tested-by: Karol Herbst <kher...@redhat.com> Signed-off-by: Karol Herbst <k

[Mesa-dev] [PATCH v7 12/35] nvir/nir: run assignSlots

getSlotAddress helper fix for 64 bit typed inputs v5: change getSlotAddress interface for easier use fix sample inputs fix slot counting for mat v7: fix driver_location of images Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp

[Mesa-dev] [PATCH v7 15/35] nvir/nir: implement CFG handling

v6: fix loops with blocks at the end nothing points to skip blocks with no instructions and no predecessors Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 270 - 1 file changed, 268 insertions(+), 2 del

[Mesa-dev] [PATCH v7 16/35] nvir/nir: implement nir_load_const_instr

Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 18 ++ 1 file changed, 18 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_n

[Mesa-dev] [PATCH v7 14/35] nvir/nir: parse NIR shader info

v2: parse a few more fields v3: add special handling for GL_ISOLINES Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 60 ++ 1 file changed, 60 insertions(+) diff --git a/src/gallium/drivers/nouveau/c

[Mesa-dev] [PATCH v7 05/35] nvir: add lowering helper

this is mostly usefull for lazy IR converters not wanting to deal with 64 bit lowering and other illegal stuff v5: also handle SAT v6: rename type variables fixed lowering of NEG add lowering of NOT Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/gallium/drivers/n

[Mesa-dev] [PATCH v7 11/35] nvir/nir: add nir type helper functions

v4: treat imul as unsigned v5: remove pointless !! v7: inot is unsigned as well Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 116 + 1 file changed, 116 insertions(+) diff --git a/src/gallium/drivers/nouveau/c

[Mesa-dev] [PATCH v7 10/35] nvir/nir: track defs and provide easy access functions

v2: add helper function for indirects v4: add new getIndirect overload for easier use v5: use getSSA for ssa values we can just create the values for unassigned registers in getSrc v6: always create at least 32 bit values Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../d

[Mesa-dev] [PATCH v7 08/35] nouveau: fix nir and TGSI shader cache collision

Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/gallium/drivers/nouveau/nouveau_screen.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/nouveau_screen.c b/src/gallium/drivers/nouveau/nouveau_screen.c index 2598c78a45b..655d2

[Mesa-dev] [PATCH v7 13/35] nvir/nir: add loadFrom and storeTo helpler

Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 72 ++ 1 file changed, 72 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_n

[Mesa-dev] [PATCH v7 01/35] st/glsl_to_nir: run lower_output_reads on !PIPE_CAP_TGSI_CAN_READ_OUTPUTS

this is required for Drivers which don't allow reading from outputs. Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com> Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/mesa/state_tracker/st_glsl_to_nir.cpp | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/mesa/s

[Mesa-dev] [PATCH v7 07/35] nouveau: add env var to make nir default

v2: allow for non debug builds as well v3: move reading out env var more global disable tg4 with multiple offsets with nir disable caps for 64 bit types v6: nv50 support disable MS images disable bindless textures Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/g

[Mesa-dev] [PATCH 2/3] nir: print 8 and 16 bit constants correctly

Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/nir/nir_print.c | 14 -- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/src/compiler/nir/nir_print.c b/src/compiler/nir/nir_print.c index 21f13097651..1c84b4b7076 100644 --- a/src/compil

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