[Mesa-dev] [PATCH 3/3] nir/opt_constant_folding: fix folding of 8 and 16 bit ints

Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/nir/nir_opt_constant_folding.c | 14 -- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/src/compiler/nir/nir_opt_constant_folding.c b/src/compiler/nir/nir_opt_constant_folding.c index d6be8

[Mesa-dev] [PATCH 0/3] Some 8/16 bit fixes for nir

I encountered those issues while testing OpenCL chars and shorts. Karol Herbst (3): nir: support converting to 8-bit integers in nir_type_conversion_op nir: print 8 and 16 bit constants correctly nir/opt_constant_folding: fix folding of 8 and 16 bit ints src/compiler/nir/nir_opcodes_c.py

[Mesa-dev] [PATCH 1/3] nir: support converting to 8-bit integers in nir_type_conversion_op

Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/nir/nir_opcodes_c.py | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/compiler/nir/nir_opcodes_c.py b/src/compiler/nir/nir_opcodes_c.py index c19185534af..8afccca9504 100644 --- a/src/compil

Re: [Mesa-dev] [PATCH 3/3] nir/opt_constant_folding: fix folding of 8 and 16 bit ints

don't have to wait. > So this is: > > Reviewed-by: Jose Maria Casanova Crespo <jmcasan...@igalia.com> > > El 25/04/18 a las 11:14, Karol Herbst escribió: >> Signed-off-by: Karol Herbst <kher...@redhat.com> >> --- >> src/compiler/nir/nir_opt_constant

[Mesa-dev] [PATCH] gm107/ir/lib: fix sched in div u32 builtin

Imad needs to set a read barrier. With significant big work groups I was getting wrong results for div u32. Turns out the issue was with the sched opcodes. CC: Samuel Pitoiset <samuel.pitoi...@gmail.com> Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/gallium/drivers/nou

[Mesa-dev] [PATCH] nvc0/ir: fix emiting NOTs with predicates

From: Karol Herbst <karolher...@gmail.com> Signed-off-by: Karol Herbst <karolher...@gmail.com> --- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gal

[Mesa-dev] [PATCH] nv50/ir: add more advanced slct constant folding code

From: Karol Herbst <karolher...@gmail.com> shader-db changes: total instructions in shared programs : 5894114 -> 5887031 (-0.12%) total gprs used in shared programs: 666558 -> 666514 (-0.01%) total shared used in shared programs : 520416 -> 520416 (0.00%) total local used in

Re: [Mesa-dev] [PATCH] nv50/ir: optimise slct(t, f, set) to mov(set) or not(set)

here we can use TGSI. > On 03/27/2018 01:50 PM, Karol Herbst wrote: >> From: Karol Herbst <karolher...@gmail.com> >> >> helps mainly Feral-ported games >> >> changes in shader-db: >> total instructions in shared programs : 3940749 -> 3935015 (-0.1

Re: [Mesa-dev] [PATCH] nv50/ir: optimise slct(t, f, set) to mov(set) or not(set)

just noticed I sent out the wrong version of that patch... On Tue, Mar 27, 2018 at 10:50 PM, Karol Herbst <kher...@redhat.com> wrote: > From: Karol Herbst <karolher...@gmail.com> > > helps mainly Feral-ported games > > changes in shader-db: > total instruction

Re: [Mesa-dev] [PATCH] nv50/ir: optimise slct(t, f, set) to mov(set) or not(set)

On Tue, Mar 27, 2018 at 11:04 PM, Ilia Mirkin <imir...@alum.mit.edu> wrote: > On Tue, Mar 27, 2018 at 4:50 PM, Karol Herbst <kher...@redhat.com> wrote: >> From: Karol Herbst <karolher...@gmail.com> >> >> helps mainly Feral-ported games >> >> ch

Re: [Mesa-dev] [PATCH] nvc0/ir: fix INTERP_* with indirect inputs

Reviewed-by: Karol Herbst <kher...@redhat.com> On Sat, Mar 24, 2018 at 8:19 PM, Ilia Mirkin <imir...@alum.mit.edu> wrote: > There were two problems, both of which are fixed now: > - The indirect address was not being shifted by 4 > - The indirect address was being

[Mesa-dev] [PATCH] nv50/ra: prefer def == src2 for mad/sad with immediates on nvc0

From: Karol Herbst <karolher...@gmail.com> This helps with the PostRALoadPropagation pass moving long immediates into FMA/MAD instructions. changes in shader-db: total instructions in shared programs : 5894114 -> 5886074 (-0.14%) total gprs used in shared programs: 666558 ->

Re: [Mesa-dev] [PATCH] nir: add support for 4 constant offsets in tg4

On Fri, Mar 30, 2018 at 9:35 PM, Eric Anholt <e...@anholt.net> wrote: > Karol Herbst <kher...@redhat.com> writes: > >> Nvidia hardware can do that natively so there is no need to lower that to >> four >> TG4s instructions. >> >> Signed-off-by:

[Mesa-dev] [PATCH] nir: add support for 4 constant offsets in tg4

Nvidia hardware can do that natively so there is no need to lower that to four TG4s instructions. Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/glsl/glsl_to_nir.cpp | 25 ++--- src/compiler/nir/nir.h| 9 - src/compiler/nir/nir_p

Re: [Mesa-dev] [PATCH] nvc0: drop image binding from BGR10A2 format

Did a CTS run on that. Things are looking better with it. No regressions. Tested-By: Karol Herbst <kher...@redhat.com> On Thu, Mar 29, 2018 at 5:47 AM, Ilia Mirkin <imir...@alum.mit.edu> wrote: > Fixes a bunch of new CTS pbo tests that use that as an output format, > which

Re: [Mesa-dev] [PATCH v5 18/21] clover: Handle CL_PROGRAM_IL in clGetProgramInfo

Reviewed-by: Karol Herbst <kher...@redhat.com> On Sun, Mar 25, 2018 at 8:02 PM, Pierre Moreau <pierre.mor...@free.fr> wrote: > Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> > --- > src/gallium/state_trackers/clover/api/program.cpp | 7 +++ > 1 file cha

Re: [Mesa-dev] [PATCH v3 06/19] RFC: nir/vtn: "raw" pointer support

On Sun, Mar 25, 2018 at 12:18 AM, Rob Clark <robdcl...@gmail.com> wrote: > On Fri, Mar 23, 2018 at 5:18 PM, Jason Ekstrand <ja...@jlekstrand.net> wrote: >> On Fri, Mar 23, 2018 at 2:15 PM, Karol Herbst <kher...@redhat.com> wrote: >>> >>> On Fri,

Re: [Mesa-dev] [PATCH v3 06/19] RFC: nir/vtn: "raw" pointer support

On Sun, Mar 25, 2018 at 2:18 PM, Rob Clark <robdcl...@gmail.com> wrote: > On Sun, Mar 25, 2018 at 6:35 AM, Karol Herbst <kher...@redhat.com> wrote: >> On Sun, Mar 25, 2018 at 12:18 AM, Rob Clark <robdcl...@gmail.com> wrote: >>> On Fri, Mar 23, 2018 at 5:18 PM,

[Mesa-dev] [PATCH 0/4] nir: add support for bindless_texture

I think most of the changes are straigh forward. The changes needed for images should be discussed, because in its current form it would require changing all drivers using nir and supporting images. Karol Herbst (4): nir/split_var_copies: handle IMAGE and SAMPLER for bindless vars nir: add

[Mesa-dev] [PATCH 4/4] RFC nir: add support for bindless_texture images

I added another source for all image_var_* intrinsics. Drivers have to be adjusted with this change. There was some discussion to add new intrinsics to handle operations on bindless images. Maybe we can continue with this here? Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/co

[Mesa-dev] [PATCH 3/4] glsl/nir: fix variable type for image intrinsics and ubos

If the bindless image is passed through a struct we ended up getting the glsl_type of the struct, not the image. variable_referenced points to the declaration of the struct, so it won't work for bindless images. So just drop it. Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/co

[Mesa-dev] [PATCH 2/4] nir: add support for bindless_texture samplers

Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/glsl/glsl_to_nir.cpp | 17 +++-- src/compiler/nir/nir.h| 1 + src/compiler/nir/nir_print.c | 3 +++ 3 files changed, 19 insertions(+), 2 deletions(-) diff --git a/src/compiler/glsl/glsl_to_nir.

[Mesa-dev] [PATCH 1/4] nir/split_var_copies: handle IMAGE and SAMPLER for bindless vars

Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/nir/nir_split_var_copies.c | 4 1 file changed, 4 insertions(+) diff --git a/src/compiler/nir/nir_split_var_copies.c b/src/compiler/nir/nir_split_var_copies.c index bc3ceedbdb8..231a89add4d 100644 --- a/src/compil

Re: [Mesa-dev] [PATCH 2/4] nir: add support for bindless_texture samplers

On Tue, Apr 3, 2018 at 3:21 PM, Karol Herbst <kher...@redhat.com> wrote: > Signed-off-by: Karol Herbst <kher...@redhat.com> > --- > src/compiler/glsl/glsl_to_nir.cpp | 17 +++-- > src/compiler/nir/nir.h| 1 + > src/compiler/nir/nir_print.c

[Mesa-dev] [PATCH] nv50/ir: optimise slct(t, f, set) to mov(set) or not(set)

From: Karol Herbst <karolher...@gmail.com> helps mainly Feral-ported games changes in shader-db: total instructions in shared programs : 3940749 -> 3935015 (-0.15%) total gprs used in shared programs: 481460 -> 481433 (-0.01%) total local used in shared programs : 27481 -&

Re: [Mesa-dev] [PATCH 2/2] gk110/ir: always use limm form for log ops with immediates

On Fri, Mar 16, 2018 at 11:10 PM, Ilia Mirkin <imir...@alum.mit.edu> wrote: > You got the subjects backwards. > > On Fri, Mar 16, 2018 at 6:05 PM, Karol Herbst <kher...@redhat.com> wrote: >> in the short imm form 0x8 was sign-extended to 0xfff8 which leads to >

[Mesa-dev] [PATCH 2/2] gk110/ir: always use limm form for log ops with immediates

in the short imm form 0x8 was sign-extended to 0xfff8 which leads to wrong results. Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/d

[Mesa-dev] [PATCH 1/2] nvc0/ir: always use limm form for log ops with immediates

in the short imm form 0x8 was sign-extended to 0xfff8 which leads to wrong results. Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/d

[Mesa-dev] [PATCH v6 04/34] nvir: move common converter code in base class

v2: remove TGSI related bits Signed-off-by: Karol Herbst <kher...@redhat.com> Reviewed-by: Pierre Moreau <pierre.mor...@free.fr> --- src/gallium/drivers/nouveau/Makefile.sources | 2 + .../nouveau/codegen/nv50_ir_from_common.cpp| 107 + .../dri

[Mesa-dev] [PATCH v6 06/34] nv50,nvc0: add support for nir

of the nir shader merge: use the lowering helper v6: include TGSI debug header for proper assert call v6: add nv50 support Acked-by: Pierre Moreau <pierre.mor...@free.fr> Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/gallium/drivers/nouveau/Makefile.sources | 1 +

[Mesa-dev] [PATCH v6 11/34] nvir/nir: run assignSlots

getSlotAddress helper fix for 64 bit typed inputs v5: change getSlotAddress interface for easier use fix sample inputs fix slot counting for mat Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 614 + 1 file change

[Mesa-dev] [PATCH v6 13/34] nvir/nir: parse NIR shader info

v2: parse a few more fields v3: add special handling for GL_ISOLINES Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 60 ++ 1 file changed, 60 insertions(+) diff --git a/src/gallium/drivers/nouveau/c

[Mesa-dev] [PATCH v6 08/34] nvir/nir: run some passes to make the conversion easier

v2: add constant_folding v6: print non final NIR only for verbose debugging Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 39 ++ 1 file changed, 39 insertions(+) diff --git a/src/gallium/drivers/nouveau/c

[Mesa-dev] [PATCH v6 05/34] nvir: add lowering helper

this is mostly usefull for lazy IR converters not wanting to deal with 64 bit lowering and other illegal stuff v5: also handle SAT v6: rename type variables fixed lowering of NEG add lowering of NOT Reviewed-by: Pierre Moreau <pierre.mor...@free.fr> Signed-off-by: Karol Herbst

[Mesa-dev] [PATCH v6 03/34] nvir: print the shader type when dumping headers

this makes debugging the shader header a little easier Acked-by: Pierre Moreau <pierre.mor...@free.fr> Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/

[Mesa-dev] [PATCH v6 09/34] nvir/nir: track defs and provide easy access functions

v2: add helper function for indirects v4: add new getIndirect overload for easier use v5: use getSSA for ssa values we can just create the values for unassigned registers in getSrc v6: always create at least 32 bit values Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../d

[Mesa-dev] [PATCH v6 10/34] nvir/nir: add nir type helper functions

v4: treat imul as unsigned v5: remove pointless !! Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 115 + 1 file changed, 115 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp

[Mesa-dev] [PATCH v6 01/34] st/glsl_to_nir: run lower_output_reads on !PIPE_CAP_TGSI_CAN_READ_OUTPUTS

this is required for Drivers which don't allow reading from outputs. Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com> Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/mesa/state_tracker/st_glsl_to_nir.cpp | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/mesa/s

[Mesa-dev] [PATCH v6 02/34] nv50/ir/ra: Fix copying compound for moves

so we don't know which is which. I took the approach of calling copyCompound() inside coalesceValues(), instead of afterwards. Cc: Ilia Mirkin <imir...@alum.mit.edu> Cc: Karol Herbst <kher...@redhat.com> Tested-by: Karol Herbst <kher...@redhat.com> Signed-off-by: Karol Herbst <k

[Mesa-dev] [PATCH v6 28/34] nvir/nir: implement geometry shader nir_intrinsics

v4: use smarter getIndirect helper use new getSlotAddress helper use loadFrom helper Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 27 ++ 1 file changed, 27 insertions(+) diff --git a/src/gallium/d

[Mesa-dev] [PATCH v6 29/34] nvir/nir: implement nir_intrinsic_load_ubo

v4: use loadFrom helper Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 14 ++ 1 file changed, 14 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/n

[Mesa-dev] [PATCH v6 31/34] nvir/nir: implement images

v3: fix compiler warnings v4: use loadFrom helper v5: fix signed min/max v6: set tex mask add support for indirect image access set cache mode Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 395 +++--

[Mesa-dev] [PATCH v6 26/34] nvir/nir: implement vote and ballot

v2: add vote_eq support use the new subop intrinsic helper add ballot v3: add read_(first_)invocation Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 42 ++ 1 file changed, 42 insertions(+) diff --git

[Mesa-dev] [PATCH v6 34/34] nvir/nir: implement intrinsic shader_clock

Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 8 1 file changed, 8 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp

[Mesa-dev] [PATCH v6 27/34] nvir/nir: implement variable indexing

with indirects aren't guarenteed to be aligned to 0x10 anymore. v3: use fixed size vec4 arrays until we fix MemoryOpt v4: fix for 64 bit types v5: use loadFrom helper Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 58 +++

[Mesa-dev] [PATCH v6 30/34] nvir/nir: implement ssbo intrinsics

v4: use loadFrom helper v5: support indirect buffer access Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 90 ++ 1 file changed, 90 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_n

[Mesa-dev] [PATCH v6 23/34] nvir/nir: implement nir_ssa_undef_instr

v2: use mkOp Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 13 + 1 file changed, 13 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/c

[Mesa-dev] [PATCH v6 33/34] nvir/nir: implement load_per_vertex_output

v4: use smarter getIndirect helper use new getSlotAddress helper v5: use loadFrom helper Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 23 ++ 1 file changed, 23 insertions(+) diff --git a/src/gallium/d

[Mesa-dev] [PATCH v6 32/34] nvir/nir: add memory barriers

v5: add more barrier intrinsics Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 19 +++ 1 file changed, 19 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/d

[Mesa-dev] [PATCH v2 1/2] gk110/ir: always use limm form for log ops with immediates

In the short imm form 0x8 was sign-extended to 0xfff8 which leads to wrong results. Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/d

[Mesa-dev] [PATCH v2 2/2] nvc0/ir: always use limm form for log ops with immediates

In the short imm form 0x8 was sign-extended to 0xfff8 which leads to wrong results. Fix setting the NOT modifier on immediate sources as well, because this is not legal anyway. v2: add an assert and move setting the NOT modifier Signed-off-by: Karol Herbst <kher...@redhat.com> --

[Mesa-dev] [PATCH v6 18/34] nvir/nir: implement nir_intrinsic_load_uniform

v2: use new getIndirect helper fixes symbols for 64 bit types v4: use smarter getIndirect helper simplify address calculation use loadFrom helper Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 10 ++

[Mesa-dev] [PATCH v6 16/34] nvir/nir: add skeleton for nir_intrinsic_instr

Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp| 17 + 1 file changed, 17 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_n

[Mesa-dev] [PATCH v6 20/34] nvir/nir: implement nir_intrinsic_load_(interpolated_)input

v3: and load_output v4: use smarter getIndirect helper use new getSlotAddress helper v5: don't use const_offset directly fix for indirects v6: add support for interpolateAt Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp

[Mesa-dev] [PATCH v6 15/34] nvir/nir: implement nir_load_const_instr

Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 18 ++ 1 file changed, 18 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_n

[Mesa-dev] [PATCH v6 12/34] nvir/nir: add loadFrom and storeTo helpler

Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 72 ++ 1 file changed, 72 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_n

[Mesa-dev] [PATCH v6 14/34] nvir/nir: implement CFG handling

v6: fix loops with blocks at the end nothing points to skip blocks with no instructions and no predecessors Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 270 - 1 file changed, 268 insertions(+), 2 del

[Mesa-dev] [PATCH v6 17/34] nvir/nir: implement nir_alu_instr handling

Signed-off-by: Karol Herbst <kher...@redhat.com> v2: user bitfield_insert instead of bfi rework switch helper macros remove some lowering code (LoweringHelper is now used for this) v3: add pack_half_2x16_split add unpack_half_2x16_split_x/y v5: replace first argument with n

[Mesa-dev] [PATCH v6 07/34] nvc0: add env var to make nir default

ed-off-by: Karol Herbst <kher...@redhat.com> --- src/gallium/drivers/nouveau/nouveau_screen.c | 5 + src/gallium/drivers/nouveau/nouveau_screen.h | 2 ++ src/gallium/drivers/nouveau/nv50/nv50_screen.c | 4 +++- src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 19 +-- 4 files

[Mesa-dev] [PATCH v6 25/34] nvir/nir: add getOperation for intrinsics

Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 24 ++ 1 file changed, 24 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_n

[Mesa-dev] [PATCH v6 24/34] nvir/nir: implement nir_instr_type_tex

reference in convert(glsl_sampler_dim&, bool, bool) fix tg4 component selection v5: fill up coords args with scratch values if coords provided is less than TexTarget.getArgCount() Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_nir.c

[Mesa-dev] [PATCH v6 22/34] nvir/nir: implement loading system values

v2: support more sys values fixed a bug where for multi component reads all values ended up in x v3: add load_patch_vertices_in v4: add subgroup stuff v5: add helper invocation v6: fix loading 64 bit system values Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/n

[Mesa-dev] [PATCH v6 21/34] nvir/nir: implement intrinsic_discard(_if)

Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 14 ++ 1 file changed, 14 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_n

[Mesa-dev] [PATCH v6 19/34] nvir/nir: implement nir_intrinsic_store_(per_vertex_)output

v3: add workaround for RA issues indirects have to be multiplied by 0x10 fix indirect access v4: use smarter getIndirect helper use storeTo helper v5: don't use const_offset directly Signed-off-by: Karol Herbst <kher...@redhat.com> --- .../drivers/nouveau/codegen/nv50_ir_from_n

[Mesa-dev] [PATCH v6 00/34] Nouveau NIR support

, because it requires changes to NIR itself. Support for bindless textures are missing, because it isn't support in NIR yet same goes for MS Images. Connor Abbott (1): nv50/ir/ra: Fix copying compound for moves Karol Herbst (33): st/glsl_to_nir: run lower_output_reads

[Mesa-dev] [PATCH v3 03/19] glsl: add packed for struct types

We need this for OpenCL kernels because we have to apply C rules for alignment and padding inside structs and for this we also have to know if a struct is packed or not. Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/glsl_types.cpp | 17 +++-- src/co

[Mesa-dev] [PATCH v3 08/19] nir/vtn: import OpenCL.std.h

From: Rob Clark <robdcl...@gmail.com> Lightly edited to be valid 'C' code. Is there a bug open to fix this upstream? Signed-off-by: Rob Clark <robdcl...@gmail.com> Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/spirv/

[Mesa-dev] [PATCH v3 06/19] RFC: nir/vtn: "raw" pointer support

ed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/spirv/spirv_to_nir.c | 87 --- src/compiler/spirv/vtn_private.h | 20 ++- src/compiler/spirv/vtn_variables.c | 300 - 3 files changed, 347 insertions(+), 60 deletions(-) diff --git a/

[Mesa-dev] [PATCH v3 12/19] nir: specify bit_size when loading system values

With OpenCL the size of some system value depends on the Physical model choosen, so we need a way to load any system value as 32 or 64 bit. Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/nir/nir_builder.h | 10 +--- src/compiler/nir/nir_lower_alpha_

[Mesa-dev] [PATCH v3 10/19] RFC: nir/vtn: handle constant builtins from kernels

With SPIR-V it is perfectly fine to declare builtins as constants and have no constant initializer on them. This change seems to be able to break Vulkan shaders, so please check if this is the correct thing here. Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler

[Mesa-dev] [PATCH v3 07/19] nir/vtn: print extension name in fail msg

From: Rob Clark <robdcl...@gmail.com> Signed-off-by: Rob Clark <robdcl...@gmail.com> Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/spirv/spirv_to_nir.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/spirv_to_nir

[Mesa-dev] [PATCH v3 13/19] nir/vtn: Handle OpInBoundsPtrAccessChain

From: Rob Clark <robdcl...@gmail.com> Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/spirv/spirv_to_nir.c | 1 + src/compiler/spirv/vtn_variables.c | 1 + 2 files changed, 2 insertions(+) diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/sp

[Mesa-dev] [PATCH v3 11/19] nir/vtn: pointers can point to cross_workgroup or local memory as well

Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/spirv/vtn_variables.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/compiler/spirv/vtn_variables.c b/src/compiler/spirv/vtn_variables.c index 80fca6e8a32..51f73b3cf8c 100644 --- a/src/compiler

[Mesa-dev] [PATCH v3 05/19] RFC glsl: add cl_size and cl_alignment

v2: fix cl_size for arrays_of_arrays Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/glsl_types.cpp | 48 + src/compiler/glsl_types.h | 10 ++ src/compiler/nir_types.cpp | 12 src/compiler/nir_types.h

[Mesa-dev] [PATCH v3 04/19] glsl: add glsl_base_get_byte_size

Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/glsl_types.h | 34 ++ src/compiler/nir_types.h | 30 +- 2 files changed, 35 insertions(+), 29 deletions(-) diff --git a/src/compiler/glsl_types.h b/src/co

[Mesa-dev] [PATCH v3 01/19] nir: add load/store_global intrinsics

on the memory model). Signed-off-by: Rob Clark <robdcl...@gmail.com> Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/nir/nir_intrinsics.h | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/compiler/nir/nir_intrinsics.h b/src/

[Mesa-dev] [PATCH v3 02/19] vtn: handle SpvExecutionModelKernel

Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/spirv/spirv_to_nir.c | 3 +++ src/compiler/spirv/vtn_private.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index 7ce7e9ba62e..edf02db584b

[Mesa-dev] [PATCH v3 00/19] nir/vtn/compiler: first batch of compute support

important core NIR changes and somebody should take a closer look at those. Karol Herbst (12): nir: add load/store_global intrinsics vtn: handle SpvExecutionModelKernel glsl: add packed for struct types glsl: add glsl_base_get_byte_size RFC glsl: add cl_size and cl_alignment RFC: nir/vtn

[Mesa-dev] [PATCH v3 19/19] RFC: nir/vtn: member in struct deref

Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/spirv/vtn_private.h | 5 +++-- src/compiler/spirv/vtn_variables.c | 14 +++--- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/src/compiler/spirv/vtn_private.h b/src/compiler/spirv/vtn_private.h

[Mesa-dev] [PATCH v3 14/19] nir/vtn/opencl: support fma

Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/spirv/vtn_opencl.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/compiler/spirv/vtn_opencl.c b/src/compiler/spirv/vtn_opencl.c index 3c5ecd22452..723a7edf9c2 100644 --- a/src/compiler/spirv/vtn_opencl.c +++

[Mesa-dev] [PATCH v3 16/19] nir: add load_kernel_param

OpenCL kernels have parameters (see pipe_grid_info::input), and so we need a way to access them. The offset source is the offset of the parameter to load in the kernel input buffer. v2: improve commit message remove BASE split lower_io changes into separate commit Signed-off-by: Karol

[Mesa-dev] [PATCH v3 15/19] nir: use load_local_group_size

From: Rob Clark <robdcl...@gmail.com> If local_size is not known at compile time, which is the case with clover, use the load_local_group_size intrinsic instead. Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/nir/nir_lower_system_values.c | 25

[Mesa-dev] [PATCH v3 09/19] nir/vtn: initial OpenCL.std extension

From: Rob Clark <robdcl...@gmail.com> Not complete, mostly just adding things as I encounter them in CTS. But not getting far enough yet to hit most of the OpenCL.std instructions. v2: update hadd definition (Karol Herbst <kher...@redhat.com>) Signed-off-by: Rob Clark <robd

[Mesa-dev] [PATCH v3 18/19] nir: kernel entrypoints can have arguments

From: Rob Clark <robdcl...@gmail.com> This assert is not valid for OpenCL kernels. TODO can we somehow conditionally assert based on glsl vs cl?? Signed-off-by: Rob Clark <robdcl...@gmail.com> Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/nir/nir.h | 1 -

[Mesa-dev] [PATCH v3 17/19] RFC nir/lower_io: lower kernel entry param load_vars to load_kernel_param

functions. Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compiler/nir/nir_lower_io.c | 39 --- 1 file changed, 36 insertions(+), 3 deletions(-) diff --git a/src/compiler/nir/nir_lower_io.c b/src/compiler/nir/nir_lower_io.c index df91febd68d..ed8e3

Re: [Mesa-dev] [PATCH v3 12/19] nir: specify bit_size when loading system values

On Fri, Mar 23, 2018 at 9:15 PM, Jason Ekstrand <ja...@jlekstrand.net> wrote: > On Fri, Mar 23, 2018 at 12:33 PM, Karol Herbst <kher...@redhat.com> wrote: >> >> With OpenCL the size of some system value depends on the Physical model >> choosen, so we need a way to

Re: [Mesa-dev] [PATCH v3 06/19] RFC: nir/vtn: "raw" pointer support

On Fri, Mar 23, 2018 at 10:07 PM, Jason Ekstrand <ja...@jlekstrand.net> wrote: > +list > > On Fri, Mar 23, 2018 at 1:45 PM, Karol Herbst <kher...@redhat.com> wrote: >> >> On Fri, Mar 23, 2018 at 9:30 PM, Jason Ekstrand <ja...@jlekstrand.net> >> wrot

Re: [Mesa-dev] [PATCH v3 15/19] nir: use load_local_group_size

On Fri, Mar 23, 2018 at 9:18 PM, Jason Ekstrand <ja...@jlekstrand.net> wrote: > On Fri, Mar 23, 2018 at 12:33 PM, Karol Herbst <kher...@redhat.com> wrote: >> >> From: Rob Clark <robdcl...@gmail.com> >> >> If local_size is not known at compil

Re: [Mesa-dev] [PATCH v2 2/2] nvir/gm107: consider FILE_FLAGS dependencies in SchedDataCalculatorGM107

On Mon, Feb 26, 2018 at 11:52 AM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: > > > On 02/24/2018 11:36 AM, Karol Herbst wrote: >> >> currently while insterting barriers, writes and reads to FILE_FLAGS aren't >> considered. This can lead

[Mesa-dev] [RFC PATCH] nir: add support for tg4 with multiple offsets

Just want quick feedback on this. Nouveau can make use of it, which would eliminate the need of having 4 seperate tg4 instructions. The current code runs into the assert when PIPE_CAP_TEXTURE_GATHER_OFFSETS is enabled. Signed-off-by: Karol Herbst <kher...@redhat.com> --- src/compile

Re: [Mesa-dev] [RFC] opencl: mega-cl

On Mon, Feb 26, 2018 at 2:28 PM, Rob Clark <robdcl...@gmail.com> wrote: > On Mon, Feb 26, 2018 at 7:15 AM, Karol Herbst <kher...@redhat.com> wrote: >> On Mon, Feb 26, 2018 at 1:10 PM, Emil Velikov <emil.l.veli...@gmail.com> >> wrote: >>> Hi guys

Re: [Mesa-dev] [RFC] opencl: mega-cl

On Mon, Feb 26, 2018 at 1:10 PM, Emil Velikov wrote: > Hi guys, > > Having attempted a similar thing in the past, I think there are two > things at play here. > As such I'd recommend trying to keep them separate. > > 1) Having a single and/or modular - state-tracker <>

Re: [Mesa-dev] [PATCH 02/13] nir: add load_param

On Fri, Mar 2, 2018 at 7:02 AM, Jason Ekstrand <ja...@jlekstrand.net> wrote: > On Wed, Feb 28, 2018 at 1:25 PM, Rob Clark <robdcl...@gmail.com> wrote: >> >> On Wed, Feb 28, 2018 at 4:16 PM, Eric Anholt <e...@anholt.net> wrote: >> > Rob Clark <robdcl

Re: [Mesa-dev] [PATCH] nv50/ir: Improve Maintainability of Target*::initOpInfo()

(i = 0; i < sizeof(commutative) / sizeof(commutative[0]); ++i) > + opInfo[commutative[i]].commutative = true; > + for (i = 0; i < sizeof(shortForm) / sizeof(shortForm[0]); ++i) > + opInfo[shortForm[i]].minEncSize = 4; same comment here > for (i = 0; i < sizeof(n

Re: [Mesa-dev] [PATCH v2 2/2] i965: Implement ARB_compute_variable_group_size.

Hi, if the changes inside "src/compiler/nir/nir_lower_system_values.c" are extracted into a seperate patch, this patch with the equal changes would be Reviewed-by: Karol Herbst I would need that for a nir to codegen pass for Nouveau and maybe it will help other drivers im

[Mesa-dev] [PATCH] nv50/ir: fix ConstantFolding::createMul for 64 bit muls

Fixes: 2f52925f5c60c72c9389bfdc122c3d5f8e15b25f "nv50/ir: move a * b -> a << log2(b) code into createMul()" Reviewed-by: Rhys Perry Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 2 +- 1 file changed, 1 insertion(+), 1 dele

Re: [Mesa-dev] [PATCH v4] nir: Don't lower the local work group size if it's variable.

Reviewed-by: Karol Herbst On Tue, Nov 13, 2018 at 3:51 AM Jason Ekstrand wrote: > > On Mon, Nov 12, 2018 at 6:10 PM Karol Herbst wrote: >> >> it shouldn't make a difference. This pass lowers load_derefs into >> whatever we want here. If we handle the system value explici

Re: [Mesa-dev] [PATCH v4] nir: Don't lower the local work group size if it's variable.

it shouldn't make a difference. This pass lowers load_derefs into whatever we want here. If we handle the system value explicitly "sysval" gets set. If not, we fetch the op through nir_intrinsic_from_system_value and do the load based on that. We just take a different path, but fundamentally we do

Re: [Mesa-dev] [PATCH v2] nir: Handle variables dependent on the local work group size.

On Sun, Nov 11, 2018 at 10:48 PM Jason Ekstrand wrote: > > On Sun, Nov 11, 2018 at 3:35 PM Plamena Manolova > wrote: >> >> Lowering shader variables which depend on the local work group >> size being available in nir_lower_system_values is only possible >> if the local work group size isn't

Re: [Mesa-dev] [PATCH v2] nir: Handle variables dependent on the local work group size.

an) On Mon, Nov 12, 2018 at 12:37 AM Jason Ekstrand wrote: > > On November 11, 2018 16:36:16 Karol Herbst wrote: > > > On Sun, Nov 11, 2018 at 10:48 PM Jason Ekstrand > > wrote: > >> > >> On Sun, Nov 11, 2018 at 3:35 PM Plamena Manolova > >> wr

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