On 7 December 2017 at 11:37, Giordon Stark wrote:
> Hi Alistair,
>
>
> On Wed, Dec 6, 2017 at 7:23 PM Alistair Francis
> wrote:
>>
>> On Wed, Dec 6, 2017 at 4:45 PM, Giordon Stark wrote:
>> > Hi Manju,
>> >
>> > Indeed, you might be right... I guess now I'm confused by why Xilinx is
>> > not
>>
Hi Alistair,
On Wed, Dec 6, 2017 at 7:23 PM Alistair Francis
wrote:
> On Wed, Dec 6, 2017 at 4:45 PM, Giordon Stark wrote:
> > Hi Manju,
> >
> > Indeed, you might be right... I guess now I'm confused by why Xilinx is
> not
> > exporting the HDF to a device tree correctly:
> >
> > Our block des
On Wed, Dec 6, 2017 at 4:45 PM, Giordon Stark wrote:
> Hi Manju,
>
> Indeed, you might be right... I guess now I'm confused by why Xilinx is not
> exporting the HDF to a device tree correctly:
>
> Our block design has the DDR set to 16gigs here:
> https://www.dropbox.com/s/r8yzbvlf9kov8ei/Screensh
Hi Manju,
Indeed, you might be right... I guess now I'm confused by why Xilinx is not
exporting the HDF to a device tree correctly:
Our block design has the DDR set to 16gigs here:
https://www.dropbox.com/s/r8yzbvlf9kov8ei/Screenshot%202017-12-06%2018.40.29.png?dl=0
Our HDF indicates 2 banks:
ht
> -Original Message-
> From: Giordon Stark [mailto:kra...@gmail.com]
> Sent: Wednesday, December 06, 2017 12:16 PM
> To: Manjukumar Harthikote Matha
> Cc: meta-xilinx@yoctoproject.org; Tang, Shaochun
> Subject: Re: [meta-xilinx] Wrong DRAM set for custom board using FSBL +
> u-boot?
>
As discussed previously on mailing list, we are proceeding with layer
restructuring. For rocko release we will have the following layers
meta-xilinx
->meta-xilinx-bsp (current meta-xilinx)
->meta-xilinx-contrib
In the subsequent releases we will add other layers from Xilinx
meta-x
Hi Nathan,
> -Original Message-
> From: meta-xilinx-boun...@yoctoproject.org [mailto:meta-xilinx-
> boun...@yoctoproject.org] On Behalf Of Nathan Rossi
> Sent: Friday, November 24, 2017 5:28 AM
> To: meta-xilinx@yoctoproject.org
> Subject: [meta-xilinx] [PATCH v2 0/7] MicroBlaze updates an
Hi Manju,
The generated device tree section (that I think is relevant) is here:
https://github.com/kratsg/meta-l1calo/blob/master/conf/machine/boards/gfex/prototype3/system-top.dts#L27-L30
memory {
device_type = "memory";
reg = <0x0 0x0 0x0 0x8000>, <0x0008 0x 0x0 0x8000>;
};
> -Original Message-
> From: meta-xilinx-boun...@yoctoproject.org [mailto:meta-xilinx-
> boun...@yoctoproject.org] On Behalf Of Giordon Stark
> Sent: Wednesday, December 06, 2017 9:26 AM
> To: meta-xilinx@yoctoproject.org
> Cc: Tang, Shaochun
> Subject: [meta-xilinx] Wrong DRAM set for c
Hi,
I've also tried adding a new defconfig for the board with the following
patch:
+CONFIG_SYS_SDRAM_BASE=0x
+CONFIG_SYS_SDRAM_SIZE=0x8000
but u-boot still reports the DRAM as 4 GiB. I'm at a loss as to why this is
happening. Is there something I'm missing?
On Wed, Dec 6, 2017 at 11
Hi all,
The board I'm using is defined here:
https://github.com/kratsg/meta-l1calo/blob/master/conf/machine/gfex-prototype3.conf
but
I'm noticing that the DRAM reported by U-Boot is set to 4 GiB. This would
be correct for ZCU102, but we have 16 GiB DRAM for our custom (v3) board.
Where is this se
Hi Syed,
I'm using the machine defined here: https://github.com/kratsg/meta-l1calo/ (
https://github.com/kratsg/meta-l1calo/blob/master/conf/machine/gfex-prototype3.conf
).
However this is the current output I'm seeing:
https://gist.github.com/kratsg/9100572d578900cd251c40f1f651d161 where it's
st
Hey,
here's a patch, which allows to change the KERNEL_DEVICETREE in a machine
overlay without modifying the IMAGE_BOOT_FILES.
Franz
From 25a170c8b3e07308fb1d9c27e7403486b37c72fb Mon Sep 17 00:00:00 2001
From: Calculus
Date: Wed, 6 Dec 2017 15:54:07 +0100
Subject: [PATCH] Append *-KERNEL_DEVICETRE
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