Eric Lowe wrote:
Holger Berger wrote:
I wasn't directly involved in the 64K prototype but only 64K and
larger
were used for user applications, and the page_t was 64K in span
(PAGESIZE=65536). There may have been some 8K mappings in the
kernel due
to OBP handing off translation lists with holes
Holger Berger wrote:
I wasn't directly involved in the 64K prototype but only 64K and larger
were used for user applications, and the page_t was 64K in span
(PAGESIZE=65536). There may have been some 8K mappings in the kernel due
to OBP handing off translation lists with holes -- I don't remember
On 3/19/06, Eric Lowe <[EMAIL PROTECTED]> wrote:
> Holger Berger wrote:
> >> I wasn't directly involved in the 64K prototype but only 64K and larger
> >> were used for user applications, and the page_t was 64K in span
> >> (PAGESIZE=65536). There may have been some 8K mappings in the kernel due
> >
Holger Berger wrote:
I wasn't directly involved in the 64K prototype but only 64K and larger
were used for user applications, and the page_t was 64K in span
(PAGESIZE=65536). There may have been some 8K mappings in the kernel due
to OBP handing off translation lists with holes -- I don't remember
On 3/9/06, Eric Lowe <[EMAIL PROTECTED]> wrote:
> >> The performance
> >> analysis was, as I recall, done mostly using US-III+.
> >
> > Did this include the concept that dwarfpages (8k) are no longer
> > available to both kernel and user land applications?
>
> I wasn't directly involved in the 64K
Holger Berger wrote:
US3 only has one TLB set with 512 entries for 8k pages. US3+ improved
this by the addition of another TLB set with 512 entries for 4M pages
- anything between these points - 64k and 512k pages - was ignored.
Today this design shows it's drawbacks as "automatic" MPSS has only
On 3/9/06, Eric Lowe <[EMAIL PROTECTED]> wrote:
> Hello,
>
> [...]
> > Comparing SF68k/SF15k with Niagara is problematic. The broken MMU design in
> > the US3/4 CPU models used in these machines is not able to use a
> > significant amount of 64k pages. If you still got a small performance win
>
Hello,
[...]
Comparing SF68k/SF15k with Niagara is problematic. The broken MMU design in the US3/4 CPU models used in these machines is not able to use a significant amount of 64k pages. If you still got a small performance win there then this would prove that an all-64k kernel has significant pe
> David S. Miller wrote:
> > The only thing that breaks is if apps don't call
> sysconf(_SC_PAGESIZE)
> > or some similar function such as getpagesize() to
> obtain that
> > information portably.
>
> .. or they make assumptions about the possible range
> of values. ;)
>
> > Or did Solaris acciden
