Still another ping.
This is already ok sthen@ to import (but not yet in the tree).
Any other developer available to give it a try? Tarball re-attached.
On 26/06/2020 18:19, Stuart Henderson wrote:
This is OK sthen@ to import.
On 2020/06/26 16:35, Alessandro De Laurenzis wrote:
Weekly ping.
This is OK sthen@ to import.
On 2020/06/26 16:35, Alessandro De Laurenzis wrote:
> Weekly ping.
>
> Tarball re-attached for your convenience.
>
> While there, I changed the master site from Github to
> opencircuitdesign.com (so we can avoid the on-the-fly generated
> archive).
>
> If you
Just a note:
On 26/06/2020 16:35, Alessandro De Laurenzis wrote:
[...]
If you would like to play a bit with the port:
- make a new directory (e.g. ./qflow-trial) and copy there the enclosed
map9v3.v file;
- change to that dir and run 'qflow gui';
- in the 'synthesys preparation' tab:
*
Weekly ping.
Tarball re-attached for your convenience.
While there, I changed the master site from Github to
opencircuitdesign.com (so we can avoid the on-the-fly generated
archive).
If you would like to play a bit with the port:
- make a new directory (e.g. ./qflow-trial) and copy there the
Greetings,
This is a proposal for a new port: cad/qflow, a full end-to-end digital
synthesis flow for VLSI ASIC designs.
DESCR
=
A digital synthesis flow is a set of tools and methods used to turn a
VLSI design written in a high-level behavioral language like Verilog
or VHDL into a
