> -Original Message-
> From: "Bagotronix Tech Support" <[EMAIL PROTECTED]>
> Sent: Thursday, July 26, 2001 11:12 PM
> To: Protel EDA Forum
> Subject: Re: [PEDA] ASCII Format
>
> > I believe CDs only have a finite life also. Does anyone know how long?
>
> The number I ha
On Fri, 27 Jul 2001 [EMAIL PROTECTED] wrote:
> The pin data probably does exist somewhere as a text file or bonding details of
> die pad location ( in x,y ) to pin number on the package. But for manufacturers
> to put these into Protel specific format, its not going to happen soon.
I don't need
On Thu, 26 Jul 2001, chris mackensen wrote:
> for example, to get an Excel spreadsheet of pin data, one only has to copy
> and paste from PDF to Excel (usually through MS-Word, to get the tables
> correct)
Hmm, the massaging this needs normally makes it very painful. I've not
tried going t
To Mr. Colin Weber
>
> I believe CDs only have a finite life also. Does anyone know how long?
In an Computer-magazin that tested CD-R-live in 1997 I red obout a Time of one
(only one!) year until first foult could be noticed. Dont know wether the times
have changed in the last Years, but mak
Today I tried to duplicate a section of a dual-cpu board, call it CPU1 (with
all its associated parts.) When I do that on the PCB, each part of the
duplicated pcb layout has a _1 suffixed to it. Fine. Now for the purpose
of duplicating the schematic representation of that, I copied the
correspo
This web page has some info on CD longevity
http://www.mrichter.com/cdr/primer/lifetime.htm
Roger Anderson
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Sorry if this seems off topic but several
people have asked in the ASCII thread
about CD lifetime. Here is more info
from the cdrfaq.
http://www.cdrfaq.org/faq07.html#S7-5
Roger Anderson
> -Original Message-
> From: Anderson, Roger [mailto:[EMAIL PROTECTED]]
> Sent: Friday, July 27, 2
Hello,
Has anyone figured out a work around so test points will only be exposed
on
the tested side and tented on the untested side (like under fine pitch SMT
components)?
Editing the Gerber's is the only way I know to do this now. :(
I would prefer something that be reproducible after revi
Well, here is what I thought of
Rather than pasting it into ths same PCB file create a copy of the PCB file
and open the new copy. And paste your corresponding section into a new
schematic as you did... but leave it out of the hierarchy for the first part
of this.
Close the original schemat
Thanks Colby. I'll try to follow that through as time goes by today. Right
now, I'm testing all that I can about multi-sheet and in particular the
"complex" hierarchy method described in my manual. But not having any luck
so far as the Create Netlist method doesn't seem to create the second cpu
I am not sure if this is relevant to what you are trying to do
specifically... But if I remember correctly the reference to Complex
hierarchy in the manual actually refers to the way it worked in 98... I
don't have my manual handy to check.
Either way... if you haven't looked at this KB article y
Carl ,
What I have done in the past: I have our engineer layout his design with a
TESTPOINT symbol on each net. This can be done on each sheet or can be
attached as the last page(s) of the schematic. I create a surface mount pad
according to my test requirements. The pad will also include a
Thanks for the link. So far, when I do the final step, "complex to simple",
it still creates a drawing similar to what I would have created by just
copying the desired section of the schematic - with the same designators
duplicated (U2 is U2 in both sub-sheets now). And when I create the
netlist
Exactly =)
In the article I pointed to one of the final lines is.
"You must then annotate the design to ensure that all designators are
unique"
Basically what this document tells you is how to copy the schematics, change
the name of the schematics, change the name of the sheet symbol, re-annota
So what's the point of all this complex hierarchy stuff if it doesn't add
the important bits automatically? As it stands I wind up maintaining two
flattened copies of the CPU section or maintaining one "complex hierarchy"
copy and having to manually edit all the designators when I flatten it.
Sur
The way I do this is to simply plot the soldermask for the side with the
testpoints
normally, and then select the testpoints, and edit the soldermask expansion
for
them to be negative, (ex: 30 mil TP gets -15mil expansion) and plot the
opposite
side to bury them in the mask.
Reed Woltering
Cad
This did work differently in Protel 98.
But... I think you understand how it works now.
I could be wrong, but I never could find a way to get the complex to simple
to function like it did in Protel 98.
If someone knows a way please share =)
I think however it was done in Protel 98 was not por
Reed,
Your solution would work if all the test points are on one side.
I have test points on both sides due to the high density of the product.
I am using vias for test points in some locations, so if I give them a
negative expansion
then I will be covering my testpoints with mask.
Makin
I have two different testpoint components in my library, one for topside,
one for bottom. This way you can just select them by pattern and edit
the mask expansion.
Reed
At 12:29 PM 7/27/01 -0700, you wrote:
>Reed,
> Your solution would work if all the test points are on one side.
>I have test
Just as an idea for someone swifter than me (don't know if it would be less
work than just doing the manual entry in Protel) for dealing with
manufacturer PDF files for high pin count devices: The latest version of
ScanSoft OmniPage Pro Version 11.0 (used to be Caere) includes the ability
to
Hello, all:
I am trying to open an Orcad DSN file into Protel 99SE with no success. The
message I get is:
Error reading Orcad Cache!
Try to Cleanup Cache first!
Any idea what that means and how to work around it? Or is this another
Protel advertised "feature" that doesn't really work?
I don'
At 12:29 PM 7/27/01 -0700, Schattke, Carl wrote:
>I have test points on both sides due to the high density of the product.
> I am using vias for test points in some locations, so if I give them a
>negative expansion
>then I will be covering my testpoints with mask.
> Making parts for each tes
At 06:16 PM 7/27/01 -0400, Bagotronix Tech Support wrote:
>I am trying to open an Orcad DSN file into Protel 99SE with no success. The
>message I get is:
>
>Error reading Orcad Cache!
>Try to Cleanup Cache first!
>
>Any idea what that means and how to work around it? Or is this another
>Protel a
Ivan,
I think the central issue to Protel to ORCAD and vice verse transfers is the
interpretation of the libraries. As well, design transfers seem to only see
the light of day when the base design files were ASCII in origin. Me ? I
have had about 30% success in importing ORCAD 9.2 stuff. Parts wo
> Hello, all:
>
> I am trying to open an Orcad DSN file into Protel 99SE with no success. The
> message I get is:
>
> Error reading Orcad Cache!
> Try to Cleanup Cache first!
>
> Any idea what that means and how to work around it? Or is this another
> Protel advertised "feature" that doesn't rea
On 03:39 PM 27/07/2001 -0700, Abd ul-Rahman Lomax said:
>Then make a solder mask expansion design rule to tent the pad for each
>class as desired. Top and bottom masks can be subject to different design
>rules by adding layer scope as the second term in the rule selection criteria.
Restricting
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