It depends on many things, but I don't think you need to use an extra internal RJ45,
unless there is a manufacturing reason for it.
I use internal Ethernet in all our products.
You need to take into account:
Ethernet speed - 10baseT and you'll probably be OK, 100Base or faster and you need to
b
sformer.
A PCB component with more parts, such as a connector.
A simple enclosure, e.g. a square box
A more complicated enclosure, e.g. A desktop case
An even more complicated enclosure, e.g. rack mount
Q3: Would you use the service?
Best Regards,
Jason Morgan
jason dot morgan at cit
Pro/Engineer + IntelliCAD (AutoCAD Clone)
-Original Message-
From: RogerHead [mailto:[EMAIL PROTECTED]
Sent: 23 July 2004 08:25
To: [EMAIL PROTECTED]
Subject: [PEDA] Adobe Illustrator
I am considering AI for designing instrument front panels. What do other
people use? Our publications d
Any problems I've had with board warpage in the past have been due to either
Bad design with respect to copper density across and through the board, or un-even
density of drill holes.
Bad processing, the board having stresses frozen into it during manufacturing.
Bad build up, using asymmetric bui
Sounds to me, like many things, each vendor has their own standard ;)
Honestly, I've no idea if mini-DIN has a numbering standard (though the name, DIN
means Deutsches Insitut für Normung, a German standards org)
What I normally do is use the numbering (or naming) that either makes most sense in
For those that have been waiting, QualECAD have released their View3D for Protel2004.
Its at http://www.qualecad.com/
Regards,
Jason Morgan
P.S. Its so much better than Altium's attempt at the same...
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* To post a me
You could use my Re-pour poly server, its on the Yahoo Groups Protel forum as
CitelTools.
The other way is to carefully select all the polys, then without accidently moving
them cut and re-paste them.
Its so tricky that I wrote the server to do the task automatically.
Protel 2004 does this its
Assuming you still have it, and EasyPC can generate Gerber files, then you can use
Camtastics Reverse engineering capabilities to create a PCB from the Gerber.
Failing that, (if its only two layer) if you only have a paper print, or a bare PCB,
then you could try scanning a bitmap, using a cad p
You need to use a negative component clearance rule distance.
e.g.
IsFootprint('Footprint1') and IsFootprint('footprint2')
Clearance = -5000mil
You need to enable 'Full' clearance rule checking which can be slow.
We use this method for LED arrays under light pipes.
Protel 99se has no idea of t
99SE sp6. I get the message
>
>Design Explorer Error!
>File C:\\Temp\xxx.tmp is too large.
Jason Morgan had a similar problem way back in August 2002.
From the look of it there was no obvious solution then - Jason are you
still on this forum? (I will ask on the DXP forum as I know he
The UI for signal integrity is much improved, though I expect that the
underlying algorithm is the same.
The signal integrity module also allows you to calculate the trace impedance
based on a user defined algorithm if you think that the default is not
correct for your synario.
Although you can s
There IS a manual way, using rooms and component classes.
A room is defined in the Rules using in_component_class('name'), classes are
defined by the
synchroniser, or manually, there has to be one class per room.
Classes (and rooms) muck up if the room/class definition is in any way
wrong, the ro
I've used a Aluminium/Ceramic/Copper substrate before. I think one brand is
ThermalClad. This should meet your dimensional stability, and you can choose
any metal substrate, e.g.. spring steel or aluminium, this should give
you the strength you need.
http://www.bergquistcompany.com/objects/Tclad_S
I have a book called "Writing windows device drivers" - though I can't
remember who its by.
(If I remember, I'll take a look in the loft at the weekend, to see if I can
find it)
I recall it did use the authoring of a windows printer driver as the example
throughout. (Its was
for the w95 model, not
I would not call this a bug, just Protel getting confused about what you are
actually trying to do. It could be that the entity that you are trying
to edit is on a disabled layer.
I've had interesting times' and serious problems with panelisation under
99se, I've found that planes get disconnect
Gwyn,
I bet you were a little taken aback that innocuous query caused such a
flurry of emails. In a way, that is the problem with PEDA these days. On
a number of occasions it has gone extremely off topic (less so until
recently), causing some long term and well respected members to leave and
othe
Original Message-
From: Ian Wilson [mailto:[EMAIL PROTECTED]
Sent: 09 July 2003 12:59
To: Protel EDA Forum
Cc: DXP Technical Forum
Subject: Re: [PEDA] adjacent component placement DXP
On 06:45 PM 9/07/2003, Jason Morgan said:
>Firstly you posted to the wrong list, this list is for Pr
>distinction between these forums. Altium's is one which is a quarantined,
>corporate sponsored list, with all of the implications that go with that
>status. Techserv's is an open user's forum for ANY and ALL Protel EDA
>products, regardless of any ignornat comments made b
27;s novice or jaded
participants.
thank you,
Andrew Jenkins
> -Original Message-
> From: Jason Morgan [mailto:[EMAIL PROTECTED]
> Sent: Wednesday, July 09, 2003 4:46 AM
> To: 'Protel EDA Forum'
>
> Firstly you posted to the wrong list, this list is for Prot
Firstly you posted to the wrong list, this list is for Protel 99se, and not
DXP,
there is a separate list for DXP issues, see
http://forums.altium.com/cgi-bin/msgbylist.asp?list=dxp
To answer your question, its the same as in 99se, you create a
component-component clearance rule
that uses the same
Hi,
In a previous company we used a self adhesive pre-printed metallic label
that could stand (2-3 passes) of reflow and was safe in the wash.
It even withstood conformal coat removal.
However I don't know the supplier, the fab house was Foundation
Technologies (A division or Radstone)
in Towch
If you used the construction you suggest you'd encounter a problem with
copper balance.
It would appear either during board manufacture or reflow, or both.
The mass of copper on 2/3 is different to 4/5 so the board will be badly
bent or twisted.
(The coefficient of expansion of copper is differe
I've never had problems with the transformer models that come with 99se - I
use them all the time.
(ok, that's not exactly true, they can be a pig, but do work if you use them
right.)
I usually use the dual primary, dual secondary and join the middles
together.
or you can use two separate transf
Try the dxp forum, you'll get more help there.
mailto:[EMAIL PROTECTED]
You'll need to join at
http://forums.altium.com/
Jason.
-Original Message-
From: mbestha [mailto:[EMAIL PROTECTED]
Sent: 31 March 2003 10:51
To: [EMAIL PROTECTED]
Subject: [PEDA] hi all
hi all,
Iam new user to
Peter,
Try the PEDA list-server at techservinc.com , more people hang out there.
If you can't find an off the shelf TO-220 V, then you'll have to draw one
yourself, its very, very easy. Especially if you have the manufacturers
drawings to hand.
One thing to note, however.
If you are running
I've had this problem with some printer drivers, its been there since the
early days of Protel 99se and never fixed.
Protel's support blaim the printer, but no other programs have such
problems, I've seen it in more than
one printer driver, also missing text and bounding boxes missing, shaded
area
Jamie, check out the start up banner for DXP schematic, you'll notice that
its call 'nVisage' DXP, if you have dxp, you already have nvisage.
then turn off the banner 'cos its annoying.
-Original Message-
From: JaMi Smith [mailto:jamismith@;sbcglobal.net]
Sent: 12 November 2002 21:15
To:
This is a question for your production process and/or house.
If you use through hole, it could mean adding an otherwise un-required wave,
machine or hand
soldering process to produce the PCA. If you are producing a number of
boards, this can
be costly.
If you have components on the top and the b
Oh,
You wanted to know if there are similar board to yours out there.
We have a number of designs on 11"x13" 6 layer + 5 mech.
It has more than 1000 components, populated both sides with several QFPs.
I think you can even see a picture of one of the boards on the web
(The site's bleeding AS
Hi,
You are correct to get a better machine and loose the ATI card.
I run 1.7GHz and 1G RAM, and NVidia TNT2 32meg, the ATI card low memory was
the
cause of most of our previous problems - still no idea why
We've also had problems with some printer drivers, especially a PCL6.
(Incidentally
You don't need to use access, just use Protel...
1st: TAKE A BACKUP OF YOUR DATABASE, I have known this to go wrong on low
memory machines.
(I've no idea why this is so hidden)
In the design explorer, with ALL DOCUMENTS CLOSED there is a downward
pointing arrow in the menu bar
at the top right.
Try doing a model in Protel using the signal integrity function.
Don't try the whole bus, just one circuit, get the IO technology, lengths,
widths, shape and board
layup and material correct and you'll get a reasonably close simulation - or
at least I did.
Assuming you're not going to let more t
Jami, read the original email, I think you've over-reacted!!
- You said
I would respectfully submit that the specific action that you appear to have
just now taken here, to wit, the shutting down the PEDA forum, may in fact
be a little extreme.
techserve said
> The new forum will be modera
e Window's
print interface) whether it's printing to Acrobat, or a PCL printer, or a
Postscript printer. It's up to the printer driver to generate the
corresponding output (PDF, PCL, or Postscript).
> -Original Message-
> From: Jason Morgan [mailto:[EMAIL PROTECTED]]
We've had this problem since getting Protel.
And two other similar problems.
1: Invert Circles on IO's are missing.
2: Some outline boxes (e.g. text box) are missing (does not affect
filled boxes)
Protel say its the printer drivers fault (but no other program produces such
wierd outpu
Jason,
No idea about the size limit, but does your assembly house require the poly
planes included?
Emanuel
Jason Morgan wrote:
> Hi,
>
> Due to some weirdness at our assembly house, they can't accept a normal
pick
> and place file.
>
> They want a Protel ASCII PCB file,
Hi,
Due to some weirdness at our assembly house, they can't accept a normal pick
and place file.
They want a Protel ASCII PCB file, which they then import and create the
necessary data for their machinery.
This has been OK up 'till now, with an output file format of 35MByte.
A recent variant o
For me, the jury is out.
I've been playing with the demo version. If that is the same as the
production version then I have some
serious concerns over the usability of the schematic hierarchy, especially
with large imported 99SE designs.
I really don't like the need to explicitly 'compile' a sch
We too use a shared network drive for a co logo on schematics, its a bit
crap, but works (sort of, lets hope
DXP makes a better job of it.)
Anyway I've found the ability for more than one machine to successfully read
the file at once depends
on the NOS you are using and how the file is attributed
How about turning the problem round?
What ever match, boolean or wildcard rules you add to your server, somebody
will find
somthing that is wrong with it.
As it is, it probably works for most of the people that want to use it. (I'm
going to try it
myself at some point.)
Perhaps its a better ide
Trumpets.Tra-da-d
Roll of drums..brrrom
Queue the marketing man in sharp suite!!
.
.
.
then.Turn off the lights.
Any more news on DXP or the beta program?
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* To post a message: mailto:[EMAIL PROTECTED]
*
* To leave this
Designer
Norsat International Inc.
Microwave Products
Tel (604) 292-9089 (direct line)
Fax (604) 292-9010
email: [EMAIL PROTECTED]
http://www.norsat.com
See us at Booth S8155 at NAB 2002 in Las Vegas April 8 - 11.
> -Original Message-
> From: Jason Morgan [mailto:[EMAIL PROTECT
>We've also noticed that over a long period (weeks) the twist gets less.
> >
> >Regards
> >
> >Jason.
> >
> >
> >-Original Message-
> >From: Mike Reagan [mailto:[EMAIL PROTECTED]]
> >Sent: 03 April 2002 16:43
> >To: Protel EDA Forum
> >Subject:
John Said:
>Another test: if you run two bare boards through reflow, with one
>"top" facing up and the other facing down, do both boards warp in
>the same direction, or is it always toward the "top" (or "bottom",
>as the case may be). The former would point to a reflow issue, while
>the latter wo
I am not beting exact on the actual thickness of the Ni/Au as its not
specified in the board report, only that the outer serfaces are plated to
1oz, part of that plating will be copper when the via and through hole
connections are made.
The manufacturers report only states the plate thickness, no
ormed of the solution and the outcome, thanks once
again for all the help.
Jason
-Original Message-
From: Jon Elson [mailto:[EMAIL PROTECTED]]
Sent: 03 April 2002 21:53
To: Protel EDA Forum
Subject: Re: [PEDA] WANTED: PCB Expert (Off Topic)
Jason Morgan wrote:
> Many thanks,
>
>
el EDA Forum
Subject: Re: [PEDA] WANTED: PCB Expert (Off Topic)
Jason
Some of our advice is free
What process is warping the boards? Reflow or manufacturing? or upset
employee?
Mike Reagan
EDSI
- Original Message -
From: Jason Morgan <[EMAIL PROTECTED]>
To: 'Protel EDA
.
Regards,
Jason Morgan
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*
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*
* Forum Guidelines Rules
On this subject, (I appologise if this has already been mentioned as I've
not followed the thread too well)
Another thing to add to the protel wish list should be mechanical layer
pairs.
It should be possible for each mechanical (M) layer to pair it with another.
Such that that when a component
"
file.
I would recommend using a Gerber viewer / editor for viewing Gerber files.
Leon Fonstin
-Original Message-----
From: Jason Morgan [mailto:[EMAIL PROTECTED]]
Sent: Tuesday, 19 February 2002 5:36 AM
To: Protel EDA Forum (E-mail)
Subject: [PEDA] URGENT HELP REQUIRED: Paste Mask
I
Yes and No.
Yes I designed the board and No the Vias are not free pads.
There is no holes in the solder paste layers on the origional protel
drawing, only on the gerber import.
The gerber import is just photoplot commands, therefore if there is a shape
there then there will be a hole.
J.
---
Hi,
As normal we load the gerbers back into protel to check they look right,
I've noticed that
the tented vias have solder on them on the paste mask. Why, and how do I
get rid of it?
I've never noticed this before but can't say it hasn't happened.
We're just about to spin the boards and want t
Here's some more for the database, all on Protel 99SE
1:
Schematic print produces different results with different drivers on the
same printer.
As its windows GUI that does the rendering for the print driver, I've no
idea why.
Items affected are rectangle outline
Inverts generated with single i
oftware (JET) to work with multiple users.
J.
-Original Message-
From: Ian Wilson [mailto:[EMAIL PROTECTED]]
Sent: 14 February 2002 23:28
To: Protel EDA Forum
Subject: Re: [PEDA] Bug Database - a new bug (or is it?)
On 03:59 PM 14/02/2002 +, Jason Morgan said:
>Here's an intere
Here's an interesting 'bug' for the database, or perhaps it will be when its
confirmed?
Its not much of one, and I don't want to start a big duscussion on file
naming.
Try creating a .ddb then save it and exit.
Rename it to a file with a single quote in it.
e.g.
MyDatabase.ddb -> Jason's Databa
If its assigned to a net, and it must be if its got a ratnest:-
XA to un-select all.
use the net browse box to select the offding net by double clicking on the
net name and checking the selected box.
then shift delete delete to delete selected items.
-Original Message-
From: Bryn Wolfe [m
We've banned use of multiple users as it seems the semantics round it are
broken.
Under SP6:
If use A opens the file, followed by user B, the file it not locked by
default, user A must lock it
manually (I'm sure unlike earlier versions)
If user A forgets to lock it, B can open it, change it and
>>, synchronizer
>
>What is the problem with the synchronizer - I have not found anything I
>think is broken with it?
It fails sometimes - well sort of anyway.
On our relatively complex designs, update PCB sometimes misses out changes,
we have a rule that
it should be run 3 or more times to en
Ive just had the following report. I don't use BigFudge for this reason, but
I know IT managers in some places make it mandatory - they think it saves
them work.
Anyway here's a BigF-Up that affects Protel, so you'd better be aware of it.
J.
-
Pat came a
Have you tried talking to lattice, they can be very helpful
Lattice changed their programming method from a proprietory system
to JTAG about five years ago (perhaps more).
As far as I know they still support the non-E variants of the
1000 series, at least is there in the V3.0 of their ISP do
Solved it
Close the schematic
Delete all of the automatically generated files in the .ddb leaving just
the schematic.
Open the schematic
Bingo
AC and Fourier Sim now works.
J.
-Original Message-
From: Jason Morgan [mailto:[EMAIL PROTECTED]]
Sent: 15 January 2002 11:47
To: Protel
Hi,
I've used the Protel SPICE Simulator many times in the past, but not for a
while.
Just come to do an AC analysis of a filter and the Simulation Setup dialogue
box
ignores my instructions.
I know I've had this problem before, just can't remember how to fix it.
I seem to remember it writes a
Hi,
I think you are going to be disappointed. In simple terms there is no such
thing as a 'standard' component
footprint. Several factors define the footprint used for any single
component.
Potentially there are an infinite number of PCB footprints, I don't think
anybody has hade time to make
EXCEPT free upgrade to next version. And
on purchase of the upgrade we receive all of the features. They want there
money for the next release. Which while I wish it were different, I
actually think is reasonable.
Mike
-----Original Message-
From: Jason Morgan [mailto:[EMAIL PROTECTED]]
S
itely told me that as i paid before 1/10/01, I do
NOT get ATS, and will have to pay for the next release, but they don't know
how much.
Steve.
> -Original Message-----
> From: Jason Morgan [mailto:[EMAIL PROTECTED]]
> Sent: 05 December 2001 16:30
> To: 'Protel EDA Forum
I can confirms it's true (at least for the UK) I received the following
flyer
from Premier EDA
www.cropwell.net/protel/protel99.jpg
Looks like all of our shouting has paid off, lets just hope its all its an
improvement
on 99SE!!
J.
-Original Message-
From: Steve Smith [mailto:[EM
, overclocked, metastable,
negative-timing-margin PC.
Best regards,
Ivan Baggett
Bagotronix Inc.
website: www.bagotronix.com
- Original Message -
From: "Jason Morgan" <[EMAIL PROTECTED]>
To: "'Protel EDA Forum'" <[EMAIL PROTECTED]>
Sent: Monday, Nov
(Note I've seen the latter on several past Protel installs with certain
graphics cards, notably ATI)
So we've got the same files on the same everything, what's left? Protel is
sensitive to PC hardware, surely not..
J.
Michael,
First lets get something straight, I take offence at your questioning my
competence with Protel, I've been using it for a very long time and am
familiar with all of its usual weird behaviours (even though they are still
unacceptable)
The only reason we are using it at all, and not the
>On 11/15/01 Altium responded:
>"It is not possible to manually define the 3D model that Protel will use to
>represent your custom made components at this time. There are third-party
>tools that may be helpful in this task. The companies that I am aware of
>that offer these tools are . http://ww
All,
I'd like to point out that (in my opinion ) Protel's 'tech' support is not
worth it.
[Rave switch on]
In the UK (Yes, Premier I know you are listening... you let the cat out the
other day) their support could be described as desktop support, similar to
that offered by PC reseller to new Wi
Hi,
Does anybody have a spare (legitimate) Protel PCB 99SE License for sale?
Jason.
Jason Morgan - Development Engineer
CITEL Technologies Ltd.
Wheatcroft Business Park
Landmere Lane, Edwalton
NOTTINGHAM, NG12 4DG, UK
Tel: +44 (0) 115 940 5444 Ext 204
Direct: +44 (0) 115 931 5104
Fax: +44 (0
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