On 12/26/2011 07:20 PM, Peter Maydell wrote:
On 26 December 2011 10:03, Mitsyanko Igori.mitsya...@samsung.com wrote:
New calc_size field in VMStateField is supposed to help us easily add
save/restore
support of dynamically allocated buffers in device's states.
There are some cases when
Am 26.12.2011 15:58, schrieb Peter Maydell:
diff --git a/hw/sd.c b/hw/sd.c
index 07eb263..2b489d3 100644
--- a/hw/sd.c
+++ b/hw/sd.c
@@ -81,22 +85,22 @@ struct SDState {
uint8_t sd_status[64];
uint32_t vhs;
int wp_switch;
-int *wp_groups;
+uint8_t *wp_groups;
C99 appears to consider compound literals as non-constants, and complains
when they are used in static initializers. Switch to ordinary initializer
syntax.
Signed-off-by: Avi Kivity a...@redhat.com
---
fpu/softfloat-specialize.h |8
fpu/softfloat.h|2 ++
2 files
Am 27.12.2011 09:11, schrieb Mitsyanko Igor:
On 12/26/2011 07:20 PM, Peter Maydell wrote:
On 26 December 2011 10:03, Mitsyanko Igori.mitsya...@samsung.com
wrote:
diff --git a/hw/hw.h b/hw/hw.h
index efa04d1..8ce4475 100644
--- a/hw/hw.h
+++ b/hw/hw.h
@@ -303,9 +303,9 @@ enum VMStateFlags
On 12/26/2011 05:00 PM, Dor Laor wrote:
On 12/26/2011 05:12 PM, Anthony Liguori wrote:
Hi Dor,
Merry Christmas Anthony,
Happy Hanukkah!
I think it's not a bad thing to have multiple test suites when there
isn't considerable overlap.
I agree but in this case, it loos to me that
Hi,
Am 27.12.2011 05:21, schrieb Khansa Butt:
any one of you know about MIPS64el cross compiler?
What do you need to know? Where to get one?
I would try compiling the latest stable binutils and GCC with
--target=mips64el-linux or so. Dependencies are GMP, MPFR and MPC - your
Linux distro
Am 27.12.2011 03:26, schrieb Richard Cole:
https://github.com/qemu/QEMU/blob/2ac711791b2e4aabc5e4046b7428727828c705eb/hw/pl080.c#L96
Further down, this also looks odd:
if (s-conf (PL080_CONF_M1 | PL080_CONF_M1)) {
hw_error(pl080_write: Big-endian DMA not implemented\n);
On Tue, Dec 27, 2011 at 5:21 AM, Khansa Butt kha...@kics.edu.pk wrote:
hi
any one of you know about MIPS64el cross compiler? I would appreciate
your response..
Have you looked at Aboriginal?
http://landley.net/aboriginal/downloads/binaries/
--
Regards,
Artyom Tarasenko
solaris/sparc under
On 12/27/2011 05:22 PM, Anthony Liguori wrote:
The infrastructure assumes that you have a full OS available in the
guest. The tests are written in Python and make a variety of
assumptions. To my knowledge, it's not very practical to build a
busybox environment with Python embedded in it.
Am 27.12.2011 16:11, schrieb Avi Kivity:
C99 appears to consider compound literals as non-constants, and complains
when they are used in static initializers. Switch to ordinary initializer
syntax.
Signed-off-by: Avi Kivity a...@redhat.com
Acked-by: Andreas Färber afaer...@suse.de
For the
On 12/27/2011 05:27 PM, Andreas Färber wrote:
Am 26.12.2011 15:58, schrieb Peter Maydell:
diff --git a/hw/sd.c b/hw/sd.c
index 07eb263..2b489d3 100644
--- a/hw/sd.c
+++ b/hw/sd.c
@@ -81,22 +85,22 @@ struct SDState {
uint8_t sd_status[64];
uint32_t vhs;
int wp_switch;
-int
On 12/23/2011 09:26 AM, Paolo Bonzini wrote:
Anthony,
the following changes since commit 3799ce4ab64f578eb818689a276e4f0c73d01fb5:
sd: Remember to reset .expecting_acmd on reset. (2011-12-21 05:04:21 +0100)
are available in the git repository at:
git://github.com/bonzini/qemu.git
On 12/22/2011 02:13 PM, Marcelo Tosatti wrote:
The following changes since commit 03ecd2c80a64d030a22fe67cc7a60f24e17ff211:
virtio-serial-bus: Ports are expected to implement 'have_data' callback
(2011-12-21 15:00:29 -0600)
are available in the git repository at:
On 12/21/2011 01:57 AM, Aneesh Kumar K.V wrote:
Hi Anthony,
This is the updated pull request after moving the repo to github. I added two
patches to the series. The signed tag for-anthony is updated with updated info
The following changes since commit 3799ce4ab64f578eb818689a276e4f0c73d01fb5:
On 12/27/2011 08:02 AM, Avi Kivity wrote:
Make's multiple output syntax
x.c x.h: x.template
gen x.template
actually invokes the command once for x.c and once for x.h (with differing $@
in each invocation). During a parallel build, the two commands may be invoked
in parallel; this
On 12/27/2011 09:58 AM, Avi Kivity wrote:
On 12/27/2011 05:22 PM, Anthony Liguori wrote:
The infrastructure assumes that you have a full OS available in the
guest. The tests are written in Python and make a variety of
assumptions. To my knowledge, it's not very practical to build a
busybox
On 2011-12-26 21:49, Liu, Jinsong wrote:
From 19caf1db1f93e6f6b736e1dfd5e91a0c7669adec Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Tue, 27 Dec 2011 04:08:27 +0800
Subject: [PATCH] Expose tsc deadline timer cpuid to guest
Depend on several factors:
1. Considering
On 12/26/2011 06:58 PM, Peter Maydell wrote:
On 26 December 2011 10:03, Mitsyanko Igori.mitsya...@samsung.com wrote:
We couldn't properly implement save/restore functionality of SD host controllers
states without SD card's state VMStateDescription implementation. This patch
updates SD card
On 12/26/2011 04:58 PM, Peter Maydell wrote:
void sd_enable(SDState *sd, int enable)
{
-sd-enable = enable;
+sd-enable = enable ? true : false;
This kind of thing is why I don't like bool :-)
/me leaps to bool's defence:
sd-enable = enable should work just fine. The
Changes since first posting: fold a fixup patch into its parent patch,
style fixes.
I didn't get much review or testing for vhost or Xen, due to various
issues around births separated by a large amount of time if not
distance, but I don't want to get this series to get stale. Given that
both are
Make's multiple output syntax
x.c x.h: x.template
gen x.template
actually invokes the command once for x.c and once for x.h (with differing $@
in each invocation). During a parallel build, the two commands may be invoked
in parallel; this opens up a race, where the second invocation
Changes since first posting: fold a fixup patch into its parent patch,
style fixes.
I didn't get much review or testing for vhost or Xen, due to various
issues around births separated by a large amount of time if not
distance, but I don't want to get this series to get stale. Given that
both are
From: M. Mohan Kumar mo...@in.ibm.com
In passthrough security model in local fs driver, after a file creation
chown and chmod are done to set the file credentials and mode as requested
by 9p client. But if there was a request to create a file with S_ISGID
bit, doing chown on that file resets the
On 12/27/2011 02:40 PM, Anthony Liguori wrote:
On 12/27/2011 09:58 AM, Avi Kivity wrote:
On 12/27/2011 05:22 PM, Anthony Liguori wrote:
The infrastructure assumes that you have a full OS available in the
guest. The tests are written in Python and make a variety of
assumptions. To my
This is a collection of fixes and additions to the models for various ARM
devices. These changes are needed to support the forthcoming Calxeda
Highbank SoC model.
Makefile.target |2 +
hw/a9mpcore.c | 45 +-
hw/arm11mpcore.c|2 +-
hw/arm_gic.c| 46 ---
Add a cp15 config_base_register that currently defaults to 0.
After the QOM CPU support is added, the value will be properly
set to the periphal base value.
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v2
Added test against op2
hanges from v1
renamed
From: Rob Herring rob.herr...@calxeda.com
Add support for ahci on sysbus.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v1, v2
Corrected indentation of PlatAHCIState members
Made plat_ahci_info into a
From: Rob Herring rob.herr...@calxeda.com
Implement handling for the RAZ/WI gic security registers.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
Changes from v2
None
Increase the maximum number of GIC interrupts for a9mp to 192, and
create a configurable property defaulting to 96 so that device
modelers can set the value appropriately for their SoC.
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v2
Skipped
Changes from v1
From: Rob Herring rob.herr...@calxeda.com
This is just a dummy device for ARM L2 cache controllers, based on the
pl310. The cache type parameter can be defined by a property value
and has a meaningful default.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf
From: Rob Herring rob.herr...@calxeda.com
Add power control register to a9mpcore
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v2:
Better handling of byte and halfword writes to the power register
Use qdev properties to allow board modelers to set the frequencies
for the sp804 timer. Each of the sp804's timers can have an
individual frequency. The timers default to 1MHz.
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v2
Comment correctly describes
From: Rob Herring rob.herr...@calxeda.com
Use AHCIState instead of AHCIPCIState so the function can be used for
non-PCI based AHCI controllers.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
---
Changes from v1, v2
None
This adds very basic support for XG-mac ethernet core from Synopsis and
others. Missing things include:
- statistics counters
- WoL support
- rx checksum offload
- chained descriptors (only linear descriptor ring)
- broadcast and multicast handling
Signed-off-by: Rob Herring
On 27 December 2011 14:13, Avi Kivity a...@redhat.com wrote:
On 12/26/2011 04:58 PM, Peter Maydell wrote:
void sd_enable(SDState *sd, int enable)
{
- sd-enable = enable;
+ sd-enable = enable ? true : false;
This kind of thing is why I don't like bool :-)
/me leaps to bool's
On 27 December 2011 20:13, Mark Langsdorf mark.langsd...@calxeda.com wrote:
Increase the maximum number of GIC interrupts for a9mp to 192, and
create a configurable property defaulting to 96 so that device
modelers can set the value appropriately for their SoC.
/* Configuration for
On 27 December 2011 20:13, Mark Langsdorf mark.langsd...@calxeda.com wrote:
From: Rob Herring rob.herr...@calxeda.com
Add power control register to a9mpcore
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
Reviewed-by: Peter Maydell
On 27 December 2011 20:13, Mark Langsdorf mark.langsd...@calxeda.com wrote:
Use qdev properties to allow board modelers to set the frequencies
for the sp804 timer. Each of the sp804's timers can have an
individual frequency. The timers default to 1MHz.
Signed-off-by: Mark Langsdorf
On 12/27/2011 03:59 PM, Peter Maydell wrote:
On 27 December 2011 20:13, Mark Langsdorf mark.langsd...@calxeda.com wrote:
Increase the maximum number of GIC interrupts for a9mp to 192, and
create a configurable property defaulting to 96 so that device
modelers can set the value appropriately
On 27 December 2011 20:13, Mark Langsdorf mark.langsd...@calxeda.com wrote:
Add a cp15 config_base_register that currently defaults to 0.
After the QOM CPU support is added, the value will be properly
set to the periphal base value.
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
On 27 December 2011 22:04, Mark Langsdorf mark.langsd...@calxeda.com wrote:
On 12/27/2011 03:59 PM, Peter Maydell wrote:
The GIC architectural limit on number of interrupts is 1020;
that would (I think) imply a ~64K memory usage by the GIC,
which we can live with I think.
I think you just
On 27 December 2011 02:26, Richard Cole richard.j.c...@gmail.com wrote:
I'm new to QEMU so this might be a rather naive question but why is
there a hw_error [in pl080_run]:
I believe that hw_error() is basically there to say the code for
handling DMA is untested at best and unimplemented at
On 27 December 2011 14:33, Andreas Färber afaer...@suse.de wrote:
Further down, this also looks odd:
if (s-conf (PL080_CONF_M1 | PL080_CONF_M1)) {
hw_error(pl080_write: Big-endian DMA not implemented\n);
}
Maybe (..._M1 | ..._M2)?
Yes, obvious typo. I've noticed
On 12/26/2011 08:00 PM, Dor Laor wrote:
On 12/26/2011 05:12 PM, Anthony Liguori wrote:
Hi Dor,
Merry Christmas Anthony,
On 12/25/2011 09:19 AM, Dor Laor wrote:
On 12/19/2011 07:13 PM, Anthony Liguori wrote:
Well, I'm still not convinced that a new standalone package should
handle these
On 27 December 2011 03:21, Richard Cole richard.j.c...@gmail.com wrote:
Another thing I don't understand is the code from this function
switch(offset 2)
case 0:
// src address register
but 0x100 2 does not equal 0. Not even close. Maybe it should be
(offset - 0x100) 2?
But
On 27 December 2011 20:13, Mark Langsdorf mark.langsd...@calxeda.com wrote:
From: Rob Herring rob.herr...@calxeda.com
Use AHCIState instead of AHCIPCIState so the function can be used for
non-PCI based AHCI controllers.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark
QEMU does not exit and handle interrupt within translation blocks. it
only exits after the translation block is finished. Assuming a
translation block is very long, is it possible that QEMU could have
exceeded the interrupt's timing window and yields unexpected
behavior.
The reason I ask is that
On 12/27/2011 04:54 PM, Peter Maydell wrote:
On 27 December 2011 20:13, Mark Langsdorf mark.langsd...@calxeda.com wrote:
From: Rob Herring rob.herr...@calxeda.com
Use AHCIState instead of AHCIPCIState so the function can be used for
non-PCI based AHCI controllers.
Signed-off-by: Rob Herring
On 27 December 2011 23:12, Xin Tong xerox.time.t...@gmail.com wrote:
The reason I ask is that I am searching for alternatives to QEMU
current way of handling interrupt (unlink translation blocks on
interrupt). However, an obvious approach - checking for interrupt in
every basic block, seems
On 27 December 2011 20:13, Mark Langsdorf mark.langsd...@calxeda.com wrote:
+#define DEFAULT_CACHE_TYPE 0x19080800
Could use a comment saying what this actually is.
As far as I can tell it's actually specifying an invalid
I/D size for a PL310, which makes me suspicious of it.
(I might have
On 21 December 2011 22:39, Mark Langsdorf mark.langsd...@calxeda.com wrote:
I have code for a board model that uses it, but it uses the pre-
MemoryRegion API including direct calls to
cpu_register_physical_memory() and qemu_ram_alloc(). I can't
submit it until I get it updated. Any suggestions
On 27 December 2011 20:13, Mark Langsdorf mark.langsd...@calxeda.com wrote:
This adds very basic support for XG-mac ethernet core from Synopsis and
others. Missing things include:
+ if ((bd.buffer1_size 0xfff) 2048) {
+ fprintf(stdout, qemu:%s:ERROR...ERROR...ERROR... --
On Tue, Dec 27, 2011 at 4:36 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 27 December 2011 23:12, Xin Tong xerox.time.t...@gmail.com wrote:
The reason I ask is that I am searching for alternatives to QEMU
current way of handling interrupt (unlink translation blocks on
interrupt).
On 28 December 2011 00:43, Xin Tong xerox.time.t...@gmail.com wrote:
Which version of QEMU did you do your test on, and what are the tests.
It was whatever trunk qemu was a year or so ago, and the test was
just time to login prompt for ARM guest in system mode.
I modified QEMU to check for
On Tue, Dec 27, 2011 at 6:10 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 28 December 2011 00:43, Xin Tong xerox.time.t...@gmail.com wrote:
Which version of QEMU did you do your test on, and what are the tests.
It was whatever trunk qemu was a year or so ago, and the test was
just
This is a collection of fixes and additions to the models for various
ARM devices. These changes are needed to support the forthcoming
Calxeda Highbank SoC model.
Makefile.target |2 +
hw/a9mpcore.c | 43 +-
hw/arm11mpcore.c| 14 +-
hw/arm_gic.c| 63 +---
From: Rob Herring rob.herr...@calxeda.com
Add power control register to a9mpcore
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
Changes from v3
None
Changes from v2:
Increase the maximum number of GIC interrupts for a9mp and a11mp to 256,
and create a configurable property for each defaulting to 96 and 64
(respectively) so that device modelers can set the value appropriately
for their SoC. Other ARM processors also set their maximum number of
used IRQs
On 28 December 2011 01:24, Mark Langsdorf mark.langsd...@calxeda.com wrote:
+ case 0x104:
+ /* aux_ctrl values affect cache_type values */
+ s-aux_ctrl = value;
+ cache_data = (value (7 17)) 15;
+ cache_data |= (value (1 16)) 16;
+ s-cache_type |=
From: Rob Herring rob.herr...@calxeda.com
Implement handling for the RAZ/WI gic security registers.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
Changes from v2, v3
None
Use qdev properties to allow board modelers to set the frequencies
for the sp804 timer. Each of the sp804's timers can have an
individual frequency. The timers default to 1MHz.
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
Changes
This adds very basic support for XG-mac ethernet core from Synopsis and
others. Missing things include:
- statistics counters
- WoL support
- rx checksum offload
- chained descriptors (only linear descriptor ring)
- broadcast and multicast handling
Signed-off-by: Rob Herring
From: Rob Herring rob.herr...@calxeda.com
This is just a dummy device for ARM L2 cache controllers, based on the
pl310. The cache type parameter can be defined by a property value
and has a meaningful default.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Signed-off-by: Mark Langsdorf
Add a cp15 config_base_register that currently defaults to 0.
After the QOM CPU support is added, the value will be properly
set to the periphal base value.
Signed-off-by: Mark Langsdorf mark.langsd...@calxeda.com
Reviewed-by: Peter Maydell peter.mayd...@linaro.org
---
Changes from v3
On 12/27/2011 04:35 PM, Cleber Rosa wrote:
On 12/26/2011 08:00 PM, Dor Laor wrote:
On 12/26/2011 05:12 PM, Anthony Liguori wrote:
Hi Dor,
Merry Christmas Anthony,
On 12/25/2011 09:19 AM, Dor Laor wrote:
On 12/19/2011 07:13 PM, Anthony Liguori wrote:
Well, I'm still not convinced that a
Hi,
There were a number of requests about support of 64bit PCI BAR allocations.
Also we have observed the issue on guests with older linux version
(2.6.18): if we
have a 64bit BAR allocated within first 4GB, the OS may hang during
start process.
(I guess it is an OS bug, but we need to take
On 12/27/2011 11:37 PM, Anthony Liguori wrote:
On 12/27/2011 04:35 PM, Cleber Rosa wrote:
On 12/26/2011 08:00 PM, Dor Laor wrote:
On 12/26/2011 05:12 PM, Anthony Liguori wrote:
Hi Dor,
Merry Christmas Anthony,
On 12/25/2011 09:19 AM, Dor Laor wrote:
On 12/19/2011 07:13 PM, Anthony
Since Windows is using CRS table for PCI resource allocation, this patch
allows Windows
guests to work with PCI devices when PCI BAR allocation is above 4GB.
This also might be helpful on Linux when use_crs kernel boot option is set.
Michael I've added you to signed-off if you don't mind.
This patch adds PCI_REGION_TYPE_PREFMEM_64 region type and modifies types of
variables to make it possible to work with 64 bit addresses.
Why I've added just one region type PCI_REGION_TYPE_PREFMEM_64 and haven't
added PCI_REGION_TYPE_MEM_64? According to PCI architecture
specification, the
All devices behind a bridge need to have all their regions consecutive and
not overlapping with all the normal memory ranges.
Since prefetchable memory is described by one record, we must avoid the
situations
when 32bit and 64bit prefetchable regions are present within one secondary bus.
Dear QEMU team I want to add some debug command for qemu so my peter-bochs
(http://peter-bochs.googlecode.com) debugger can support qemu. So I have these
questions:1) QEMU use SVN?2) How to apply a role to submit code to their svn?
Thanksfrom Peter
Hi Cheung,
On Wed, Dec 28, 2011 at 05:40:20AM +, Peter Cheung wrote:
Dear QEMU team I want to add some debug command for qemu so my peter-bochs
(http://peter-bochs.googlecode.com) debugger can support qemu. So I have
these questions:1) QEMU use SVN?2) How to apply a role to submit
Hi, I am chinese too. Am I welcome to add some debug command to the qemu
internal debugger? I have some bad experiment before on other project, the
project owner is not willing to add feature by other people.
Thanksfrom Peter
Date: Wed, 28 Dec 2011 13:44:07 +0800
From:
2011/12/28 Peter Cheung mcheun...@hotmail.com:
Hi, I am chinese too. Am I welcome to add some debug command to the qemu
Sure, if your debugger idea is good enough. I think that you should
send out your idea at first before working on it.
Unfortunately, some maintainers are enjoying their holiday.
I hate thunderbird. Will resend the patches tomorrow.
+pci_config_writel(bdf, PCI_PREF_BASE_UPPER32, base 32);
Take a look the tutorial here http://code.google.com/p/peter-bochs/w/list
Thanksfrom Peter
Date: Wed, 28 Dec 2011 14:29:08 +0800
Subject: Re: [Qemu-devel] add debugger command
From: zwu.ker...@gmail.com
To: mcheun...@hotmail.com
CC: che...@iis.sinica.edu.tw; qemu-devel@nongnu.org
2011/12/28 Peter Cheung mcheun...@hotmail.com:
Hi, I am chinese too. Am I welcome to add some debug command to the qemu
internal debugger? I have some bad experiment before on other project, the
project owner is not willing to add feature by other people.
I think you would be disappointed
Dear AllPlease take a look http://peter-bochs.googlecode.com , I am an
operating system developer, bochs has a great build in command-line debugger,
but it is not good enough for normal use, so I created peter-bochs for it. But
bochs has a deadly weak point, it runs very slow. So I want to
I'll have to learn quite a bit more about QEMU and arm before I'll be
able to contribute back any patches. I bought a beagle board today so
that at least is a start, being able to compare QEMU to some real
hardware.
Out of curiosity what is the testing strategy for QEMU. Does one
simply write
On 12/27/2011 05:10 PM, Andreas Färber wrote:
Am 27.12.2011 09:11, schrieb Mitsyanko Igor:
On 12/26/2011 07:20 PM, Peter Maydell wrote:
On 26 December 2011 10:03, Mitsyanko Igori.mitsya...@samsung.com
wrote:
diff --git a/hw/hw.h b/hw/hw.h
index efa04d1..8ce4475 100644
--- a/hw/hw.h
+++
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