Hi,
> And qemu error output is:
> qemu: /home/akorolev/qemu-kvm/exec.c:2255: register_subpage: Assertion
> `existing->mr->subpage || existing->mr == &io_mem_unassigned' failed.
>
> Guest OS is Centos 5.5 and log is pretty boring, as qemu crashes before Linux
> can report an issue.
Where does
Hi Gerd, Liming,
On Tue, Dec 4, 2012 at 6:15 PM, Gerd Hoffmann wrote:
> Hi,
>
>> Gerd,
>>
>> Is there any documentation out there on how to tell QEMU on command
>> line which EHCI you want your usb-storage to attach to?
>
> docs/usb2.txt has some examples, although those are pc-centric where th
"Aneesh Kumar K.V" writes:
> I found this to be confusing. How about avoiding all those pointers, something
> like below ? If you are ok can I add the signed-off-by for this ? I can
> test this and get a pull request out with the build fix.
>
> commit 24cc9f0d07c2a505bfafbdcb72006f2eda1288a4
> Au
This message is not an error condition, its just informing the user that
the device is corking the uart traffic to not drop characters.
Reported-by: Jason Wu
Signed-off-by: Peter Crosthwaite
---
hw/xilinx_uartlite.c |6 +-
1 files changed, 1 insertions(+), 5 deletions(-)
diff --git a/
The device return false from the can receive function when the FIFO is
full. This mean the device should check for buffered input whenever a byte is
popped from the FIFO.
Reported-by: Jason Wu
Signed-off-by: Peter Crosthwaite
---
hw/xilinx_uartlite.c |1 +
1 files changed, 1 insertions(+),
The interrupt status register R_IS is the standard clear-on-write behaviour.
This was unimplemented and defaulting to updating the register to the written
value. Implemented clear-on-write.
Reported-by: Jason Wu
Signed-off-by: Peter Crosthwaite
---
hw/xilinx_axienet.c |4
1 files chan
Minor fixes to xilinx microblaze IP.
Peter Crosthwaite (3):
xilinx_axienet: Implement R_IS behaviour
xilinx_uartlite: suppress "cannot receive message"
xilinx_uartlite: Accept input after rx FIFO pop
hw/xilinx_axienet.c |4
hw/xilinx_uartlite.c |7 ++-
2 files changed, 6
On 12/04/12 18:14, Gabriel L. Somlo wrote:
> On Tue, Dec 04, 2012 at 05:56:55PM +0100, Gerd Hoffmann wrote:
>> Ok, and how does the RTC look like on your MacPro?
>
> Device (RTC)
> {
> Name (_HID, EisaId ("PNP0B00"))
> Name (_CRS, ResourceTemplate ()
> {
> IO (Decode16,
>
The device return false from the can receive function when the FIFO is
full. This mean the device should check for buffered input whenever a byte is
popped from the FIFO.
Reported-by: Jason Wu
Signed-off-by: Peter Crosthwaite
---
hw/cadence_uart.c |1 +
1 files changed, 1 insertions(+), 0 d
On Sat, Nov 24, 2012 at 8:51 PM, Liu Ping Fan wrote:
> From: Liu Ping Fan
>
> This logic has been integrated into pci core, so remove it.
>
> Signed-off-by: Liu Ping Fan
Signed-off-by: Cam Macdonell
> ---
> hw/ivshmem.c |1 -
> 1 files changed, 0 insertions(+), 1 deletions(-)
>
> diff --gi
On Sat, Nov 24, 2012 at 8:51 PM, Liu Ping Fan wrote:
> From: Liu Ping Fan
>
> Using irqfd, so we can avoid switch between kernel and user when
> VMs interrupts each other.
>
Hi Liu Ping,
With this patch applied I was still seeing transitions to user-level
on the receipt of an msi interrupt.
un
> -Original Message-
> From: qemu-devel-bounces+ericj=mips@nongnu.org [mailto:qemu-devel-
> bounces+ericj=mips@nongnu.org] On Behalf Of Aurelien Jarno
> Sent: Friday, November 16, 2012 3:04 AM
> To: qemu-devel@nongnu.org
> Cc: Aurelien Jarno
> Subject: [Qemu-devel] [PATCH 5/7] targe
> -Original Message-
> From: qemu-devel-bounces+ericj=mips@nongnu.org [mailto:qemu-devel-
> bounces+ericj=mips@nongnu.org] On Behalf Of Aurelien Jarno
> Sent: Friday, November 16, 2012 3:04 AM
> To: qemu-devel@nongnu.org
> Cc: Aurelien Jarno
> Subject: [Qemu-devel] [PATCH 7/7] targe
> -Original Message-
> From: qemu-devel-bounces+ericj=mips@nongnu.org [mailto:qemu-devel-
> bounces+ericj=mips@nongnu.org] On Behalf Of Aurelien Jarno
> Sent: Friday, November 16, 2012 3:04 AM
> To: qemu-devel@nongnu.org
> Cc: Aurelien Jarno
> Subject: [Qemu-devel] [PATCH 4/7] targe
> -Original Message-
> From: qemu-devel-bounces+ericj=mips@nongnu.org [mailto:qemu-devel-
> bounces+ericj=mips@nongnu.org] On Behalf Of Aurelien Jarno
> Sent: Friday, November 16, 2012 3:04 AM
> To: qemu-devel@nongnu.org
> Cc: Aurelien Jarno
> Subject: [Qemu-devel] [PATCH 6/7] targe
On Tue, Dec 4, 2012 at 4:59 PM, Liming Wang wrote:
> The IRQ number of the second EHCI controller should be 76, not 75.
>
> Signed-off-by: Liming Wang
Tested-by: Peter Crosthwaite
> ---
> hw/xilinx_zynq.c |2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/xilinx_zy
Beginning with the RA-2004.1 release, SR access instructions (rsr, wsr,
xsr) are associated with their corresponding SR and raise illegal opcode
exception in case the register is not configured for the core.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h |1 +
target-xtensa/ove
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/Makefile |1 +
tests/tcg/xtensa/macros.inc |2 +-
tests/tcg/xtensa/test_sr.S | 90 +++
3 files changed, 92 insertions(+), 1 deletions(-)
create mode 100644 tests/tcg/xtensa/test_sr.S
diff --git
ATOMCTL SR controls s32c1i opcode behavior depending on targeted memory
type. See ISA, 4.3.12.4 for details.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.c |2 +
target-xtensa/cpu.h | 10 +++
target-xtensa/helper.c | 56 +++
The Miscellaneous Special Registers Option provides zero to four scratch
registers within the processor readable and writable by RSR, WSR, and
XSR. These registers are privileged. They may be useful for some
application-specific exception and interrupt processing tasks in the
kernel. The MISC regis
There are read-only (DEBUGCAUSE, PRID) and write-only (INTCLEAR) SRs,
and INTERRUPT/INTSET SR allows rsr/wsr, but not xsr. Raise illeagal
opcode exception on illegal access to these SRs.
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 49 +++-
In XEA1, the Options for Memory Protection and Translation and the
corresponding TLB management instructions are not available. Instead,
functionality similar to the Region Protection Option is available
through the cache attribute register. See ISA, A.2.14 for details.
Signed-off-by: Max Filippov
On Tue, Dec 4, 2012 at 4:10 AM, Andrew Jones wrote:
>
>
> - Original Message -
>> On Thu, Nov 29, 2012 at 1:34 AM, liu ping fan
>> wrote:
>> > On Thu, Nov 29, 2012 at 12:42 PM, Cam Macdonell
>> > wrote:
>> >> On Tue, Nov 27, 2012 at 7:53 PM, liu ping fan
>> >> wrote:
>> >>> On Wed, Nov
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/Makefile |1 +
tests/tcg/xtensa/test_s32c1i.S | 39 +++
2 files changed, 40 insertions(+), 0 deletions(-)
create mode 100644 tests/tcg/xtensa/test_s32c1i.S
diff --git a/tests/tcg/xtensa/Makefile b/te
Use movcond for all sorts of conditional moves, ABS, CLAMPS, MIN/MAX
opcodes.
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 92
1 files changed, 42 insertions(+), 50 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/
Hi.
This is my current patch queue for xtensa:
- add support for a number of Special Registers: ATOMCTL, CACHEATTR, MISC;
- raise exceptions on access to unconfigured SRs/invalid access to configured
SRs;
- add unit tests for SR access and for s32c1i opcode;
- use movcond to re-implement some opc
Yes. You can never shut the window completely trying to do it that way,
which is why you need fix the problem properly instead.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/955379
Title:
cmake han
try to make breakpoint related functions
more cleaner.
originally, these functions implicit use
0,1,2,3 as name of breakpoint, really
hard to understand, so name them readable,
and also refactor the statement to
check these types for clean reason.
target-i386/cpu.h |11 ++--
target-i
On 04.12.2012, at 14:20, Erlon Cruz wrote:
>
>
> On Tue, Dec 4, 2012 at 12:42 AM, David Gibson
> wrote:
> Now that we have implemented PAPR compatible NVRAM interfaces in qemu, this
> updates the SLOF firmware to actually initialize and use the NVRAM as a
> PAPR guest firmware is expected to
Hi,
> Gerd,
>
> Is there any documentation out there on how to tell QEMU on command
> line which EHCI you want your usb-storage to attach to?
docs/usb2.txt has some examples, although those are pc-centric where the
ehci is created on the command line. The problem with zynx is that both
ehci c
On Tue, Dec 04, 2012 at 05:03:36PM +0100, Andreas Färber wrote:
> Am 04.12.2012 14:19, schrieb Eduardo Habkost:
> > The flag is necessary for code that doesn't use the variables from
> > Makefile (but use Makefile.objs), like libcacard/ and stubs/.
> >
> > Signed-off-by: Eduardo Habkost
>
> I do
Refactor common code around calls to cpu_restore_state().
tb_find_pc() has now no external users, make it static.
Signed-off-by: Blue Swirl
---
exec-all.h|6 ++
hw/kvmvapic.c |4 +---
target-alpha/helper.c | 14 +++---
target-alp
On Mon, Dec 3, 2012 at 8:42 PM, Stefan Hajnoczi wrote:
> On Fri, Nov 23, 2012 at 8:47 AM, Dong Xu Wang
> wrote:
>> Patch 1-3 are from Luiz, added Markus's comments, discussion could be found
>> here:
>> http://lists.nongnu.org/archive/html/qemu-devel/2012-07/msg02716.html
>> Patch 3 was changed
在 2012-12-04二的 12:49 +，Peter Maydell写道：
> On 4 December 2012 08:11, liguang wrote:
> > Signed-off-by: liguang
> > ---
> > target-i386/cpu.h |7 +++
> > 1 files changed, 7 insertions(+), 0 deletions(-)
> >
> > diff --git a/target-i386/cpu.h b/target-i386/cpu.h
> > index 90ef1ff..9abec
Hi all,
I had qemu 1.2.0 crash when using ivshmem driver with 64bit PCI support
enabled. The qemu process is terminated at a very early stage of
Linux boot up. Here is the qemu command line:
LC_ALL=C
PATH=/usr/kerberos/sbin:/usr/kerberos/bin:/usr/local/sbin:/usr/local/bin:/sbin:/bin:/usr/sbin:/u
Fix coding style in areas to be moved by later patches.
Signed-off-by: Blue Swirl
---
exec.c | 178 +++
1 files changed, 110 insertions(+), 68 deletions(-)
diff --git a/exec.c b/exec.c
index 8435de0..6efd93e 100644
--- a/exec.c
+++ b/
On 4 December 2012 08:11, liguang wrote:
> Signed-off-by: liguang
> ---
> target-i386/cpu.h |4 ++--
> 1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target-i386/cpu.h b/target-i386/cpu.h
> index 9abec3e..8ca25c8 100644
> --- a/target-i386/cpu.h
> +++ b/target-i386/cpu.h
>
在 2012-12-04二的 18:51 +，Blue Swirl写道：
> On Tue, Dec 4, 2012 at 8:11 AM, liguang wrote:
> > Signed-off-by: liguang
> > ---
> > target-i386/helper.c | 70
> > +
> > target-i386/machine.c |2 +-
> > target-i386/misc_helper.c |4 +-
>
在 2012-12-04二的 11:26 +，Peter Maydell写道：
> On 4 December 2012 11:11, Jan Kiszka wrote:
> > On 2012-12-04 11:23, Peter Maydell wrote:
> >> Doesn't this break the use of this function in target-i386/seg_helper.c:
> >>
> >> if (hw_breakpoint_enabled(env->dr[7], i) == 0x1) {
> >>
> >> which speci
Refactor TranslationBlock handling out of exec.c.
This could also help make TCG more optional or
add other code generators.
Blue Swirl (4):
exec: fix coding style
exec: extract TB watchpoint check
exec: move TB handling to translate-all.c
exec: refactor cpu_restore_state
exec-all.h
Peter Maydell writes:
> On 4 December 2012 18:38, Blue Swirl wrote:
>> The definition of the hard freeze bothers me. A few patches that went
>> in after 1.3-rc0 were not bug fixes but just new features, so the
>> difference between soft and hard freezes was not clear.
>
> My vote for this would
Am 04.12.2012 16:58, schrieb Robert Schiele:
> When we build neither any system emulation targets nor the tools there
> is actually no need for pixman library. In that case do not enforce
> presence of that library on the system.
>
> Signed-off-by: Robert Schiele
Reviewed-by: Andreas Färber
T
On 2012-12-04 13:00, Blue Swirl wrote:
>> > +if (rs5_0 == 0)
>> > +return;
> The check should be moved to translation time so that the call to this
> helper is not generated at all.
No, we'd do that only if this value were an immediate.
Branch over helper is not an optimization for an
On Tue, Dec 04, 2012 at 09:27:54PM -0200, Erlon Cruz wrote:
> Em 04/12/2012 20:58, "David Gibson" escreveu:
> >
> > On Tue, Dec 04, 2012 at 11:20:03AM -0200, Erlon Cruz wrote:
> > > On Tue, Dec 4, 2012 at 12:42 AM, David Gibson
> > > wrote:
> > >
> > > > Now that we have implemented PAPR compatibl
Am 04.12.2012 20:34, schrieb Eduardo Habkost:
> From: Igor Mammedov
>
> Signed-off-by: Igor Mammedov
> Acked-by: Andreas Färber
Mike, do we need to do anything here wrt deallocation visitors?
Or can you ack?
Thanks,
Andreas
> ---
> qapi/qapi-visit-core.c | 11 +++
> qapi/qapi-v
Juan Quintela writes:
> Rusty Russell wrote:
>> Hi all,
>>
>> I want to rework the qemu virtio subsystem, but various
>> structures are currently blatted to disk in save/load. So I looked at
>> altering that, only to discover that it needs conversion to vmstate, and
>> 2009 patches in p
> From: Andreas Färber [afaer...@suse.de]
>FWIW you could use our unlikely() macro then to aid branch prediction.
Just did. Thanks.
Petar
From: Petar Jovanovic
helper_shilo has not been shifting an accumulator value correctly for negative
values in 'shift' field. Minor optimization for shift=0 case.
This change also adds tests that will trigger issue and check for regressions.
Signed-off-by: Petar Jovanovic
---
target-mips/dsp_h
Em 04/12/2012 20:58, "David Gibson" escreveu:
>
> On Tue, Dec 04, 2012 at 11:20:03AM -0200, Erlon Cruz wrote:
> > On Tue, Dec 4, 2012 at 12:42 AM, David Gibson
> > wrote:
> >
> > > Now that we have implemented PAPR compatible NVRAM interfaces in
qemu, this
> > > updates the SLOF firmware to actual
Signed-off-by: liguang
---
target-i386/helper.c | 70 +
target-i386/machine.c |2 +-
target-i386/misc_helper.c |4 +-
target-i386/seg_helper.c |6 ++--
4 files changed, 51 insertions(+), 31 deletions(-)
diff --git a/target-i386/
On 28 November 2012 19:20, Eduardo Habkost wrote:
> The type_register_static() interface is documented as:
>
> type_register_static:
> @info: The #TypeInfo of the new type.
>
> @info and all of the strings it points to should exist for the life
> time that the type is registered.
>
> But c
On Mon, Dec 03, 2012 at 10:49:56PM +0100, Igor Mammedov wrote:
> On Fri, 30 Nov 2012 17:27:18 -0200
> Eduardo Habkost wrote:
>
> > Add vmstate stub functions, so that qdev.o can be used without savevm.o
> > when vmstate support is not necessary (i.e. by *-user).
> >
> > Signed-off-by: Eduardo Ha
On Tue, Dec 04, 2012 at 11:20:03AM -0200, Erlon Cruz wrote:
> On Tue, Dec 4, 2012 at 12:42 AM, David Gibson
> wrote:
>
> > Now that we have implemented PAPR compatible NVRAM interfaces in qemu, this
> > updates the SLOF firmware to actually initialize and use the NVRAM as a
> > PAPR guest firmware
Ping,
Am 26.11.2012 01:12, schrieb Andreas Färber:
> Hello Anthony and Paolo,
>
> As announced at KVM Forum, I have been preparing a new approach to
> incrementally
> get us Anthony's QOM realizefn concept. A previous attempt by Paolo and me had
> been turned down for making this available at Ob
Am 04.12.2012 20:23, schrieb Alex Horn:
> * Define constants for TMP105 registers.
> * Move tmp105_set() from I2C to TMP105 header.
>
> Signed-off-by: Alex Horn
CC'ing TMP105 author and ARM maintainer. Comments inline.
> ---
> hw/i2c.h|3 ---
> hw/tmp105.c | 17 +
> h
On 4 December 2012 21:39, Richard Henderson wrote:
> On 2012-12-04 15:25, Peter Maydell wrote:
>> So this is just a refactoring, but it prompts me to ask -- how does
>> this work if the PC that caused us to take this TLB fill is legitimately
>> zero? We seem to be overloading retaddr==0 as a "not
On Tue, Dec 04, 2012 at 04:59:38PM +0100, Andreas Färber wrote:
> Am 04.12.2012 14:19, schrieb Eduardo Habkost:
> > Changes on v9:
> > - Instead of moving qemu_[un]register_reset() to reset.c and including
> >it on *-user, create stubs for them on libqemustub.a
>
> We compile cpu.c twice. Can
"Daniel P. Berrange" writes:
> On Tue, Dec 04, 2012 at 01:13:46PM -0600, Anthony Liguori wrote:
>> "Daniel P. Berrange" writes:
>>
>> > On Tue, Dec 04, 2012 at 03:42:32PM +0100, Ján Tomko wrote:
>> >> On 12/04/12 12:46, Luiz Capitulino wrote:
>> >> > On Mon, 03 Dec 2012 16:55:35 +0100
>> >> > J
On 2012-12-04 15:25, Peter Maydell wrote:
> So this is just a refactoring, but it prompts me to ask -- how does
> this work if the PC that caused us to take this TLB fill is legitimately
> zero? We seem to be overloading retaddr==0 as a "not a real cpu fault"
> indicator...
Since this is a host co
On 4 December 2012 21:20, Blue Swirl wrote:
> diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
> index 6e3ab90..1fcc975 100644
> --- a/target-arm/op_helper.c
> +++ b/target-arm/op_helper.c
> @@ -74,19 +74,13 @@ uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t
> ireg, uint32_t def,
Will be moved by the next patch.
Signed-off-by: Blue Swirl
---
exec.c | 22 ++
1 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/exec.c b/exec.c
index 6efd93e..7ee0650 100644
--- a/exec.c
+++ b/exec.c
@@ -2985,12 +2985,24 @@ static const MemoryRegionOps notdir
Am 04.12.2012 20:48, schrieb Jovanovic, Petar:
>> diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
>> index e7949c2..f8a7a9f 100644
>> --- a/target-mips/dsp_helper.c
>> +++ b/target-mips/dsp_helper.c
>> @@ -3814,17 +3814,17 @@ void helper_shilo(target_ulong ac, target_ulong rs,
>>
On 4 December 2012 20:57, Antoine Mathys wrote:
> On 12/04/2012 06:42 PM, Peter Maydell wrote:
>> This looks good as far as the logic goes, but I think we could use some
>> symbolic constants for the 12-hour and PM bits rather than all the literal
>> 0x20 0x40 0x60. thanks -- PMM
>
> I refrained f
On 12/04/2012 06:42 PM, Peter Maydell wrote:
This looks good as far as the logic goes, but I think we could use
some symbolic constants for the 12-hour and PM bits rather than all
the literal 0x20 0x40 0x60. thanks -- PMM
I refrained from using symbolic constants for three reasons:
1. You need
On Tue, Dec 04, 2012 at 05:34:42PM -0200, Eduardo Habkost wrote:
> From: Igor Mammedov
>
> Signed-off-by: Igor Mammedov
> Acked-by: Andreas Färber
Reviewed-by: Eduardo Habkost
> ---
> qapi/qapi-visit-core.c | 11 +++
> qapi/qapi-visit-core.h | 2 ++
> qapi/string-input-v
From: Igor Mammedov
Signed-off-by: Igor Mammedov
Reviewed-by: Andreas Färber
---
target-i386/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 56a5646..5d11180 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -1195,7
From: Igor Mammedov
delay capping cpuid_level to 7 to realize time so property setters
for cpuid_7_0_ebx_features and "level" could be used in any order/time
between x86_cpu_initfn() and x86_cpu_realize().
Signed-off-by: Igor Mammedov
---
target-i386/cpu.c | 8 +---
1 file changed, 5 inser
Dear Andrzej,
> Most likely the function has never been in use. It is there for
> completeness of the API.
I've submitted a patch to create a header file for the TMP105 API [1].
Having this API makes sense because the probe is compatible with
several others (as documented in the patch, see also
On Tue, Dec 4, 2012 at 7:48 PM, Jovanovic, Petar wrote:
>> diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
>> index e7949c2..f8a7a9f 100644
>> --- a/target-mips/dsp_helper.c
>> +++ b/target-mips/dsp_helper.c
>> @@ -3814,17 +3814,17 @@ void helper_shilo(target_ulong ac, target_ulon
On Tue, Dec 04, 2012 at 05:34:43PM -0200, Eduardo Habkost wrote:
> From: Igor Mammedov
>
> Signed-off-by: Igor Mammedov
> Reviewed-by: Andreas Färber
Reviewed-by: Eduardo Habkost
> ---
> target-i386/cpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target-i386/
On Tue, Dec 4, 2012 at 7:43 PM, Richard Henderson wrote:
> On 2012-12-04 13:00, Blue Swirl wrote:
>>> > +if (rs5_0 == 0)
>>> > +return;
>> The check should be moved to translation time so that the call to this
>> helper is not generated at all.
>
> No, we'd do that only if this value w
On Tue, Dec 04, 2012 at 01:13:46PM -0600, Anthony Liguori wrote:
> "Daniel P. Berrange" writes:
>
> > On Tue, Dec 04, 2012 at 03:42:32PM +0100, Ján Tomko wrote:
> >> On 12/04/12 12:46, Luiz Capitulino wrote:
> >> > On Mon, 03 Dec 2012 16:55:35 +0100
> >> > Ján Tomko wrote:
> >> >
> >> >> Hello,
> diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
> index e7949c2..f8a7a9f 100644
> --- a/target-mips/dsp_helper.c
> +++ b/target-mips/dsp_helper.c
> @@ -3814,17 +3814,17 @@ void helper_shilo(target_ulong ac, target_ulong rs,
> CPUMIPSState *env)
>
> rs5_0 = rs & 0x3F;
>
From: Igor Mammedov
Signed-off-by: Igor Mammedov
---
target-i386/cpu.c | 6 +++---
target-i386/cpu.h | 2 ++
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 70ba323..05ac79a 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -110
On Tue, 4 Dec 2012 17:34:39 -0200
Eduardo Habkost wrote:
> Instead of using parsing the whole cpu_model string inside
> cpu_x86_find_by_name(), first split it into the CPU model name and the
> full feature string, then parse the feature string into pieces.
>
> When using CPU model classes, thos
On Tue, 4 Dec 2012 17:34:38 -0200
Eduardo Habkost wrote:
> - Use spaces instead of tabs on cpu_x86_cpuid().
> - Use braces on 'if' statement cpu_x86_find_by_name().
>
> Signed-off-by: Eduardo Habkost
> ---
> target-i386/cpu.c | 28 +++-
> 1 file changed, 15 insertions(
On Tue, Dec 04, 2012 at 05:34:40PM -0200, Eduardo Habkost wrote:
> From: Igor Mammedov
>
> Signed-off-by: Igor Mammedov
Reviewed-by: Eduardo Habkost
> ---
> target-i386/cpu.c | 6 +++---
> target-i386/cpu.h | 2 ++
> 2 files changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/target-i
On Sun, Nov 18, 2012 at 12:52 AM, Max Filippov wrote:
> cpu_get_phys_page_debug is not in sync with cpu_x86_handle_mmu_fault:
> the latter first checks CR0_PG_MASK and only after CR4_PAE_MASK.
>
> This fixes odd gdb code display with PAE enabled.
>
> Signed-off-by: Max Filippov
> ---
> target-i3
Changes v3:
- Fix memory leak spotted by Igor, on patch 2
Changes v2:
- Coding style changes (patches 1-2)
- Use "return -1" directly instead of "goto error" on cpu_x86_find_by_name()
(patch 2)
This series is based on the qom-cpu branch from afaerber's tree. The full
branch can be found in
On Tue, Dec 04, 2012 at 05:34:41PM -0200, Eduardo Habkost wrote:
> From: Igor Mammedov
>
> delay capping cpuid_level to 7 to realize time so property setters
> for cpuid_7_0_ebx_features and "level" could be used in any order/time
> between x86_cpu_initfn() and x86_cpu_realize().
>
> Signed-off-
Instead of using parsing the whole cpu_model string inside
cpu_x86_find_by_name(), first split it into the CPU model name and the
full feature string, then parse the feature string into pieces.
When using CPU model classes, those two pieces of information will be
used at different moments (CPU mod
From: Igor Mammedov
Signed-off-by: Igor Mammedov
Acked-by: Andreas Färber
---
qapi/qapi-visit-core.c | 11 +++
qapi/qapi-visit-core.h | 2 ++
qapi/string-input-visitor.c | 22 ++
3 files changed, 35 insertions(+)
diff --git a/qapi/qapi-visit-core.c b/qap
- Use spaces instead of tabs on cpu_x86_cpuid().
- Use braces on 'if' statement cpu_x86_find_by_name().
Signed-off-by: Eduardo Habkost
---
target-i386/cpu.c | 28 +++-
1 file changed, 15 insertions(+), 13 deletions(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
in
Instead of using parsing the whole cpu_model string inside
cpu_x86_find_by_name(), first split it into the CPU model name and the
full feature string, then parse the feature string into pieces.
When using CPU model classes, those two pieces of information will be
used at different moments (CPU mod
* Define constants for TMP105 registers.
* Move tmp105_set() from I2C to TMP105 header.
Signed-off-by: Alex Horn
---
hw/i2c.h|3 ---
hw/tmp105.c | 17 +
hw/tmp105.h | 34 ++
3 files changed, 43 insertions(+), 11 deletions(-)
create mod
From: Igor Mammedov
Signed-off-by: Igor Mammedov
---
target-i386/cpu.c | 6 +++---
target-i386/cpu.h | 2 ++
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 4090152..86d7a61 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -110
From: Igor Mammedov
Signed-off-by: Igor Mammedov
Reviewed-by: Andreas Färber
---
target-i386/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index a56a130..f8ba569 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -1195,7
On Tue, Dec 4, 2012 at 6:42 PM, Peter Maydell wrote:
> On 4 December 2012 18:38, Blue Swirl wrote:
>> The definition of the hard freeze bothers me. A few patches that went
>> in after 1.3-rc0 were not bug fixes but just new features, so the
>> difference between soft and hard freezes was not clea
"Daniel P. Berrange" writes:
> On Tue, Dec 04, 2012 at 03:42:32PM +0100, Ján Tomko wrote:
>> On 12/04/12 12:46, Luiz Capitulino wrote:
>> > On Mon, 03 Dec 2012 16:55:35 +0100
>> > Ján Tomko wrote:
>> >
>> >> Hello,
>> >>
>> >> is there a way to check if QEMU was compiled with --enable-seccomp v
On Tue, 4 Dec 2012 16:58:19 -0200
Eduardo Habkost wrote:
> Instead of using parsing the whole cpu_model string inside
> cpu_x86_find_by_name(), first split it into the CPU model name and the
> full feature string, then parse the feature string into pieces.
>
> When using CPU model classes, thos
On Tue, Dec 04, 2012 at 08:05:43PM +0100, Andreas Färber wrote:
> Am 04.12.2012 20:01, schrieb Eduardo Habkost:
> > On Tue, Dec 04, 2012 at 06:55:17PM +, Blue Swirl wrote:
> >> On Tue, Dec 4, 2012 at 1:19 PM, Eduardo Habkost
> >> wrote:
> >>> +static int parse_drive(DeviceState *dev, const ch
Am 04.12.2012 20:01, schrieb Eduardo Habkost:
> On Tue, Dec 04, 2012 at 06:55:17PM +, Blue Swirl wrote:
>> On Tue, Dec 4, 2012 at 1:19 PM, Eduardo Habkost wrote:
>>> +static int parse_drive(DeviceState *dev, const char *str, void **ptr)
>>> +{
>>> +BlockDriverState *bs;
>>> +
>>> +bs =
On Tue, Dec 4, 2012 at 7:01 PM, Eduardo Habkost wrote:
> On Tue, Dec 04, 2012 at 06:55:17PM +, Blue Swirl wrote:
>> On Tue, Dec 4, 2012 at 1:19 PM, Eduardo Habkost wrote:
>> > This separates the qdev properties code in two parts:
>> > - qdev-properties.c, that contains most of the qdev prope
On Tue, Dec 4, 2012 at 2:49 PM, Petar Jovanovic
wrote:
> From: Petar Jovanovic
>
> helper_shilo has not been shifting an accumulator value correctly for negative
> values in 'shift' field. Minor optimization for shift=0 case.
> This change also adds tests that will trigger issue and check for reg
On Tue, Dec 04, 2012 at 06:55:17PM +, Blue Swirl wrote:
> On Tue, Dec 4, 2012 at 1:19 PM, Eduardo Habkost wrote:
> > This separates the qdev properties code in two parts:
> > - qdev-properties.c, that contains most of the qdev properties code;
> > - qdev-properties-system.c for code specific
- Use spaces instead of tabs on cpu_x86_cpuid().
- Use braces on 'if' statement cpu_x86_find_by_name().
Signed-off-by: Eduardo Habkost
---
target-i386/cpu.c | 28 +++-
1 file changed, 15 insertions(+), 13 deletions(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
in
Changes v1 -> v2:
- Coding style changes (patches 1-2)
- Use "return -1" directly instead of "goto error" on cpu_x86_find_by_name()
(patch 2)
This series is based on the qom-cpu branch from afaerber's tree. The full
branch can be found in a git tree, at:
git://github.com/ehabkost/qemu-hacks
From: Igor Mammedov
Signed-off-by: Igor Mammedov
Acked-by: Andreas Färber
---
qapi/qapi-visit-core.c | 11 +++
qapi/qapi-visit-core.h | 2 ++
qapi/string-input-visitor.c | 22 ++
3 files changed, 35 insertions(+)
diff --git a/qapi/qapi-visit-core.c b/qap
From: Igor Mammedov
delay capping cpuid_level to 7 to realize time so property setters
for cpuid_7_0_ebx_features and "level" could be used in any order/time
between x86_cpu_initfn() and x86_cpu_realize().
Signed-off-by: Igor Mammedov
---
target-i386/cpu.c | 8 +---
1 file changed, 5 inser
Paolo Bonzini writes:
> Il 11/10/2012 09:25, M. Mohan Kumar ha scritto:
>> Also as per the man page:
>>When glibc determines that the argument is not a valid user ID,
>>it will return -1 and set errno to EINVAL
>>without attempting the system call.
>>
>> If it mean a no
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