Hello all:
At present, I met an issue (I guess, it should be my code bug), I am
analyzing it which may spend quite a few time resources (checking and
reconstructing the code is helpful for analyzing this issue):
- It is about invalid memory access for ld operation. The related
tilegx code is
On 4/29/15 21:32, Chen Gang wrote:
> On 4/29/15 05:43, Peter Maydell wrote:
>> On 28 April 2015 at 22:32, Chen Gang wrote:
>>> The related information for cmpexch instruction:
>>>
>>> Description
>>>
>>> Compare the 8-byte contents of the CmpValue SPR with the 8-byte
>>> value in memor
On 05/01/2015 04:48 PM, Paolo Bonzini wrote:
On 01/05/2015 21:55, John Snow wrote:
Where it makes sense, use the new faster primitives.
For generally small reads/writes such as for the PRDT
and FIS packets, stick with the more wasteful but
easier to debug memread/memwrite.
For ahci-test;
Wi
Quoting Paolo Bonzini (2015-05-01 15:43:45)
>
>
> On 01/05/2015 01:03, Michael Roth wrote:
> >
> > I played around with the idea of temporarilly moving unparented, unfinalized
> > objects to an "orphan" container. It seemed like a fun way of tracking
> > leaked
> > objects, and avoids the asser
Signed-off-by: Stefan Berger
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 0b67c48..0e0f573 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -668,6 +668,12 @@ S: Maintained
F: hw/ssi/*
F: hw/block/m25p80.c
+TPM
+M: Stefan Berger
+S: Ma
On 04/02/2015 11:29 AM, Markus Armbruster wrote:
>
> * Implicit type definitions are made explicit, and given
> auto-generated names. These names start with ':' so they don't
> clash with the user's names.
>
> Example: a simple union implicitly defines an enumeration type for
> its disc
On 05/01/2015 04:48 PM, Paolo Bonzini wrote:
On 01/05/2015 21:55, John Snow wrote:
Where it makes sense, use the new faster primitives.
For generally small reads/writes such as for the PRDT
and FIS packets, stick with the more wasteful but
easier to debug memread/memwrite.
For ahci-test;
Wi
Public bug reported:
oVirt uses libvirt to run QEMU.
Images are passed to QEMU as files, not file descriptors.
When running images from a GlusterFS, the file descriptors may get invalidated
because of network problems or the glusterfs process being restarted.
In this case, the VM goes into paused
Looks like VDI is the only writable image format that does not use
write-with-barrier(sync) when updating the metadata. A sequence of commits
b0ad5a455d~078a458e077d6b0db2 fixes this for QCOW/COW/QCOW2/VPC/VMDK, but
the VDI does not issue a barrier by sync after updating the metadata.
This commit
On 01/05/2015 21:55, John Snow wrote:
> Where it makes sense, use the new faster primitives.
> For generally small reads/writes such as for the PRDT
> and FIS packets, stick with the more wasteful but
> easier to debug memread/memwrite.
>
> For ahci-test;
> With this patch:
> real 0m4.802s
> us
On 01/05/2015 01:03, Michael Roth wrote:
>
> I played around with the idea of temporarilly moving unparented, unfinalized
> objects to an "orphan" container. It seemed like a fun way of tracking leaked
> objects, and avoids the assert, but that got wierd pretty quickly... and
> having DEVICE_DEL
Now that we no longer have nested structs to visit, the use of
prefix strings is no longer required. Remove the code that is
no longer reachable.
Signed-off-by: Eric Blake
---
scripts/qapi-visit.py | 49 -
1 file changed, 12 insertions(+), 37 dele
A conflict must be marked even when the two dictionaries being
compared differ on whether the key is marked optional.
Signed-off-by: Eric Blake
---
scripts/qapi.py| 4 +++-
tests/qapi-schema/flat-union-branch-clash.json | 2 +-
tests/qapi-schema/struct-base-clash-
On 04/29/2015 07:06 AM, Eric Blake wrote:
> Our type inheritance for both 'struct' and for flat 'union' merges
> key/value pairs from the base class with those from the type in
> question. Although the C code currently boxes things so that there
> is a distinction between which member is referred
On 04/29/2015 07:06 AM, Eric Blake wrote:
> A future patch will be using a 'name':{dictionary} entry in the
> QAPI schema to specify a default value for an optional argument
> (see previous commit messages for more details why); but existing
> use of inline nested structs conflicts with that goal.
Signed-off-by: Eric Blake
---
This needs to be squashed into v7:22/39 to avoid a regression in QGA.
If you'd rather me post a single amended patch as v8, I can do that.
scripts/qapi-commands.py | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/scripts/qapi-commands.py
On 04/29/2015 07:06 AM, Eric Blake wrote:
> For a few QMP commands, we are forced to pass an arbitrary type
> without tracking it properly in QAPI. Among the existing clients,
> this unnamed type was spelled 'dict', 'visitor', and '**'; this
> patch standardizes on '**', matching the documentation
Previously, memset was just a frontend to write() and only
stupidly sent the pattern many times across the wire.
Let's not discuss who stupidly wrote it like that in the first place.
(Hint: It was me.)
Signed-off-by: John Snow
---
qtest.c | 20
tests/libqtest.c |
Where it makes sense, use the new faster primitives.
For generally small reads/writes such as for the PRDT
and FIS packets, stick with the more wasteful but
easier to debug memread/memwrite.
For ahci-test;
With this patch:
real0m4.802s
user0m3.506s
sys 0m2.393s
Without this series:
re
Adds new qtest protocol commands for base64 reads and writes,
as well as a proper command for memset instead of faking it
via write.
This improves the ahci-test performance on my machine from about
14 seconds to about 4.
==
For convenience, this branch is available at:
https://github.com/jnsnow/q
qtest currently has a static buffer of size 1024 that if we
overflow, ignores the additional data silently which leads
to hangs or stream failures.
Use glib's string facilities to allow arbitrarily long data,
but split this off into a new function, qtest_sendf.
Static data can still be sent using
For larger pieces of data that won't need to be debugged and
viewing the hex nibbles is unlikely to be useful, we can encode
data using base64 instead of encoding each byte as %02x, which
leads to some space savings and faster reads/writes.
For now, the default is left as hex nibbles in memwrite()
** Also affects: qemu
Importance: Undecided
Status: New
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1450881
Title:
qemu-system-sparc MUTEX_HELD assert and libC lock errors
Status in QE
On 01/05/2015 16:09, Eduardo Habkost wrote:
> +void object_property_add_const_link(Object *obj, const char *name,
> + const char *type, Object *child,
> + ObjectPropertyLinkFlags flags,
> +
From: Fabian Aggeler
This register is banked in GICs with Security Extensions. Storing the
non-secure copy of BPR in the abpr, which is an alias to the non-secure
copy for secure access. ABPR itself is only accessible from secure state
if the GIC implements Security Extensions.
Signed-off-by: Fa
Now that the GIC base class has state fields for the GICD_IGROUPRn
registers, make kvm_arm_gic_get() and kvm_arm_gic_put() write and
read them. This allows us to remove the check that made us
fail migration if the guest had set any of the group register bits.
Signed-off-by: Peter Maydell
---
hw/
From: Fabian Aggeler
The Interrupt Group Registers allow the guest to configure interrupts
into one of two groups, where Group0 are higher priority and may
be routed to IRQ or FIQ, and Group1 are lower priority and always
routed to IRQ. (In a GIC with the security extensions Group0 is
Secure inte
From: Fabian Aggeler
Grouping (GICv2) and Security Extensions change the behavior of EOIR
writes. Completing Group0 interrupts is only allowed from Secure state.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Message-id: 1429113742-8371-13-git-send-email-greg.bell...@linaro.org
[PMM
From: Fabian Aggeler
Grouping (GICv2) and Security Extensions change the behavior of IAR
reads. Acknowledging Group0 interrupts is only allowed from Secure
state and acknowledging Group1 interrupts from Secure state is only
allowed if AckCtl bit is set.
Signed-off-by: Fabian Aggeler
Signed-off-
From: Fabian Aggeler
ICDDCR/GICD_CTLR is banked if the GIC has the security extensions,
and the S (or only) copy has separate enable bits for Group0 and
Group1 enable if the GIC implements interrupt groups.
EnableGroup0 (Bit [1]) in GICv1 is architecturally IMPDEF. Since this
bit (Enable Non-sec
Switch the GIC's MMIO callback functions to the read_with_attrs
and write_with_attrs functions which provide MemTxAttrs. This will
allow the GIC to correctly handle secure and nonsecure register
accesses.
Signed-off-by: Peter Maydell
---
hw/intc/arm_gic.c | 144 ++
From: Fabian Aggeler
Connect FIQ output of the GIC CPU interfaces to the CPUs.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Message-id: 1429113742-8371-3-git-send-email-greg.bell...@linaro.org
[PMM: minor format tweak]
Signed-off-by: Peter Maydell
---
hw/arm/vexpress.c | 2 ++
1
This patch series adds support for GICv1 and GICv2 security
extensions, as well as support for GIC interrupt grouping on GICv2.
This is based on the work originally by Fabian and then by Greg.
I've gone through and dealt with all the issues I raised in code
review, and a few others I noticed as I
From: Fabian Aggeler
Create the outbound FIQ lines from the GIC to the CPUs; these are
used if the GIC has security extensions or grouping support.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Message-id: 1429113742-8371-2-git-send-email-greg.bell...@linaro.org
[PMM: added FIQ lin
From: Fabian Aggeler
Add a QOM property which allows the GIC Security Extensions to be
enabled. These are an optional part of the GICv1 and GICv2 architecture.
This commit just adds the property and some sanity checks that it
is only enabled on GIC revisions that support it.
Signed-off-by: Fabia
From: Greg Bellows
Connect FIQ output of the GIC CPU interfaces to the CPUs.
Signed-off-by: Greg Bellows
Message-id: 1429113742-8371-4-git-send-email-greg.bell...@linaro.org
[PMM: minor format tweak]
Signed-off-by: Peter Maydell
---
hw/arm/virt.c | 2 ++
1 file changed, 2 insertions(+)
diff
From: Fabian Aggeler
GICs with Security Extensions restrict the non-secure view of the
interrupt priority and priority mask registers.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Message-id: 1429113742-8371-15-git-send-email-greg.bell...@linaro.org
[PMM: minor code tweaks; fixed
From: Fabian Aggeler
For GICs with Security Extensions Non-secure reads have a restricted
view on the current running priority.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Message-id: 1429113742-8371-11-git-send-email-greg.bell...@linaro.org
[PMM: make function static, minor comm
Connect FIQ output of the GIC CPU interfaces to the CPUs.
Signed-off-by: Peter Maydell
---
hw/arm/highbank.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index b2d048b..f8353a7 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -217,6 +217,7
From: Fabian Aggeler
Grouping (GICv2) and Security Extensions change the behaviour of reads
of the highest priority pending interrupt register (ICCHPIR/GICC_HPPIR).
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
Message-id: 1429113742-8371-12-git-send-email-greg.bell...@linaro.org
[
Add support to gic_update() for determining the current IRQ
and FIQ status when interrupt grouping is supported. This
simply requires that instead of always raising IRQ we
check the group of the highest priority pending interrupt
and the GICC_CTLR.FIQEn bit to see whether we should raise
IRQ or FIQ
From: Fabian Aggeler
ICCICR/GICC_CTLR is banked in GICv1 implementations with Security
Extensions or in GICv2 in independent from Security Extensions.
This makes it possible to enable forwarding of interrupts from
the CPU interfaces to the connected processors for Group0 and Group1.
We also allo
On Wed, 29 Apr 2015 15:35:03 -0600
Eric Blake wrote:
> Here's my attempt to merge the best points of Markus' approach [1]
> (patches 16-18 of that series - benefit of smaller patches and fewer
> malloc calls) and my approach [2] (benefit of a testsuite addition
> and more detailed commit messages
On Fri, 24 Apr 2015 14:39:48 +0200
hw.clau...@gmail.com wrote:
> From: Claudio Fontana
>
> usage is similar to the commands x, xp.
>
> Example with string: looking for "ELF" header in memory:
>
> (qemu) s/100cb 0x40001000 "ELF"
> searching memory area [40001000-400f5240]
>
On Sat, 25 Apr 2015 12:28:06 -0300
Eduardo Habkost wrote:
> The QJSON code used casts to (QJSON*) directly, instead of OBJECT_CHECK.
> There were even some functions using object_dynamic_cast() calls
> followed by assert(), which is exactly what OBJECT_CHECK does (by
> calling object_dynamic_cast
Ping!
On Fri, Apr 24, 2015 at 1:28 PM, Peter Crosthwaite
wrote:
> Hi Peter and all,
>
> Xilinx's next gen SoC has been announced. This series adds a SoC and
> board.
>
> Series start with addition of ARM cortex A53 support (P1 and P2). The
> Soc skeleton is then added with GIC, EMACs and UARTs ar
On 04/29/2015 05:04 AM, Markus Armbruster wrote:
> Eric Blake writes:
>
>> Now that the two functions are identical, we only need one of them.
>>
>> Signed-off-by: Eric Blake
>
> c_var() isn't the possible best name, but it'll do.
I'm looking at using c_name() in my v3.
--
Eric Blake eblak
On 04/03/2015 07:05 AM, Paolo Bonzini wrote:
On 03/04/2015 12:01, Wen Congyang wrote:
Signed-off-by: Wen Congyang
Signed-off-by: zhanghailiang
Signed-off-by: Gonglei
---
include/qemu/hbitmap.h | 8
tests/test-hbitmap.c | 39 +++
util/hbi
Quoting Michael Roth (2015-05-01 11:19:05)
> Quoting Eduardo Habkost (2015-04-29 07:55:48)
> > On Wed, Apr 29, 2015 at 08:38:02AM -0400, Luiz Capitulino wrote:
> > > On Mon, 27 Apr 2015 14:23:20 -0300
> > > Eduardo Habkost wrote:
> > >
> > > > On Sat, Apr 25, 2015 at 07:05:55PM +0200, Andreas Fär
Quoting Eduardo Habkost (2015-04-29 07:55:48)
> On Wed, Apr 29, 2015 at 08:38:02AM -0400, Luiz Capitulino wrote:
> > On Mon, 27 Apr 2015 14:23:20 -0300
> > Eduardo Habkost wrote:
> >
> > > On Sat, Apr 25, 2015 at 07:05:55PM +0200, Andreas Färber wrote:
> > > > Am 25.04.2015 um 17:28 schrieb Eduar
On 01/05/2015 16:43, Peter Maydell wrote:
> On 1 May 2015 at 16:24, Yongbok Kim wrote:
>> MIPS SIMD Architecture vector loads and stores require misalignment support.
>> MSA Memory access should work as an atomic operation. Therefore, it has to
>> check validity of all the addresses for the operat
On 1 May 2015 at 16:24, Yongbok Kim wrote:
> MIPS SIMD Architecture vector loads and stores require misalignment support.
> MSA Memory access should work as an atomic operation. Therefore, it has to
> check validity of all the addresses for the operation.
>
> Signed-off-by: Yongbok Kim
> ---
> t
On 1 May 2015 at 16:24, Yongbok Kim wrote:
> Release 6 requires misaligned memory access support for all ordinary memory
> access instructions (for example, LW/SW, LWC1/SWC1).
> However misaligned support is not provided for certain special memory accesses
> such as atomics (for example, LL/SC).
>
This patch set adds support for misaligned memory accesses in MIPS architecture
Release 6 and MIPS SIMD Architecture.
The behaviour, semantics, and architecture specifications of misaligned memory
accesses are described in:
MIPS Architecture For Programmers Volume I-A: Introduction to the MIPS64
A
Release 6 requires misaligned memory access support for all ordinary memory
access instructions (for example, LW/SW, LWC1/SWC1).
However misaligned support is not provided for certain special memory accesses
such as atomics (for example, LL/SC).
In the mips_cpu_do_unaligned_access() callback, if i
Pass a data size argument to do_unaligned_access().
It is unable to find if an access spans two pages without the data size
in the call back function.
Signed-off-by: Yongbok Kim
---
include/qom/cpu.h |7 ---
softmmu_template.h | 24
target-alph
MIPS SIMD Architecture vector loads and stores require misalignment support.
MSA Memory access should work as an atomic operation. Therefore, it has to
check validity of all the addresses for the operation.
Signed-off-by: Yongbok Kim
---
target-mips/op_helper.c | 30 +++
On Thu, Apr 30, 2015 at 9:24 PM, Peter Crosthwaite
wrote:
> On Thu, Apr 30, 2015 at 11:14 AM, Christopher Covington
> wrote:
>> Present a system with an instructions per cycle of exactly one.
>> This makes it less likely a user will mistake the cycle counter
>> values as meaningful and makes calc
On Thu, Apr 30, 2015 at 01:11:41PM +0300, Alberto Garcia wrote:
> int qcow2_cache_put(BlockDriverState *bs, Qcow2Cache *c, void **table)
> {
> -int i;
> +int i = (*table - c->table_array) / c->table_size;
>
> -for (i = 0; i < c->size; i++) {
> -if (table_addr(c, i) == *table
On Thu, Apr 30, 2015 at 01:11:40PM +0300, Alberto Garcia wrote:
> Qcow2Cache *qcow2_cache_create(BlockDriverState *bs, int num_tables)
> {
> BDRVQcowState *s = bs->opaque;
> Qcow2Cache *c;
> -int i;
>
> c = g_new0(Qcow2Cache, 1);
> c->size = num_tables;
> +c->table_s
On Thu, Apr 30, 2015 at 03:15:50PM +0200, Kevin Wolf wrote:
> Signed-off-by: Kevin Wolf
> ---
> MAINTAINERS | 6 ++
> 1 file changed, 6 insertions(+)
Reviewed-by: Stefan Hajnoczi
pgpZOSUrkHzxh.pgp
Description: PGP signature
It can be used in simpler cases where a read-only property is needed.
Signed-off-by: Eduardo Habkost
---
include/qom/object.h | 23 +++
qom/object.c | 15 +++
2 files changed, 38 insertions(+)
diff --git a/include/qom/object.h b/include/qom/object.h
index
This will provide a predictable path for the CPU objects, and a more
powerful alternative for the query-cpus QMP command, as now every QOM
property on CPU objects can be easily queried.
Signed-off-by: Eduardo Habkost
---
Changes v1 -> v2:
* Use object_property_add_const_link()
* Use "/machine/cpu
Changes v1 -> v2:
* Implement a object_property_add_const_link() function
* Use "/machine/cpus[]" instead of "/machine/cpus/"
* Grab reference to object before adding link
Eduardo Habkost (2):
qom: Implement object_property_add_const_link()
cpu: Register QOM links at /machine/cpus[]
exec.c
On 30-04-15 18:35, Thomas Huth wrote:
On Thu, 30 Apr 2015 16:29:58 +0200
Justin Ossevoort wrote:
The current guest-fstrim support only returns an error if some
mountpoint was unable to be trimmed, skipping any possible additional
mountpoints. The result of the TRIM operation itself is also dis
On 05/01/2015 04:44 AM, Daniel P. Berrange wrote:
> The qemu_acl_init() function has long since stopped being able
> to return NULL, since g_malloc will abort on OOM. As such the
> checks for NULL were unreachable code.
>
> Signed-off-by: Daniel P. Berrange
> ---
> ui/vnc.c | 8
> 1 fil
On Thu, Apr 30, 2015 at 06:51:43PM -0700, Peter Crosthwaite wrote:
> On Thu, Apr 30, 2015 at 12:19 PM, Eduardo Habkost wrote:
> > This will provide a predictable path for the CPU objects, and a more
> > powerful alternative for the query-cpus QMP command, as now every QOM
> > property on CPU objec
On Thu, Apr 30, 2015 at 10:21:55PM +0200, Andreas Färber wrote:
> First I did not participate in that discussion, second nack to that
> self pointer. Please hold off on this until I'm back. Andreas
I suggested it 3 times before. The message mentioned in the patch has
pointers to the other 2 discus
On Wed, Apr 29, 2015 at 09:18:27PM +0200, Paolo Bonzini wrote:
> On 27/04/2015 19:23, Eduardo Habkost wrote:
> > Also, why do we have two JSON writers in QEMU? And why do they have
> > exactly the same name?
>
> qobject/qjson.c could use qjson.c... but then qjson.c probably should be
> changed 1)
On Thu, Apr 30, 2015 at 11:47:09PM +0200, Paolo Bonzini wrote:
>
>
> On 30/04/2015 22:21, Andreas Färber wrote:
> >>+cpu->self = cobj;
> >>+object_property_add_link(cpu_container, path, TYPE_CPU, &cpu->self,
> >>NULL,
> >>+ OBJ_PROP_LINK_UNREF_ON_RELEASE, &err
The qemu_acl_init() function has long since stopped being able
to return NULL, since g_malloc will abort on OOM. As such the
checks for NULL were unreachable code.
Signed-off-by: Daniel P. Berrange
---
ui/vnc.c | 8
1 file changed, 8 deletions(-)
diff --git a/ui/vnc.c b/ui/vnc.c
index
Now that properties can be explicitly registered as an enum
type, there is no need to pass the string table to the
object_get_enum method. The object property registration
already has a pointer to the string table.
In changing this method signature, the hostmem backend object
has to be converted t
The enum string table parameters in various QOM/QAPI methods
are declared 'const char *strings[]'. This results in const
warnings if passed a variable that was declared as
static const char * const strings[] = { };
Add the extra const annotation to the parameters, since
neither the string
Some types of object must be created before chardevs, other types of
object must be created after chardevs. As such there is no option but
to create objects in two phases.
This takes the decision to create as many object types as possible
in the first phase, and only delay those which have a depen
The QEMU help for -object is essentially useless, just giving users
the generic syntax. Move it down into its own section and introduce
a nested table where each user creatable object can be documented.
The existing memory-backend-file, rng-random and rng-egd object
types are documented.
Signed-of
It is reasonably common to want to create an object, set a
number of properties, register it in the hierarchy and then
mark it as complete (if a user creatable type). This requires
quite a lot of error prone, verbose, boilerplate code to achieve.
The object_new_propv / object_new_proplist construc
A QOM property can be parsed as enum using the visit_type_enum()
helper method, but this forces callers to use the more complex
generic object_property_add() method when registering it. It
also requires that users of that object have access to the
string map when they want to read the property valu
This series contains the 7 generic QOM API fixes and enhancements
that I previously posted as part of the large series refactoring
and extending the TLS support in QEMU:
https://lists.gnu.org/archive/html/qemu-devel/2015-04/msg02038.html
I'm sending it separately, since the patches are reasonab
The 'policy' property was being registered with a typename of
'str', but it is in fact an enum of the 'HostMemPolicy' type.
Signed-off-by: Daniel P. Berrange
---
backends/hostmem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/backends/hostmem.c b/backends/hostmem.c
index b
On Thu, Apr 30, 2015 at 04:46:37PM +0100, Daniel P. Berrange wrote:
> A QOM property can be parsed as enum using the visit_type_enum()
> helper method, but this forces callers to use the more complex
> generic object_property_add() method when registering it. It
> also requires that users of that o
On 30 April 2015 at 20:10, Kevin Wolf wrote:
> The following changes since commit 06feaacfb4cfef10cc0c93d97df7bfc8a71dbc7e:
>
> Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into
> staging (2015-04-30 12:04:11 +0100)
>
> are available in the git repository at:
>
>
> git://r
From: Michael Roth
This device emulates a firmware abstraction used by pSeries guests to
manage hotplug/dynamic-reconfiguration of host-bridges, PCI devices,
memory, and CPUs. It is conceptually similar to an SHPC device,
complete with LED indicators to identify individual slots to physical
physi
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