[Qemu-devel] [RFC 4/9] target-ppc: Use actual page size encodings from HPTE

At present the 64-bit hash MMU code uses information from the SLB to determine the page size of a translation. We do need that information to correctly look up the hash table. However the MMU also allows a possibly larger page size to be encoded into the HPTE itself, which is used to populate the

[Qemu-devel] [RFC 9/9] target-ppc: Allow more page sizes for POWER7 & POWER8 in TCG

Now that the TCG and spapr code has been extended to allow (semi-) arbitrary page encodings in the CPU's 'sps' table, we can add the many page sizes supported by real POWER7 and POWER8 hardware that we previously didn't support in TCG. Signed-off-by: David Gibson --- target-ppc/mmu-hash64.h

[Qemu-devel] [RFC 8/9] target-ppc: Helper to determine page size information from hpte alone

h_enter() in the spapr code needs to know the page size of the HPTE it's about to insert. Unlike other paths that do this, it doesn't have access to the SLB, so at the moment it determines this with some open-coded tests which assume POWER7 or POWER8 page size encodings. To make this more flexibl

[Qemu-devel] [RFC 2/9] target-ppc: Convert mmu-hash{32, 64}.[ch] from CPUPPCState to PowerPCCPU

Like a lot of places these files include a mixture of functions taking both the older CPUPPCState *env and newer PowerPCCPU *cpu. Move a step closer to cleaning this up by standardizing on PowerPCCPU, except for the helper_* functions which are called with the CPUPPCState * from tcg. Callers and

[Qemu-devel] [RFC 6/9] target-ppc: Split 44x tlbiva from ppc_tlb_invalidate_one()

Currently both the tlbiva instruction (used on 44x chips) and the tlbie instruction (used on hash MMU chips) are both handled via ppc_tlb_invalidate_one(). This is silly, because they're invoked from different places, and do different things. Clean this up by separating out the tlbiva instruction

[Qemu-devel] [RFC 3/9] target-ppc: Rework SLB page size lookup

Currently, the ppc_hash64_page_shift() function looks up a page size based on information in an SLB entry. It open codes the bit translation for existing CPUs, however different CPU models can have different SLB encodings. We already store those in the 'sps' table in CPUPPCState, but we don't cur

[Qemu-devel] [RFC 7/9] target-ppc: Add new TLB invalidate by HPTE call for hash64 MMUs

When HPTEs are removed or modified by hypercalls on spapr, we need to invalidate the relevant pages in the qemu TLB. Currently we do that by doing some complicated calculations to work out the right encoding for the tlbie instruction, then passing that to ppc_tlb_invalidate_one()... which totally

[Qemu-devel] [RFC 1/9] target-ppc: Remove unused kvmppc_read_segment_page_sizes() stub

This stub function is in the !KVM ifdef in target-ppc/kvm_ppc.h. However no such function exists on the KVM side, or is ever used. I think this originally referenced a function which read host page size information from /proc, for we we now use the KVM GET_SMMU_INFO extension instead. In any cas

[Qemu-devel] [RFC 5/9] target-ppc: Remove unused mmu models from ppc_tlb_invalidate_one

ppc_tlb_invalidate_one() has a big switch handling many different MMU types. However, most of those branches can never be reached: It is called from 3 places: from remove_hpte() and h_protect() in spapr_hcall.c (which always has a 64-bit hash MMU type), and from helper_tlbie() in mmu_helper.c. C

[Qemu-devel] [RFC 0/9] Clean up page size handling for ppc 64-bit hash MMUs with TCG

Encoding of page sizes on 64-bit hash MMUs for Power is rather arcane, involving control bits in both the SLB and HPTE. At present we support a few of the options, but far fewer than real hardware. We're able to get away with that in practice, because guests use a device tree property to determin

[Qemu-devel] [PATCH] net: cadence_gem: check packet size in gem_recieve

From: Prasad J Pandit While receiving packets in 'gem_receive' routine, if Frame Check Sequence(FCS) is enabled, it copies the packet into a local buffer without checking its size. Add check to validate packet length against the buffer size to avoid buffer overflow. Reported-by: Ling Liu Signed

Re: [Qemu-devel] [Qemu-arm] [PATCH] cadence_gem: fix buffer overflow

On Thu, Jan 14, 2016 at 2:03 AM, Peter Maydell wrote: > On 14 January 2016 at 09:43, Michael S. Tsirkin wrote: >> gem_receive copies a packet received from network into an rxbuf[2048] >> array on stack, with size limited by descriptor length set by guest. If >> guest is malicious and specifies a

Re: [Qemu-devel] [PATCH] cadence_gem: fix buffer overflow

+-- On Fri, 15 Jan 2016, Jason Wang wrote --+ | Looks like we need similar issue in gen_receive(), need to fix that? Yes, I'm preparing a patch. -- Prasad J Pandit / Red Hat Product Security Team 47AF CE69 3A90 54AA 9045 1053 DD13 3D32 FE5B 041F

[Qemu-devel] [Bug 1531632] Re: Can't compile qemu because of errors in the Xen code

OK. I am closing this then. :) ** Changed in: qemu Status: New => Invalid -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1531632 Title: Can't compile qemu because of errors in the Xen code

[Qemu-devel] [Bug 1534382] Re: loadvm makes Windows 7 x86 guest crash with some CPUs

What is your host processor? -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1534382 Title: loadvm makes Windows 7 x86 guest crash with some CPUs Status in QEMU: New Bug description: Running qe

Re: [Qemu-devel] [PATCH v4] qemu-char: add logfile facility to all chardev backends

On 01/11/2016 05:44 AM, Daniel P. Berrange wrote: > Typically a UNIX guest OS will log boot messages to a serial > port in addition to any graphical console. An admin user > may also wish to use the serial port for an interactive > console. A virtualization management system may wish to > collect s

[Qemu-devel] [PATCH 5/6] qmp-commands.hx: Fix the missing options for migration parameters commands

We didn't document x-cpu-throttle-initial/x-cpu-throttle-increment for commands migrate-set-parameters and query-migrate-parameters. Here we add the descriptions for these two options and fix the wrong example for query-migrate-parameters qmp commands. Besides, this will also fix the bug that we c

[Qemu-devel] [PATCH 3/6] savevm: Split load vm state function qemu_loadvm_state

qemu_loadvm_state is too long, and we can simplify it by splitting up with three helper functions. Signed-off-by: zhanghailiang Reviewed-by: Dr. David Alan Gilbert --- migration/savevm.c | 156 +++-- 1 file changed, 92 insertions(+), 64 deletions(

[Qemu-devel] [PATCH 4/6] migration/ram: Fix some helper functions' parameter to use PageSearchStatus

Some helper functions use parameters 'RAMBlock *block' and 'ram_addr_t *offset', We can use 'PageSearchStatus *pss' directly instead, with this change, we can reduce the number of parameters for these helper function, also it is easily to add new parameters for these helper functions. Signed-off-b

[Qemu-devel] [PATCH 1/6] ram: Split host_from_stream_offset() into two helper functions

Split host_from_stream_offset() into two parts: One is to get ram block, which the block idstr may be get from migration stream, the other is to get hva (host) address from block and the offset. Besides, we will do the check working in a new helper offset_in_ramblock(). Signed-off-by: zhanghailian

[Qemu-devel] [PATCH 0/6] Some improvements and small fixes for migration

Patch 1 ~ patch 4 are picked from COLO and live memory snapshot series, They are just small improvements for migration codes and have been reviewed by Dave. Patch 5, 6 are small fixes for migration releated documention. Please review. zhanghailiang (6): ram: Split host_from_stream_offset() in

[Qemu-devel] [PATCH 6/6] qmp-commands.hx: Document the missing options for migration capability commands

Add the missing descriptions for the options of migration capability commands, and fix the example for query-migrate-capabilities command. Signed-off-by: zhanghailiang --- qmp-commands.hx | 15 ++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/qmp-commands.hx b/qmp-co

[Qemu-devel] [PATCH 2/6] migration: Rename the'file' member of MigrationState

Rename the 'file' member of MigrationState to 'to_dst_file'. Signed-off-by: zhanghailiang Reviewed-by: Dr. David Alan Gilbert --- include/migration/migration.h | 2 +- migration/exec.c | 4 +-- migration/fd.c| 4 +-- migration/migration.c | 72 +++

Re: [Qemu-devel] [PATCH] cadence_gem: fix buffer overflow

On 01/14/2016 05:43 PM, Michael S. Tsirkin wrote: > gem_receive copies a packet received from network into an rxbuf[2048] > array on stack, with size limited by descriptor length set by guest. If > guest is malicious and specifies a descriptor length that is too large, > and should packet size e

Re: [Qemu-devel] [PATCH] intel_iommu: large page support

On 01/14/2016 05:28 PM, Michael S. Tsirkin wrote: > On Thu, Jan 14, 2016 at 12:47:24AM -0500, Jason Wang wrote: >> > Current intel_iommu only supports 4K page which may not be sufficient >> > to cover guest working set. This patch tries to enable 2M and 1G mapping >> > for intel_iommu. This is al

Re: [Qemu-devel] [PATCH v5 2/5] Add Error **errp for xen_host_pci_device_get()

On 01/15/2016 06:29 AM, Eric Blake wrote: On 01/13/2016 05:51 AM, Cao jin wrote: To catch the error msg. Also modify the caller Signed-off-by: Cao jin --- hw/xen/xen-host-pci-device.c | 142 +-- hw/xen/xen-host-pci-device.h | 5 +- hw/xen/xen_pt.

[Qemu-devel] [PATCH v4 2/2] change type of pci_bridge_initfn() to void

Since it can`t fail. Also modify the callers. Signed-off-by: Cao jin Reviewed-by: Markus Armbruster --- hw/pci-bridge/i82801b11.c | 5 + hw/pci-bridge/ioh3420.c| 6 +- hw/pci-bridge/pci_bridge_dev.c | 8 +++- hw/pci-bridge/xio3130_downstream.c | 6 +- hw

[Qemu-devel] [PATCH v4 0/2] change type of pci_bridge_initfn()

v4 changelog: 1. fix apb bridge build fail as Marcel find. Test: 1. Compiled on all arch(configure without param) 2. make check passed 3. Hacked to test dec bridge realization, passed. Cao jin (2): dec: convert to realize() change type of pci_bridge_initfn() to void hw/pci-bridge/dec.c

[Qemu-devel] [PATCH v4 1/2] dec: convert to realize()

Also because pci_bridge_initfn() can`t fail. Signed-off-by: Cao jin Reviewed-by: Markus Armbruster Reviewed-by: Marcel Apfelbaum --- hw/pci-bridge/dec.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/pci-bridge/dec.c b/hw/pci-bridge/dec.c index 28d0ff9..be0fc46 10

[Qemu-devel] [PATCH v4 1/2] blockdev: Error out on negative throttling option values

The implicit casting from unsigned int to double changes negative values into large positive numbers and accepts them. We should instead print an error. Check the number range so this case is caught and reported. Signed-off-by: Fam Zheng Reviewed-by: Max Reitz --- blockdev.c | 3

[Qemu-devel] [PATCH v4 2/2] iotests: Test that negative and large throttle values are rejected

Signed-off-by: Fam Zheng Reviewed-by: Max Reitz --- tests/qemu-iotests/051| 12 tests/qemu-iotests/051.out| 24 tests/qemu-iotests/051.pc.out | 24 3 files changed, 60 insertions(+) diff --git a/tests/qemu-iotests/051 b/

[Qemu-devel] [PATCH v4 0/2] block: Reject negative values for throttling options

v4: Add Max's rev-by in both patches, while fixing the "maxs" typo. v3: Address comments: - Add test for large value; [Berto] - Fix typos "negative" & "caught"; [Eric, Berto] - Use "LL" suffix to the upper limit constant. [Berto] v2: Check the value range and report an appropriate err

Re: [Qemu-devel] [Qemu-block] [PATCH v3 1/2] blockdev: Error out on negative throttling option values

On Thu, 01/14 16:50, Max Reitz wrote: > On 14.01.2016 16:46, Max Reitz wrote: > > On 14.01.2016 05:08, Fam Zheng wrote: > >> The implicit casting from unsigned int to double changes negative values > >> into large positive numbers and accepts them. We should instead print > >> an error. > >> > >>

Re: [Qemu-devel] [PATCH v3 2/2] change type of pci_bridge_initfn() to void

On 01/14/2016 11:42 PM, Marcel Apfelbaum wrote: On 01/14/2016 02:23 PM, Cao jin wrote: diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index 599768e..e9117b9 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -636,10 +636,7 @@ static int apb_pci_bridge_initfn(PCIDevice *dev) {

[Qemu-devel] [Bug 1534382] [NEW] loadvm makes Windows 7 x86 guest crash with some CPUs

Public bug reported: Running qemu with kvm enabled and -cpu set to some of the more "modern" CPUs, and having Windows 7 x86 as the guest. After guest OS loads, start some app (I started "cmd"), then do "savevm". After that, do some more activity (I closed cmd window and opened IE), then do "loadv

Re: [Qemu-devel] [PATCH v3 7/7] raspi: add raspberry pi 2 machine

On Thu, Jan 14, 2016 at 4:43 PM, Andrew Baumann wrote: >> From: Peter Crosthwaite [mailto:crosthwaitepe...@gmail.com] >> Sent: Thursday, 14 January 2016 15:35 >> >> On Thu, Jan 14, 2016 at 3:04 PM, Andrew Baumann >> wrote: >> > Hi Peter, >> > >> >> From: Peter Crosthwaite [mailto:crosthwaitepe...

Re: [Qemu-devel] about the 'mptable' issue

> On Thu, Jan 14, 2016 at 10:36:07AM +, Li, Liang Z wrote: > > Correct something. > > The actual parameter for QEMU in our test case is: > > 'qemu-systerm-x86_64 -enable-kvm -smp 20 -m 2048 -no-acpi -monitor > > stdio -drive file=/mnt/centos6u6.qcow, if=none, id=foo -device virtio-blk- > p

[Qemu-devel] DPDK application using vhost-user segfaults when guest is rebooted/shutdown

If a guest has vhost-user enabled, then on reboot vhost_virtqueue_stop is invoked. This unmaps vring memory. However, it will not give any indication to the underlying DPDK application about it. Therefore, a pollmode DPDK driver tries to read the ring to check for packets and segfaults. We do have

Re: [Qemu-devel] [PATCH v3 7/7] raspi: add raspberry pi 2 machine

> From: Peter Crosthwaite [mailto:crosthwaitepe...@gmail.com] > Sent: Thursday, 14 January 2016 15:35 > > On Thu, Jan 14, 2016 at 3:04 PM, Andrew Baumann > wrote: > > Hi Peter, > > > >> From: Peter Crosthwaite [mailto:crosthwaitepe...@gmail.com] > >> Sent: Tuesday, 12 January 2016 16:44 > >> On T

Re: [Qemu-devel] [PATCH v2] pc: allow raising low memory via max-ram-below-4g option

On 01/08/2016 05:58 AM, Gerd Hoffmann wrote: > This patch extends the functionality of the max-ram-below-4g option > to also allow increasing lowmem. Use case: Give as much memory as > possible to legacy non-PAE guests. > > While being at it also rework the lowmem calculation logic and add a > lo

Re: [Qemu-devel] [Qemu-arm] [PATCH v3 12/19] qom/cpu: Add MemoryRegion property

CC Andrew, This may be the missing feature for your system_memory for CPU RAM access problem. Regards, Peter On Thu, Jan 14, 2016 at 5:52 AM, Peter Maydell wrote: > From: Peter Crosthwaite > > Add a MemoryRegion property, which if set is used to construct > the CPU's initial (default) AddressS

Re: [Qemu-devel] [PATCH v3 7/7] raspi: add raspberry pi 2 machine

On Thu, Jan 14, 2016 at 3:04 PM, Andrew Baumann wrote: > Hi Peter, > >> From: Peter Crosthwaite [mailto:crosthwaitepe...@gmail.com] >> Sent: Tuesday, 12 January 2016 16:44 >> On Tue, Jan 12, 2016 at 3:53 PM, Andrew Baumann >> wrote: >> >> From: Peter Crosthwaite [mailto:crosthwaitepe...@gmail.com

Re: [Qemu-devel] [PATCH v7] spec: add qcow2 bitmaps extension specification

On 01/14/2016 05:08 PM, Eric Blake wrote: > On 01/11/2016 06:05 AM, Vladimir Sementsov-Ogievskiy wrote: >> The new feature for qcow2: storing bitmaps. >> >> This patch adds new header extension to qcow2 - Bitmaps Extension. It >> provides an ability to store virtual disk related bitmaps in a qcow

Re: [Qemu-devel] [vfio-users] [PATCH v2 1/3] input: add qemu_input_qcode_to_linux + qemu_input_linux_to_qcode

ok, now works tnx Gerd! but i found 2 problems, one with keyboard and other with the mouse Keyboard: the repetition (hold the key) don't work. Mouse: only detect 3 buttons (my Logitech G5 Laser Have 7) this is spected? greetings

Re: [Qemu-devel] [PATCH v3 7/7] raspi: add raspberry pi 2 machine

Hi Peter, > From: Peter Crosthwaite [mailto:crosthwaitepe...@gmail.com] > Sent: Tuesday, 12 January 2016 16:44 > On Tue, Jan 12, 2016 at 3:53 PM, Andrew Baumann > wrote: > >> From: Peter Crosthwaite [mailto:crosthwaitepe...@gmail.com] > >> Sent: Monday, 11 January 2016 19:58 > >> > +/* Alloca

[Qemu-devel] [Bug 1531632] Re: Can't compile qemu because of errors in the Xen code

Hello pranith, Well, as I'm using the "ABS" system from Arch Linux, I had to study how it compile things, but I found it: ./configure --prefix=/usr --sysconfdir=/etc --audio-drv-list='pa alsa sdl' \ --python=/usr/bin/python2 --smbd=/usr/bin/smbd \ --enable-docs --lib

Re: [Qemu-devel] [PATCH v5 0/5] Xen PCI passthru: Convert to realize()

On 01/14/2016 09:50 AM, Stefano Stabellini wrote: > Eric, > > I'll wait for your reviewed-by on the whole series before committing. Found a bug in 2/5, up to you if you want to fix that or wait for a v6. > On Wed, 13 Jan 2016, Cao jin wrote: >> v5 changelog: >> 1. tweaked the commit message of p

Re: [Qemu-devel] [PATCH v5 5/5] Xen PCI passthru: convert to realize()

On 01/13/2016 05:51 AM, Cao jin wrote: > Signed-off-by: Cao jin > --- > hw/xen/xen_pt.c | 53 - > 1 file changed, 28 insertions(+), 25 deletions(-) Reviewed-by: Eric Blake -- Eric Blake eblake redhat com+1-919-301-3266 Libvirt virtuali

Re: [Qemu-devel] [PATCH v5 4/5] Add Error **errp for xen_pt_config_init()

On 01/13/2016 05:51 AM, Cao jin wrote: > To catch the error msg. Also modify the caller Doesn't hurt to spell out 'message' instead of 'msg' (here and in other patches), but not a show-stopper. > > Signed-off-by: Cao jin > --- > hw/xen/xen_pt.c | 8 --- > hw/xen/xen_pt.h

Re: [Qemu-devel] [PATCH v5 3/5] Add Error **errp for xen_pt_setup_vga()

On 01/13/2016 05:51 AM, Cao jin wrote: > To catch the error msg. Also modify the caller > > Signed-off-by: Cao jin > --- > hw/xen/xen_pt.c | 7 +-- > hw/xen/xen_pt.h | 3 ++- > hw/xen/xen_pt_graphics.c | 11 ++- > 3 files changed, 13 insertions(+), 8 deletions(-)

Re: [Qemu-devel] [PATCH v5 2/5] Add Error **errp for xen_host_pci_device_get()

On 01/13/2016 05:51 AM, Cao jin wrote: > To catch the error msg. Also modify the caller > > Signed-off-by: Cao jin > --- > hw/xen/xen-host-pci-device.c | 142 > +-- > hw/xen/xen-host-pci-device.h | 5 +- > hw/xen/xen_pt.c | 13 ++-- > 3 fi

Re: [Qemu-devel] [PATCH v5 1/5] Xen: use qemu_strtoul instead of strtol

On 01/13/2016 05:51 AM, Cao jin wrote: > No need to roll our own (with slightly incorrect handling of errno), > when we can use the common version. > > Change signed parsing to unsigned, because what it read are values in > PCI config space, which are non-negative. > > Signed-off-by: Cao jin > -

Re: [Qemu-devel] [PATCH v7] spec: add qcow2 bitmaps extension specification

On 01/11/2016 06:05 AM, Vladimir Sementsov-Ogievskiy wrote: > The new feature for qcow2: storing bitmaps. > > This patch adds new header extension to qcow2 - Bitmaps Extension. It > provides an ability to store virtual disk related bitmaps in a qcow2 > image. For now there is only one type of such

Re: [Qemu-devel] [PATCH 2/2] migration/virtio: Remove simple .get/.put use

Dear David, "Dr. David Alan Gilbert (git)" writes: > The 'virtqueue_state' and 'ringsize' can be saved using VMSTATE > macros rather than hand coded .get/.put [...] > @@ -1161,44 +1143,20 @@ static const VMStateDescription > vmstate_virtio_virtqueues = { > .minimum_version_id = 1, > .

Re: [Qemu-devel] [PATCH V6 2/8] introduce aux-bus

On Thu, Jan 14, 2016 at 1:57 AM, KONRAD Frederic wrote: > > > Le 13/01/2016 22:02, Peter Crosthwaite a écrit : >> >> On Mon, Jan 4, 2016 at 10:25 AM, wrote: >>> >>> From: KONRAD Frederic >>> >>> This introduces a new bus: aux-bus. >>> >>> It contains an address space for aux slaves devices and

Re: [Qemu-devel] [PATCH] config.status: Pass extra parameters

On Tue, Jan 12, 2016 at 11:58:48AM +, Dr. David Alan Gilbert (git) wrote: > From: "Dr. David Alan Gilbert" > > This allows you to do: > ./config.status --the-option-you-forgot > > Signed-off-by: Dr. David Alan Gilbert > --- > configure | 2 +- > 1 file changed, 1 insertion(+), 1 deletion

Re: [Qemu-devel] [PATCH v16 11/14] vfio: introduce last reset sequence id

On Tue, 2016-01-12 at 10:43 +0800, Cao jin wrote: > From: Chen Fan > > avoid multi-reset host bus, we introduce sequence id to secify which > bus is resetting. and if one of the dependent devices has been do reset. > the others should skip. > > Signed-off-by: Chen Fan > --- >  hw/vfio/pci.c | 1

Re: [Qemu-devel] [PATCH v16 10/14] pci: introduce pci bus pre reset

On Tue, 2016-01-12 at 10:43 +0800, Cao jin wrote: > From: Chen Fan > > avoid repeat bus reset, here introduce a sequence ID for each time > bus hot reset, so each vfio device could know whether they've already > been reset for that sequence ID. > > Signed-off-by: Chen Fan > --- >  hw/pci/pci.c 

Re: [Qemu-devel] [PATCH v3 2/3] nbd: Split nbd.c

On 14/01/2016 18:26, Daniel P. Berrange wrote: > On Thu, Jan 14, 2016 at 04:41:02PM +0800, Fam Zheng wrote: >> We have NBD server code and client code, all mixed in a file. Now split >> them into separate files under nbd/, and update MAINTAINERS. >> >> filter_nbd for iotest 083 is updated to keep

Re: [Qemu-devel] [PATCH 2/4] macio: add dma_active to VMStateDescription

On 14/01/16 16:51, John Snow wrote: > We can revisit this once the solution for the CPU interrupt status is > nailed down :) Sure :) > Broadly, you are right that this board has been pretty broken for a long > time, but it appears to be at least semi-functional in 2.5, so it might > be time to s

[Qemu-devel] [PATCH 6/8] target-arm: Handle exception return from AArch64 to non-EL0 AArch32

Remove the assumptions that the AArch64 exception return code was making about a return to AArch32 always being a return to EL0. This includes pulling out the illegal-SPSR checks so we can apply them for return to 32 bit as well as return to 64-bit. Signed-off-by: Peter Maydell --- target-arm/op

[Qemu-devel] [PATCH 8/8] target-arm: ignore ELR_ELx[1] for exception return to 32-bit ARM mode

The architecture requires that for an exception return to AArch32 the low bits of ELR_ELx are ignored when the PC is set from them: * if returning to Thumb mode, ignore ELR_ELx[0] * if returning to ARM mode, ignore ELR_ELx[1:0] We were only squashing bit 0; also squash bit 1 if the SPSR T bit in

[Qemu-devel] [PATCH 7/8] target-arm: Implement remaining illegal return event checks

We already implement almost all the checks for the illegal return events from AArch64 state described in the ARM ARM section D1.11.2. Add the two missing ones: * return to EL2 when EL3 is implemented and SCR_EL3.NS is 0 * return to Non-secure EL1 when EL2 is implemented and HCR_EL2.TGE is 1 (We

[Qemu-devel] [PATCH 5/8] target-arm: Fix wrong AArch64 entry offset for EL2/EL3 target

The entry offset when taking an exception to AArch64 from a lower exception level may be 0x400 or 0x600. 0x400 is used if the implemented exception level immediately lower than the target level is using AArch64, and 0x600 if it is using AArch32. We were incorrectly implementing this as checking the

[Qemu-devel] [PATCH 2/8] target-arm: Move aarch64_cpu_do_interrupt() to helper.c

Move the aarch64_cpu_do_interrupt() function to helper.c. We want to be able to call this from code that isn't AArch64-only, and the move allows us to avoid awkward #ifdeffery at the callsite. Signed-off-by: Peter Maydell --- target-arm/cpu-qom.h| 2 +- target-arm/helper-a64.c | 104 --

[Qemu-devel] [PATCH 4/8] target-arm: Pull semihosting handling out to arm_cpu_do_interrupt()

Handling of semihosting calls should depend on the register width of the calling code, not on that of any higher exception level, so we need to identify and handle semihosting calls before we decide whether to deliver the exception as an entry to AArch32 or AArch64. (EXCP_SEMIHOST is also an "inter

[Qemu-devel] [PATCH 0/8] target-arm: support mixed 32/64 bit execution beyond EL0

This patch series fixes the code for ARM exception entry and exit so that we can support mixed 32/64-bit interprocessing for cases beyond the current "EL1 is 64-bit, EL0 might be 32-bit or 64-bit". This involves: * making arm_el_is_aa64() handle EL2 and EL3 and their associated register-width b

[Qemu-devel] [PATCH 1/8] target-arm: Properly support EL2 and EL3 in arm_el_is_aa64()

Support EL2 and EL3 in arm_el_is_aa64() by implementing the logic for checking the SCR_EL3 and HCR_EL2 register-width bits as appropriate to determine the register width of lower exception levels. Signed-off-by: Peter Maydell --- target-arm/cpu.h | 33 - 1 file ch

[Qemu-devel] [PATCH 3/8] target-arm: Use a single entry point for AArch64 and AArch32 exceptions

If EL2 or EL3 is present on an AArch64 CPU, then exceptions can be taken to an exception level which is running AArch32 (if only EL0 and EL1 are present then EL1 must be AArch64 and all exceptions are taken to AArch64). To support this we need to have a single implementation of the CPU do_interrupt

Re: [Qemu-devel] [PATCH] disas/libvixl: Really suppress gcc 4.6.3 sign-compare warnings

On 14 January 2016 at 15:21, Alex Bennée wrote: > > Peter Maydell writes: > >> Commit 8acc216b956 attempted to silence some sign-compare >> warnings in libvixl by adding -Wno-sign-compare to the CFLAGS >> for the relevant objects. Unfortunately it was ineffective >> because it was placed before $

Re: [Qemu-devel] [PATCH] hw/pci: do not update the PCI mappings while Decode (I/O or memory) bit is not set in the Command register

On 01/14/2016 07:28 PM, Michael S. Tsirkin wrote: On Thu, Jan 14, 2016 at 07:20:32PM +0200, Marcel Apfelbaum wrote: On 01/14/2016 05:37 PM, Michael S. Tsirkin wrote: On Thu, Jan 14, 2016 at 05:23:27PM +0200, Marcel Apfelbaum wrote: On 01/14/2016 04:49 PM, Michael S. Tsirkin wrote: On Thu, Jan

Re: [Qemu-devel] [PATCH v2] target-arm: raise exception on misaligned LDREX operands

On 14 January 2016 at 18:00, alvise rigo wrote: > Forcing an unaligned LDREX access in aarch32, QEMU fails the following assert: > target-arm/helper.c:5921:regime_el: code should not be reached > > Running this snippet both baremetal and on top of Linux will trigger > the problem: > > static inlin

Re: [Qemu-devel] [PATCH v2] target-arm: raise exception on misaligned LDREX operands

Forcing an unaligned LDREX access in aarch32, QEMU fails the following assert: target-arm/helper.c:5921:regime_el: code should not be reached Running this snippet both baremetal and on top of Linux will trigger the problem: static inline int cmpxchg(volatile void *ptr, unsigned int old,

Re: [Qemu-devel] [PATCH v3 3/3] nbd-server: Coroutine based negotiation

On Thu, Jan 14, 2016 at 04:41:03PM +0800, Fam Zheng wrote: > Create a coroutine in nbd_client_new, so that nbd_send_negotiate doesn't > need qemu_set_block(). > > Handlers need to be set temporarily for csock fd in case the coroutine > yields during I/O. > > With this, if the other end disappears

Re: [Qemu-devel] [PATCH] hw/pci: do not update the PCI mappings while Decode (I/O or memory) bit is not set in the Command register

On Thu, Jan 14, 2016 at 07:20:32PM +0200, Marcel Apfelbaum wrote: > On 01/14/2016 05:37 PM, Michael S. Tsirkin wrote: > >On Thu, Jan 14, 2016 at 05:23:27PM +0200, Marcel Apfelbaum wrote: > >>On 01/14/2016 04:49 PM, Michael S. Tsirkin wrote: > >>>On Thu, Jan 14, 2016 at 03:30:41PM +0100, Laszlo Erse

Re: [Qemu-devel] [PATCH v3 2/3] nbd: Split nbd.c

On Thu, Jan 14, 2016 at 04:41:02PM +0800, Fam Zheng wrote: > We have NBD server code and client code, all mixed in a file. Now split > them into separate files under nbd/, and update MAINTAINERS. > > filter_nbd for iotest 083 is updated to keep the log filtered out. > > Signed-off-by: Fam Zheng

Re: [Qemu-devel] [PATCH v3 1/3] nbd: Always call "close_fn" in nbd_client_new

On Thu, Jan 14, 2016 at 04:41:01PM +0800, Fam Zheng wrote: > Rename the parameter "close" to "close_fn" to disambiguous with > close(2). > > This unifies error handling paths of NBDClient allocation: > nbd_client_new will shutdown the socket and call the "close_fn" callback > if negotiation failed

Re: [Qemu-devel] [PATCH] hw/pci: do not update the PCI mappings while Decode (I/O or memory) bit is not set in the Command register

On 01/14/2016 05:37 PM, Michael S. Tsirkin wrote: On Thu, Jan 14, 2016 at 05:23:27PM +0200, Marcel Apfelbaum wrote: On 01/14/2016 04:49 PM, Michael S. Tsirkin wrote: On Thu, Jan 14, 2016 at 03:30:41PM +0100, Laszlo Ersek wrote: 2. The same as with pxb, disable Integrated End points for pxb-pci

Re: [Qemu-devel] [PATCH 4/4] pc: set the OEM fields in the RSDT and the FADT from the SLIC

On 01/14/16 17:44, Laszlo Ersek wrote: > On 01/14/16 11:24, Michael S. Tsirkin wrote: >> On Thu, Jan 14, 2016 at 02:36:57AM +0100, Laszlo Ersek wrote: >>> The Microsoft spec about the SLIC and MSDM ACPI tables at >>> requires the OEM ID and >>> OEM

Re: [Qemu-devel] [V3 3/4] hw/i386: ACPI table for AMD IO MMU

Hi all, I recall I saw IVRS filling code in the coreboot for one of the boards supported. David, you may want to have a look there. Valentine (from the phone) On Jan 14, 2016 9:29 PM, "Kevin O'Connor" wrote: > On Thu, Jan 14, 2016 at 12:09:46PM +0200, Michael S. Tsirkin wrote: > > On Thu, Jan 1

Re: [Qemu-devel] [V3 3/4] hw/i386: ACPI table for AMD IO MMU

On Thu, Jan 14, 2016 at 07:29:40PM +0300, David kiarie wrote: > On Thu, Jan 14, 2016 at 7:19 PM, Jan Kiszka wrote: > > On 2016-01-14 17:09, David kiarie wrote: > >> On Thu, Jan 14, 2016 at 6:42 PM, Jan Kiszka wrote: > >>> On 2016-01-14 16:39, Michael S. Tsirkin wrote: > On Thu, Jan 14, 2016

Re: [Qemu-devel] [PATCH v5 0/5] Xen PCI passthru: Convert to realize()

Eric, I'll wait for your reviewed-by on the whole series before committing. Thanks, Stefano On Wed, 13 Jan 2016, Cao jin wrote: > v5 changelog: > 1. tweaked the commit message of patch 1/5 as sugguested. > 2. xen_host_pci_sysfs_path() modification as sugguested. > 3. remove local 'value' variab

Re: [Qemu-devel] [PATCH 03/51] qapi: qapi for audio backends

On 01/14/2016 06:45 AM, Kővágó, Zoltán wrote: > This patch adds structures into qapi to replace the existing > configuration structures used by audio backends currently. This qapi > will be the base of the -audiodev command line parameter (that replaces > the old environment variables based config)

Re: [Qemu-devel] [PATCH 2/4] macio: add dma_active to VMStateDescription

On 01/11/2016 06:41 PM, Mark Cave-Ayland wrote: > On 08/01/16 20:55, John Snow wrote: > >> On 01/06/2016 04:17 PM, Mark Cave-Ayland wrote: >>> On 06/01/16 20:57, John Snow wrote: >>> On 01/06/2016 03:37 PM, Mark Cave-Ayland wrote: > Make sure that we include the value of dma_active in t

Re: [Qemu-devel] [PATCH 2/2] xen-hvm: Clean up xen_ram_alloc() error handling

On Thu, 14 Jan 2016, Markus Armbruster wrote: > xen_ram_alloc() dies with hw_error() on error, even though its caller > ram_block_add() handles errors just fine. Add an Error **errp > parameter and use it. > > Leave case RUN_STATE_INMIGRATE alone, because that looks like some > kind of warning. >

Re: [Qemu-devel] [PATCH] block: Fix .bdrv_open flags

On Mon, Jan 11, 2016 at 07:32:36PM +0100, Kevin Wolf wrote: > bdrv_common_open() modified bs->open_flags after inferring the set of > options to pass to the driver's .bdrv_open callback. This means that the > cache options were correctly set in bs->open_flags (and therefore > correctly displayed in

Re: [Qemu-devel] [PATCH 4/4] pc: set the OEM fields in the RSDT and the FADT from the SLIC

On 01/14/16 11:24, Michael S. Tsirkin wrote: > On Thu, Jan 14, 2016 at 02:36:57AM +0100, Laszlo Ersek wrote: >> The Microsoft spec about the SLIC and MSDM ACPI tables at >> requires the OEM ID and >> OEM Table ID fields to be consistent between the

Re: [Qemu-devel] [PATCH 01/51] qapi: support implicit structs in OptsVisitor

On 01/14/2016 06:45 AM, Kővágó, Zoltán wrote: > They are required for flat unions (you still have to allocate the > structs). > > Signed-off-by: Kővágó, Zoltán > --- > qapi/opts-visitor.c | 15 +++ > 1 file changed, 15 insertions(+) I basically have a modified version of this patch

Re: [Qemu-devel] [PATCH v7] spec: add qcow2 bitmaps extension specification

On 01/14/2016 06:35 AM, Denis V. Lunev wrote: > On 01/12/2016 03:30 AM, John Snow wrote: >> >> On 01/11/2016 08:05 AM, Vladimir Sementsov-Ogievskiy wrote: >>> The new feature for qcow2: storing bitmaps. >>> >>> This patch adds new header extension to qcow2 - Bitmaps Extension. It >>> provides an

Re: [Qemu-devel] [PATCH] docs/qapi-code-gen.txt: Fix simple union introspection example

On 01/14/2016 08:13 AM, Markus Armbruster wrote: > The implicit tag member is named "type", not "kind". Screwed up in > commit 39a1815. > > Signed-off-by: Markus Armbruster > --- > docs/qapi-code-gen.txt | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Eric Blake However,

Re: [Qemu-devel] [PATCH 1/2] xen-hvm: Clean up xen_hvm_init() error handling

On Thu, 14 Jan 2016, Markus Armbruster wrote: > xen_hvm_init() returns -1 without cleaning up on some errors (harmless > long as the caller exit()s on error), dies with hw_error() on others. > hw_error() isn't approprate here. Clean up to exit() on all errors. > > Signed-off-by: Markus Armbruster

Re: [Qemu-devel] [PATCH 3/4] acpi: stash the OEM ID and OEM Table ID fields from an external SLIC table

On 01/14/16 11:21, Michael S. Tsirkin wrote: > On Thu, Jan 14, 2016 at 02:36:56AM +0100, Laszlo Ersek wrote: >> The SLIC table is not generated by QEMU. If the user specifies an external >> one however, then board-specific code might want to adapt other, >> auto-generated tables to it. This patch s

Re: [Qemu-devel] [PATCH 0/4] set the OEM fields in the RSDT and the FADT from the SLIC

On 01/14/16 11:23, Richard W.M. Jones wrote: > On Thu, Jan 14, 2016 at 01:06:05PM +0300, Alex wrote: >> Richard, I just posted HW test results to >> https://bugzilla.redhat.com/show_bug.cgi?id=1248758. >> Should I do it here instead? > > I saw that. Testing a virt-p2v conversion is a lot more inv

Re: [Qemu-devel] [V3 3/4] hw/i386: ACPI table for AMD IO MMU

On Thu, Jan 14, 2016 at 12:09:46PM +0200, Michael S. Tsirkin wrote: > On Thu, Jan 14, 2016 at 11:04:27AM +0300, David Kiarie wrote: > > Add IVRS table for AMD IO MMU. Also reverve MMIO > > reserve? > > > region for IO MMU via ACPI > > > It does not look like you reserve anything. > > Pls add a

Re: [Qemu-devel] [V3 3/4] hw/i386: ACPI table for AMD IO MMU

On Thu, Jan 14, 2016 at 7:19 PM, Jan Kiszka wrote: > On 2016-01-14 17:09, David kiarie wrote: >> On Thu, Jan 14, 2016 at 6:42 PM, Jan Kiszka wrote: >>> On 2016-01-14 16:39, Michael S. Tsirkin wrote: On Thu, Jan 14, 2016 at 03:15:38PM +0300, David kiarie wrote: > On Thu, Jan 14, 2016 at 1

Re: [Qemu-devel] [V3 3/4] hw/i386: ACPI table for AMD IO MMU

On 2016-01-14 17:09, David kiarie wrote: > On Thu, Jan 14, 2016 at 6:42 PM, Jan Kiszka wrote: >> On 2016-01-14 16:39, Michael S. Tsirkin wrote: >>> On Thu, Jan 14, 2016 at 03:15:38PM +0300, David kiarie wrote: On Thu, Jan 14, 2016 at 1:09 PM, Michael S. Tsirkin wrote: > On Thu, Jan

Re: [Qemu-devel] [RFC 0/5] scripts/dump-guest-memory.py: Add multi-arch support

On 01/14/16 09:48, Janosch Frank wrote: > The dump guest memory script for extracting a Linux core from a qemu > core is currently limited to amd64 and python 2. > > With this series we add support for python 3 (while maintaining python > 2 support) and add the possibility to extract dumps from VM

Re: [Qemu-devel] [PATCH v10 1/2] mirror: Rewrite mirror_iteration

On 13.01.2016 03:50, Fam Zheng wrote: > The "pnum < nb_sectors" condition in deciding whether to actually copy > data is unnecessarily strict, and the qiov initialization is > unnecessarily for bdrv_aio_write_zeroes and bdrv_aio_discard. > > Rewrite mirror_iteration to fix both flaws. > > The out

Re: [Qemu-devel] [RFC 4/5] scripts/dump-guest-memory.py: Cleanup functions

On 01/14/16 09:48, Janosch Frank wrote: > Increase readability by adding newlines and comments, as well as > removing wrong whitespaces and C style braces around conditionals and > loops. > > Signed-off-by: Janosch Frank > --- > scripts/dump-guest-memory.py | 71 > ++

Re: [Qemu-devel] [V3 3/4] hw/i386: ACPI table for AMD IO MMU

On Thu, Jan 14, 2016 at 6:42 PM, Jan Kiszka wrote: > On 2016-01-14 16:39, Michael S. Tsirkin wrote: >> On Thu, Jan 14, 2016 at 03:15:38PM +0300, David kiarie wrote: >>> On Thu, Jan 14, 2016 at 1:09 PM, Michael S. Tsirkin wrote: On Thu, Jan 14, 2016 at 11:04:27AM +0300, David Kiarie wrote: >>

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