Good point. I should fall through.
On Sat, 26 Jan 2019, 03:37 Eduardo Habkost On Fri, Jan 25, 2019 at 02:00:17PM +, Alex Bennée wrote:
> > A lot of architectures can run their 32 bit cousins on KVM so the
> > kvm_available function needs to be a little less restricting when
> > deciding if
On Fri, Jan 25, 2019 at 05:48:37PM -0600, Eric Blake wrote:
> The existing qemu-nbd --partition code claims to handle logical
> partitions up to 8, since its introduction in 2008 (commit 7a5ca86).
> However, the implementation is bogus (actual MBR logical partitions
> form a sort of linked list,
On Mon, Jan 07, 2019 at 20:04:41 -0500, Pavel Tatashin wrote:
> I did exactly the same sequence on Kaby Lake CPU and could not
> reproduce it. What is your host CPU?
>
I have some machines which display this bug and others that don't, so I
was able to figure out the difference between their
On Fri, Jan 25, 2019 at 02:00:17PM +, Alex Bennée wrote:
> A lot of architectures can run their 32 bit cousins on KVM so the
> kvm_available function needs to be a little less restricting when
> deciding if KVM is available.
>
> Signed-off-by: Alex Bennée
> ---
> scripts/qemu.py | 11
On Fri, Jan 25, 2019 at 02:21:20AM +, Kang, Luwei wrote:
> > > Intel Processor Trace required CPUID[0x14] but the cpuid level is 0xd
> > > when create a kvm guest with e.g. "-cpu qemu64,+intel-pt".
> > >
> > > Signed-off-by: Luwei Kang
> > > ---
> > > target/i386/cpu.c | 7 +++
> > > 1
On 1/21/19 10:51 AM, Peter Maydell wrote:
> The SSE-200 has two Message Handling Units (MHUs), which sit behind
> the APB PPC0. Wire up some unimplemented-device stubs for these,
> since we don't yet implement a real model of this device.
>
> Signed-off-by: Peter Maydell
> ---
>
On 1/21/19 10:51 AM, Peter Maydell wrote:
> The SYS_VERSION and SYS_CONFIG register values differ between the
> IoTKit and SSE-200. Make them configurable via QOM properties rather
> than hard-coded, and set them appropriately in the ARMSSE code that
> instantiates the IOTKIT_SYSINFO device.
>
>
On 1/21/19 10:51 AM, Peter Maydell wrote:
> Create a cluster object to hold each CPU in the SSE. They are
> logically distinct and may be configured differently (for instance
> one may not have an FPU where the other does).
>
> Signed-off-by: Peter Maydell
> ---
> include/hw/arm/armsse.h | 2
On Fri, Jan 25, 2019 at 6:22 AM Peter Maydell
wrote:
>
> Thanks for this explanation -- the patch makes a lot more sense with it.
> I'm confused though -- the XML we ship is basically what gdb itself
> ships and uses internally:
>
>
On 1/21/19 10:51 AM, Peter Maydell wrote:
> Give each CPU its own container memory region. This is necessary
> for two reasons:
> * some devices are instantiated one per CPU and the CPU sees only
>its own device
> * since a memory region can only be put into one container, we must
>give
On 1/21/19 10:51 AM, Peter Maydell wrote:
> The SSE-200 has two Cortex-M33 CPUs. These see the same view
> of memory, with the exception of the "private CPU region" which
> has per-CPU devices. Internal device interrupts for SSE-200
> devices are mostly wired up to both CPUs, with the exception of
On 1/21/19 10:51 AM, Peter Maydell wrote:
> For the IoTKit the SRAM bank size is always 32K (15 bits); for the
> SSE-200 this is a configurable parameter, which defaults to 32K but
> can be changed when it is built into a particular SoC. For instance
> the Musca-B1 board sets it to 128K (17 bits).
On 1/21/19 10:51 AM, Peter Maydell wrote:
> The SSE-200 has four banks of SRAM, each with its own
> Memory Protection Controller, where the IoTKit has only one.
> Make the number of SRAM banks a field in ARMSSEInfo.
>
> Signed-off-by: Peter Maydell
> ---
> include/hw/arm/armsse.h | 9 +++--
>
On 1/21/19 10:51 AM, Peter Maydell wrote:
> The SSE-200 has 4 banks of SRAM, each with its own internal
> Memory Protection Controller. The interrupt status for these
> extra MPCs appears in the same security controller SECMPCINTSTATUS
> register as the MPC for the IoTKit's single SRAM bank.
On 1/21/19 10:51 AM, Peter Maydell wrote:
> Rename the files that used to be iotkit.[ch] to
> armsse.[ch] to reflect the fact they new cover
> multiple Arm subsystems for embedded.
>
> Signed-off-by: Peter Maydell
> ---
> hw/arm/Makefile.objs | 2 +-
> include/hw/arm/{iotkit.h
On Tue, 22 Jan 2019 13:38:52 PST (-0800), richard.hender...@linaro.org wrote:
On 1/22/19 1:28 AM, Bastian Koppelmann wrote:
Hi,
this patchset converts the RISC-V decoder to decodetree in four major steps:
1) Convert 32-bit instructions to decodetree [Patch 1-16]:
Many of the gen_*
On 1/21/19 10:51 AM, Peter Maydell wrote:
> Rename various internal uses of 'iotkit' in hw/arm/iotkit.c to
> 'armsse', for consistency. The remaining occurences are:
> * related to the devices TYPE_IOTKIT_SYSCTL, TYPE_IOTKIT_SYSINFO,
>etc, which this refactor is not touching
> * references
On 1/21/19 10:51 AM, Peter Maydell wrote:
> The Arm SSE-200 Subsystem for Embedded is a revised and
> extended version of the older IoTKit SoC. Prepare for
> adding a model of it by refactoring the IoTKit code into
> an abstract base class which contains the functionality,
> driven by a class data
The existing qemu-nbd --partition code claims to handle logical
partitions up to 8, since its introduction in 2008 (commit 7a5ca86).
However, the implementation is bogus (actual MBR logical partitions
form a sort of linked list, with one partition per extended table
entry, rather than four logical
On 1/21/19 10:50 AM, Peter Maydell wrote:
> The Arm IoTKit was effectively the forerunner of a series of
> subsystems for embedded SoCs, named the SSE-050, SSE-100 and SSE-200:
> https://developer.arm.com/products/system-design/subsystems
> These are generally quite similar, though later
On 1/25/19 1:49 PM, Rémi Denis-Courmont wrote:
> From: Remi Denis-Courmont
>
> A flawed test lead to the instructions always being treated as
> unallocated encodings.
>
> Signed-off-by: Remi Denis-Courmont
> ---
> target/arm/translate-a64.c | 2 +-
> 1 file changed, 1 insertion(+), 1
On 1/25/19 1:49 PM, Rémi Denis-Courmont wrote:
> From: Remi Denis-Courmont
>
> This always enables IA, IB, DA and DB keys in user mode on the maximum
> CPU, in a manner that is consistent with the other CPUs. That is to say
> redefining the reset value of SCTLR_ELx registers.
>
> Without this
On 1/25/19 1:49 PM, Rémi Denis-Courmont wrote:
> From: Remi Denis-Courmont
>
> Since QEMU does not support the ARMv8.2-LVA, Large Virtual Address,
> extension (yet), the VA address space is signed 48-bits. User mode can
> only handle the positive half of the address space, so that makes a
>
(1) Fix a bug I introduced at the last moment in the last
patch set -- enable pac keys during reset, not before.
(2) Add the HWCAP bits.
(3) Add the new prctl
(4) Add a smoke test so that (1) doesn't happen again.
r~
Richard Henderson (6):
target/arm: Always enable pac keys for user-only
Initialize the keys to a non-zero value on process start.
Signed-off-by: Richard Henderson
---
linux-user/aarch64/target_syscall.h | 2 ++
linux-user/aarch64/cpu_loop.c | 31 +++--
2 files changed, 31 insertions(+), 2 deletions(-)
diff --git
Drop the pac properties. This approach cannot work as written
because the properties are applied before arm_cpu_reset, which
zeros SCTLR_EL1 (amongst everything else).
We can re-introduce the properties if they turn out to be useful.
But since linux 5.0 enables all of the keys, they may not be.
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 3c7a7c2836..775a36ccdd 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -600,6 +600,7 @@ static uint32_t
When tsz == 0, aarch32 selects the address space via exclusion,
and there are no "top_bits" remaining that require validation.
Fixes: ba97be9f4a4
Reported-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 19 +--
1 file changed, 13 insertions(+), 6
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 4cff9e1a31..3c7a7c2836 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -560,6 +560,15 @@ enum {
Signed-off-by: Richard Henderson
---
linux-user/aarch64/target_syscall.h | 7 ++
linux-user/syscall.c| 33 +
2 files changed, 40 insertions(+)
diff --git a/linux-user/aarch64/target_syscall.h
b/linux-user/aarch64/target_syscall.h
index
Signed-off-by: Richard Henderson
---
tests/tcg/aarch64/pauth-1.c | 23 +++
tests/tcg/aarch64/Makefile.target | 7 ++-
2 files changed, 29 insertions(+), 1 deletion(-)
create mode 100644 tests/tcg/aarch64/pauth-1.c
diff --git a/tests/tcg/aarch64/pauth-1.c
On 1/25/19 7:38 PM, Peter Maydell wrote:
> On Fri, 25 Jan 2019 at 18:36, Brad Smith wrote:
>>
>> On 1/25/2019 1:24 AM, Thomas Huth wrote:
>>
>>> On 2019-01-25 01:48, Brad Smith wrote:
Our ports tree has an option which results in the QEMU binaries being
linked with "-z wxneeded".
>>>
On 1/25/19 11:21 PM, Palmer Dabbelt wrote:
> Michael is no longer employed by SiFive and does not want to continue
> maintianing the RISC-V port.
"maintaining"
>
> Signed-off-by: Palmer Dabbelt
> ---
> MAINTAINERS | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/MAINTAINERS
On 1/21/19 7:22 AM, Peter Maydell wrote:
For TCG we want to distinguish which cluster a CPU is in, and
we need to do it quickly. Cache the cluster index in the CPUState
struct, by having the cluster object set cpu->cluster_index for
each CPU child when it is realized.
This means that board/SoC
On 1/21/19 7:22 AM, Peter Maydell wrote:
Include the cluster number in the hash we use to look
up TBs. This is important because a TB that is valid
for one cluster at a given physical address and set
of CPU flags is not necessarily valid for another:
the two clusters may have different views of
On 1/23/19 1:25 AM, Bastian Koppelmann wrote:
decodetree handles all instructions now so the fallback is not necessary
anymore.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Reviewed-by: Alistair Francis
Alistair
---
On 1/23/19 1:25 AM, Bastian Koppelmann wrote:
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Reviewed-by: Alistair Francis
Alistair
---
target/riscv/insn_trans/trans_rvi.inc.c | 18 +-
target/riscv/insn_trans/trans_rvm.inc.c | 14 +++---
On 1/23/19 1:25 AM, Bastian Koppelmann wrote:
gen_arith_imm() does a lot of decoding manually, which was hard to read
in case of the shift instructions and is not necessary anymore with
decodetree.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
On 1/23/19 1:25 AM, Bastian Koppelmann wrote:
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_store() did.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Reviewed-by: Alistair Francis
Alistair
---
On 1/23/19 1:25 AM, Bastian Koppelmann wrote:
We now utilizes argument-sets of decodetree such that no manual
decoding is necessary.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Reviewed-by: Alistair Francis
Alistair
---
On 1/23/19 1:25 AM, Bastian Koppelmann wrote:
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_load() did.
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
Reviewed-by: Alistair Francis
Alistair
---
Michael is no longer employed by SiFive and does not want to continue
maintianing the RISC-V port.
Signed-off-by: Palmer Dabbelt
---
MAINTAINERS | 1 -
1 file changed, 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index af339b86db76..47cb3c14298e 100644
--- a/MAINTAINERS
+++
On Fri, 18 Jan 2019 16:29:57 PST (-0800), Michael Clark wrote:
One has a basic command of English but one cannot think of a
more or less glib commit message for this commit so this is it.
Palmer, I would like to send you an invoice for this commit
but I do not know what value to place on it.
On 1/23/19 2:57 PM, Richard Henderson wrote:
Now that all tcg backends support TCG_TARGET_IMPLEMENTS_DYN_TLB,
remove the define and the old code.
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
---
include/exec/cpu-defs.h | 46
On 1/23/19 2:57 PM, Richard Henderson wrote:
Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
---
tcg/riscv/tcg-target.h | 2 +-
tcg/riscv/tcg-target.inc.c | 126 -
2 files changed, 56 insertions(+), 72 deletions(-)
From: BALATON Zoltan
This device only implemented ISA compatibility mode and native PCI IDE
mode was missing but no clients actually need ISA mode but to the
contrary, they usually want to switch to and use device in native
PCI IDE mode. Therefore implement native PCI mode and switch default
to
From: BALATON Zoltan
This function is only called once from vt82c686b_ide_realize() and its
content is simple enough to not need a separate function but be
included in realize directly (as done in other IDE models except PIIX
currently).
Signed-off-by: BALATON Zoltan
Message-id:
From: BALATON Zoltan
Parts of the SiI3112 mmio are identical to PCI IDE registers so we can
use the corresponding functions that were factored out into ide/pci.c.
This removes code duplication and simplifies the SiI3112 model which
also helped to spot a copy paste error where reading status of
From: BALATON Zoltan
The io mem ops callbacks are not specific to CMD646 but really follow
the PCI IDE spec so move these from cmd646.c to pci.c to allow other
PCI IDE implementations to use them.
Signed-off-by: BALATON Zoltan
Tested-by: Mark Cave-Ayland
Reviewed-by: John Snow
Message-id:
The following changes since commit ad7a21e81231ae64540310384fb0f87ac8758b02:
Merge remote-tracking branch 'remotes/ehabkost/tags/python-next-pull-request'
into staging (2019-01-25 17:22:20 +)
are available in the Git repository at:
https://github.com/jnsnow/qemu.git
From: BALATON Zoltan
Now that no CMD646 specific parts are left in CMD646BAR (all remaining
members are really PCI IDE specific) this struct can be deleted moving
the memory regions for PCI IDE BARs to PCIIDEState where they better
belong. The CMD646 PCI IDE model is adjusted accordingly.
From: BALATON Zoltan
The cmd646 io mem ops callbacks only need the IDEBus which is
currently passed via a CMD646BAR struct. No need to wrap it up like
that, we can pass it directly to these callbacks which then allows to
drop the IDEBus from the CMD646BAR.
Signed-off-by: BALATON Zoltan
KVM has two bugs in the handling of MSR_IA32_ARCH_CAPABILITIES:
1) Linux commit commit 1eaafe91a0df ("kvm: x86: IA32_ARCH_CAPABILITIES
is always supported") makes GET_SUPPORTED_CPUID return
arch_capabilities even if running on SVM. This makes "-cpu
host,migratable=off" incorrectly
From: BALATON Zoltan
The device is called via-ide and the modelled IDE controller is not
specific to 82C686B but is also usable independently. Therefore, change
function name prefixes accordingly to match device name.
Signed-off-by: BALATON Zoltan
Message-id:
Now that kvm_arch_get_supported_cpuid() will only return
arch_capabilities if QEMU is able to initialize the MSR properly,
we know that the feature is safely migratable.
Signed-off-by: Eduardo Habkost
---
target/i386/cpu.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/i386/cpu.c
From: BALATON Zoltan
There was a pointer to PCIIDEState in CMD646BAR which was set but
not used afterwards. Get rid of this unused variable.
Signed-off-by: BALATON Zoltan
Tested-by: Mark Cave-Ayland
Reviewed-by: John Snow
Message-id:
This series works around KVM bugs that affect the arch_capabilities
feature. One bug made the feature be enabled incorrect on AMD hosts,
and another one made the feature unsafe to enable on most Intel hosts.
With the work around, we can finally make arch_capabilities a migratable
feature.
On 1/25/19 3:34 PM, Philippe Mathieu-Daudé wrote:
> Since the ahci-test uses qemu-img, add a dependency to build it
> before using it.
> This fixes:
>
> $ gmake check-qtest V=1
> QTEST_QEMU_BINARY=x86_64-softmmu/qemu-system-x86_64 QTEST_QEMU_IMG=qemu-img
> tests/ahci-test
> Failed to
This patch makes the a TPM 2.0 with TIS interface available under the
HID 'MSF0101'. This is supported by Linux and also Windows now
recognizes the TPM 2.0 with TIS interface. Leave the TPM 1.2 as before.
Signed-off-by: Stefan Berger
---
hw/i386/acpi-build.c | 12 ++--
1 file changed,
On 01/21/2019 06:03 AM, Cornelia Huck wrote:
Add a region to the vfio-ccw device that can be used to submit
asynchronous I/O instructions. ssch continues to be handled by the
existing I/O region; the new region handles hsch and csch.
Interrupt status continues to be reported through the same
On 01/25/2019 11:19 AM, Eric Farman wrote:
On 01/21/2019 06:03 AM, Cornelia Huck wrote:
Allow to extend the regions used by vfio-ccw. The first user will be
handling of halt and clear subchannel.
Signed-off-by: Cornelia Huck
---
drivers/s390/cio/vfio_ccw_ops.c | 181
On 1/25/19 11:46 AM, Kevin Wolf wrote:
> The vendor specific designator in the Device Identification VPD page has
> two problems:
>
> 1. It defaults to the BlockBackend name (-drive id=...), which everyone
>expected to be a host detail that the guest never sees
>
> 2. With -blockdev based
On 1/25/19 11:22 AM, Christophe Fergeau wrote:
Don't forget the 0/2 cover letter for series :)
> qemu-io reimplements itself what
> error_get_progname()/error_set_progname() already does.
> This commit switches it to use this API from qemu-error.h
>
> Signed-off-by: Christophe Fergeau
> ---
>
Since the ahci-test uses qemu-img, add a dependency to build it
before using it.
This fixes:
$ gmake check-qtest V=1
QTEST_QEMU_BINARY=x86_64-softmmu/qemu-system-x86_64 QTEST_QEMU_IMG=qemu-img
tests/ahci-test
Failed to execute child process "/tmp/qemu-test.19tMRF/qemu-img" (No such
file
On 01/25/2019 05:24 AM, Cornelia Huck wrote:
On Thu, 24 Jan 2019 21:37:44 -0500
Eric Farman wrote:
On 01/24/2019 09:25 PM, Eric Farman wrote:
On 01/21/2019 06:03 AM, Cornelia Huck wrote:
[1] I think these changes are cool. We end up going into (and staying
in) state=BUSY if we get
On 01/25/2019 07:58 AM, Halil Pasic wrote:
On Thu, 24 Jan 2019 21:25:10 -0500
Eric Farman wrote:
private = dev_get_drvdata(mdev_parent_dev(mdev));
- if (private->state != VFIO_CCW_STATE_IDLE)
+ if (private->state == VFIO_CCW_STATE_NOT_OPER ||
+ private->state
On 1/25/19 11:12 AM, Alex Bennée wrote:
>> +if (table_ofs > 0xfff) {
>> +int table_hi = table_ofs & ~0xfff;
>> +int mask_hi = mask_ofs & ~0xfff;
>
> Isn't there a #define for this number here?
No. I don't know what I'd call it, either.
You're just Supposed to Know that arm
On Fri, Jan 25, 2019 at 01:56:00PM +0100, Thomas Huth wrote:
> For downstream s390x builds, we'd like to be able to build QEMU with
> CONFIG_VIRTIO_PCI disabled (since virtio-ccw is used here instead),
> but still with CONFIG_PCI enabled. This currently fails since the
> virtio-*-pci.o files are
On 1/25/19 2:06 AM, Paolo Bonzini wrote:
> From: Yang Zhong
>
> Add the new configs to default-configs/hppa-sofmmu.mak.
>
> Signed-off-by: Yang Zhong
> Message-Id: <20190123065618.3520-19-yang.zh...@intel.com>
> Signed-off-by: Paolo Bonzini
> ---
> default-configs/hppa-softmmu.mak | 1 +
>
On Fri, Jan 25, 2019 at 01:26:53AM -0200, Eduardo Habkost wrote:
> On Thu, Jan 24, 2019 at 10:08:37PM -0500, Michael S. Tsirkin wrote:
> > On Thu, Jan 24, 2019 at 05:14:43PM -0200, Eduardo Habkost wrote:
> > > On Thu, Jan 24, 2019 at 02:05:45PM -0500, Michael S. Tsirkin wrote:
> > > > On Thu, Jan
On 1/25/19 2:06 AM, Paolo Bonzini wrote:
> From: Yang Zhong
>
> Add the new configs to default-configs/alpha-sofmmu.mak.
>
> Signed-off-by: Yang Zhong
> Message-Id: <20190123065618.3520-17-yang.zh...@intel.com>
> Signed-off-by: Paolo Bonzini
> ---
> default-configs/alpha-softmmu.mak | 1 +
>
On Fri, Jan 25, 2019 at 01:26:53AM -0200, Eduardo Habkost wrote:
> > I think we need not be purists here. Most people don't lose power and
> > then it's fine and compatible. People who want more robustness need to
> > use more modern kernels, that is all.
>
> I don't think that's being purist.
On Fri, 25 Jan 2019 11:07:06 +0100
Paolo Bonzini wrote:
> Signed-off-by: Paolo Bonzini
> ---
> hw/vfio/Kconfig | 18 ++
> 1 file changed, 10 insertions(+), 8 deletions(-)
>
> diff --git a/hw/vfio/Kconfig b/hw/vfio/Kconfig
> index f896779..ebda9fd 100644
> --- a/hw/vfio/Kconfig
On Fri, Jan 25, 2019 at 11:30:10PM +0530, ksourav wrote:
> On Fri, Jan 25, 2019 at 10:14 PM Philippe Mathieu-Daudé
> wrote:
> >
> > On 1/25/19 4:24 PM, Thomas Huth wrote:
> > > On 2019-01-25 16:14, kumar sourav wrote:
> > >> Sets the category of i8042 device as DEVICE_CATEGORY_INPUT
> > >>
On Fri, Jan 25, 2019 at 08:44:40PM +0530, kumar sourav wrote:
> Sets the category of i8042 device as DEVICE_CATEGORY_INPUT
> Devices should be assigned to one of DEVICE_CATEGORY_.
>
> Signed-off-by: kumar sourav
Reviewed-by: Michael S. Tsirkin
who's merging this? Paolo?
> ---
>
On Fri, Jan 25, 2019 at 09:26:05AM +0100, Igor Mammedov wrote:
> On Wed, 23 Jan 2019 18:28:59 +
> "Dr. David Alan Gilbert" wrote:
>
> > * Michael S. Tsirkin (m...@redhat.com) wrote:
> > > On Tue, Jan 22, 2019 at 08:07:41PM +, Dr. David Alan Gilbert wrote:
> > > > Hi,
> > > > I
On 1/25/19 7:25 AM, BALATON Zoltan wrote:
> On Thu, 24 Jan 2019, BALATON Zoltan wrote:
>> On Wed, 23 Jan 2019, John Snow wrote:
>>> I guess this is technically an external change in behavior... I have no
>>> real read on if this will break anything for anyone, or if anyone was
>>> even using
On Fri, Jan 25, 2019 at 02:04:15PM -0500, Brad Smith wrote:
> On 1/25/2019 1:53 PM, Philippe Mathieu-Daudé wrote:
>
> > Hi,
> >
> > On 1/15/19 9:04 PM, Michael S. Tsirkin wrote:
> > > From: Li Qiang
> > >
> > > Assert that the return value is not an error. This is like commit
> > > 7e6478e7d4f
On Fri, Jan 25, 2019 at 03:12:45PM +, Stefan Hajnoczi wrote:
> On Fri, Jan 25, 2019 at 09:49:03AM +0100, Thomas Huth wrote:
> > On 2019-01-25 09:16, Stefano Garzarella wrote:
> > > On Fri, Jan 25, 2019 at 07:07:35AM +0100, Thomas Huth wrote:
> > >> On 2019-01-25 07:01, Thomas Huth wrote:
> >
On Fri, Jan 25, 2019 at 09:49:03AM +0100, Thomas Huth wrote:
> On 2019-01-25 09:16, Stefano Garzarella wrote:
> > On Fri, Jan 25, 2019 at 07:07:35AM +0100, Thomas Huth wrote:
> >> On 2019-01-25 07:01, Thomas Huth wrote:
> >>> On 2019-01-24 18:23, Stefano Garzarella wrote:
> If the
Since OpenBSD 6.0 [1], W^X is enforced by default [2].
TCG requires WX access. Disable W^X if it is available.
This fixes:
# lm32-softmmu/qemu-system-lm32
Could not allocate dynamic translator buffer
# sysctl kern.wxabort=1
kern.wxabort: 0 -> 1
# lm32-softmmu/qemu-system-lm32
mmap:
Fixes I encountered while trying to run QEMU test suite on OpenBSD.
More to come, but please review.
Regards,
Phil.
Philippe Mathieu-Daudé (3):
configure: Disable W^X on OpenBSD
XXX oslib-posix: Ignore fcntl("/dev/null", F_SETFL, O_NONBLOCK)
failure
WIP tests/vm: Run tests on OpenBSD
On Fri, Jan 25, 2019 at 01:48:26PM +0100, Thomas Huth wrote:
> On 2019-01-25 12:58, Liu, Changpeng wrote:
> >
> >
> >> -Original Message-
> >> From: Thomas Huth [mailto:th...@redhat.com]
> >> Sent: Friday, January 25, 2019 4:49 PM
> >> To: Stefano Garzarella ; Michael S. Tsirkin
> >> ;
Signed-off-by: Philippe Mathieu-Daudé
---
tests/vm/openbsd | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/tests/vm/openbsd b/tests/vm/openbsd
index cfe0572c59..de907dd21c 100755
--- a/tests/vm/openbsd
+++ b/tests/vm/openbsd
@@ -25,9 +25,7 @@ class
Previous to OpenBSD 6.3 [1], fcntl(F_SETFL) is not permitted on memory
devices. Do not assert fcntl failures on OpenBSD.
This fixes:
$ lm32-softmmu/qemu-system-lm32
assertion "f != -1" failed: file "util/oslib-posix.c", line 247, function
"qemu_set_nonblock"
Abort trap (core dumped)
[1]
Richard Henderson writes:
> Signed-off-by: Richard Henderson
> ---
> tcg/aarch64/tcg-target.h | 2 +-
> tcg/aarch64/tcg-target.inc.c | 100 +--
> 2 files changed, 60 insertions(+), 42 deletions(-)
>
> diff --git a/tcg/aarch64/tcg-target.h
On 1/25/2019 1:53 PM, Philippe Mathieu-Daudé wrote:
Hi,
On 1/15/19 9:04 PM, Michael S. Tsirkin wrote:
From: Li Qiang
Assert that the return value is not an error. This is like commit
7e6478e7d4f for qemu_set_cloexec.
Signed-off-by: Li Qiang
Reviewed-by: Thomas Huth
Reviewed-by: Michael
Linux v4.12 introduced[1] emulation of MSR_PLATFORM_INFO and
MSR_MISC_FEATURES_ENABLES, and enabled the
MSR_PLATFORM_INFO_CPUID_FAULT bit unconditionally. This made
guests incorrectly believe the VM emulates
MSR_MISC_FEATURES_ENABLES properly (which is not true because
QEMU has no migration code
On 25.01.2019 19:53, Philippe Mathieu-Daudé wrote:
> Hi,
>
> On 1/15/19 9:04 PM, Michael S. Tsirkin wrote:
>> From: Li Qiang
>>
>> Assert that the return value is not an error. This is like commit
>> 7e6478e7d4f for qemu_set_cloexec.
>>
>> Signed-off-by: Li Qiang
>> Reviewed-by: Thomas Huth
>>
Hi,
On 1/15/19 9:04 PM, Michael S. Tsirkin wrote:
> From: Li Qiang
>
> Assert that the return value is not an error. This is like commit
> 7e6478e7d4f for qemu_set_cloexec.
>
> Signed-off-by: Li Qiang
> Reviewed-by: Thomas Huth
> Reviewed-by: Michael S. Tsirkin
> Signed-off-by: Michael S.
When tsz == 0, aarch32 selects the address space via exclusion,
and there are no "top_bits" remaining that require validation.
Fixes: ba97be9f4a4
Reported-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 19 +--
1 file changed, 13 insertions(+), 6
On Fri, 25 Jan 2019 at 14:06, Eduardo Habkost wrote:
>
> The following changes since commit 9dd0d8111fbb8015db75a38933aee1d45f9e64a3:
>
> Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2019-01-24'
> into staging (2019-01-25 11:52:12 +)
>
> are available in the Git repository
On Fri, 25 Jan 2019 at 18:36, Brad Smith wrote:
>
> On 1/25/2019 1:24 AM, Thomas Huth wrote:
>
> > On 2019-01-25 01:48, Brad Smith wrote:
> >> Our ports tree has an option which results in the QEMU binaries being
> >> linked with "-z wxneeded".
> > Then it's maybe high time to send such changes
On 1/25/2019 1:24 AM, Thomas Huth wrote:
On 2019-01-25 01:48, Brad Smith wrote:
On 1/24/2019 11:52 AM, Daniel P. Berrangé wrote:
On Thu, Jan 24, 2019 at 05:10:19PM +0100, Philippe Mathieu-Daudé wrote:
On 1/24/19 4:56 PM, Kamil Rytarowski wrote:
On 24.01.2019 16:52, Philippe Mathieu-Daudé
The PRFM prefetch insn in the load/store with imm9 encodings
requires idx field 0b00; we were underdecoding this by
only checking !is_unpriv (which is equivalent to idx != 2).
Correctly UNDEF the unallocated encodings where idx == 0b01
and 0b11 as well as 0b10.
Reported-by: Laurent Desnogues
The "system instructions" and "system register move" subcategories
of "branches, exception generating and system instructions" for A64
only apply if bits [23:22] are zero; other values are currently
unallocated. Correctly UNDEF these unallocated encodings.
Reported-by: Laurent Desnogues
On Tue, Jan 22, 2019 at 03:53:46PM +, Paul Durrant wrote:
> There is a flaw in the xen-bus state model. To allow a frontend to re-
> connect the backend state of an online XenDevice is transitioned from
> Closed to InitWait, but this is currently done unilaterally which is
> incorrect. The
This patchset fixes the various cases of underdecoded instructions
that Laurent spotted and sent a bug report for. (The exception
is "missing default in disas_data_proc_1src", which got fixed in
commit 18de2813c35e359621a.)
thanks
-- PMM
Peter Maydell (7):
target/arm/translate-a64: Don't
In the AdvSIMD load/store single structure encodings, the
non-post-indexed case should have zeroes in [20:16] (which is the
Rm field for the post-indexed case). Bit 31 must also be zero
(a check we got right in ldst_multiple but not here). Correctly
UNDEF these unallocated encodings.
Reported-by:
In the "add/subtract (extended register)" encoding group, the "opt"
field in bits [23:22] must be zero. Correctly UNDEF the unallocated
encodings where this field is not zero.
Reported-by: Laurent Desnogues
Signed-off-by: Peter Maydell
---
target/arm/translate-a64.c | 3 ++-
1 file changed, 2
1 - 100 of 311 matches
Mail list logo
