Re: [Qemu-devel] [PATCH] hw/rdma: Add support for GID state changes for non-qmp frameworks

On Fri, May 24, 2019 at 08:24:30AM +0300, Marcel Apfelbaum wrote: > > Hi Yuval, > > On 5/5/19 1:55 PM, Yuval Shaia wrote: > > Any GID change in guest must be propogate to host. This is already done > > by firing QMP event to managment system such as libvirt which in turn > > will update the host

[Qemu-devel] [PULL 01/29] SiFive RISC-V GPIO Device

From: Fabien Chouteau QEMU model of the GPIO device on the SiFive E300 series SOCs. The pins are not used by a board definition yet, however this implementation can already be used to trigger GPIO interrupts from the software by configuring a pin as both output and input. Signed-off-by: Fabien

[Qemu-devel] [PULL 02/29] target/riscv: Do not allow sfence.vma from user mode

From: Jonathan Behrens The 'sfence.vma' instruction is privileged, and should only ever be allowed when executing in supervisor mode or higher. Signed-off-by: Jonathan Behrens Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/op_help

[Qemu-devel] [PULL 05/29] target/riscv: Use --static-decode for decodetree

From: Richard Henderson The generated functions are only used within translate.c and do not need to be global, or declared. Signed-off-by: Richard Henderson Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/Makefile.objs | 8 target/riscv/translate.c | 3 -

[Qemu-devel] [PULL 03/29] RISC-V: fix single stepping over ret and other branching instructions

From: Fabien Chouteau This patch introduces wrappers around the tcg_gen_exit_tb() and tcg_gen_lookup_and_goto_ptr() functions that handle single stepping, i.e. call gen_exception_debug() when single stepping is enabled. Theses functions are then used instead of the originals, bringing single ste

[Qemu-devel] [PULL 07/29] target/riscv: Merge argument decode for RVC shifti

From: Richard Henderson Special handling for IMM==0 is the only difference between RVC shifti and RVI shifti. This can be handled with !function. Signed-off-by: Richard Henderson Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn16.decode | 12 +++--

[Qemu-devel] [PULL 10/29] target/riscv: Split gen_arith_imm into functional and temp

From: Richard Henderson The tcg_gen_fooi_tl functions have some immediate constant folding built in, which match up with some of the riscv asm builtin macros, like mv and not. Signed-off-by: Richard Henderson Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn_tra

[Qemu-devel] [PULL 13/29] linux-user/riscv: Add the CPU type as a comment

From: Alistair Francis Signed-off-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- linux-user/riscv/target_elf.h | 1 + 1 file changed, 1 insertion(+) diff --git a/linux-user/riscv/target_elf.h b/linux-user/riscv/target_elf.h index a6716a6aac23..9dd65652ee45 100644 --- a/linux-user/risc

[Qemu-devel] [PULL 11/29] target/riscv: Remove spaces from register names

From: Richard Henderson These extra spaces make the "-d op" dump look weird. Signed-off-by: Richard Henderson Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu

[Qemu-devel] [PULL 17/29] target/riscv: Deprecate the generic no MMU CPUs

From: Alistair Francis These can now be specified via the command line so we no longer need these. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- qemu-deprecated.texi | 6 ++ 1 file changed, 6 insertions(+) diff --git a/qemu-deprecated.texi

[Qemu-devel] [PULL 09/29] target/riscv: Split RVC32 and RVC64 insns into separate files

From: Richard Henderson This eliminates all functions in insn_trans/trans_rvc.inc.c, so the entire file can be removed. Signed-off-by: Richard Henderson Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/Makefile.objs | 9 +- target/riscv/insn16-32.deco

[Qemu-devel] [PULL 15/29] target/riscv: Create settable CPU properties

From: Alistair Francis Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 49 ++ target/riscv/cpu.h | 8 2 files changed, 57 insertions(+) diff --git a/target/riscv/cpu.c b/t

[Qemu-devel] [PULL 12/29] target/riscv: Remove unused include of riscv_htif.h for virt board riscv

From: Jonathan Behrens Signed-off-by: Jonathan Behrens Reviewed-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- hw/riscv/virt.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index fc4c6b306e13..352646303420 100644 ---

[Qemu-devel] [PULL 20/29] target/riscv: Trigger interrupt on MIP update asynchronously

From: Alistair Francis The requirement of holding the iothread_mutex is burdersome when swapping the background and foreground registers in the Hypervisor extension. To avoid the requrirement let's set the interrupt asynchronously. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Si

[Qemu-devel] [PULL 14/29] riscv: virt: Allow specifying a CPU via commandline

From: Alistair Francis Signed-off-by: Alistair Francis Reviewed-by: Igor Mammedov Signed-off-by: Palmer Dabbelt --- hw/riscv/virt.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 352646303420..84d94d0c42d8 100644 --- a/hw/riscv/vi

[Qemu-devel] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 1

The following changes since commit a7b21f6762a2d6ec08106d8a7ccb11829914523f: Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-4.1-pull-request' into staging (2019-05-24 12:47:49 +0100) are available in the Git repository at: git://github.com/palmer-dabbelt/qemu.git tags/ri

[Qemu-devel] [PULL 22/29] target/riscv: Add the MPV and MTL mstatus bits

From: Alistair Francis Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu_bits.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 945aa8dbb851..fe7164754

[Qemu-devel] [PULL 21/29] target/riscv: Improve the scause logic

From: Alistair Francis No functional change, just making the code easier to read. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu_helpe

[Qemu-devel] [PULL 16/29] target/riscv: Add a base 32 and 64 bit CPU

From: Alistair Francis At the same time deprecate the ISA string CPUs. It is dobtful anyone specifies the CPUs, but we are keeping them for the Spike machine (which is about to be depreated) so we may as well just mark them as deprecated. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dab

[Qemu-devel] [PULL 04/29] target/riscv: Name the argument sets for all of insn32 formats

From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn32.decode | 10 +++--- target/riscv/translate.c | 18 ++ 2 files changed, 25 insertions(+), 3 deletions(-) diff --git a/target/riscv/i

[Qemu-devel] [PULL 25/29] target/riscv: Add the HSTATUS register masks

From: Alistair Francis Signed-off-by: Alistair Francis Reviwed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu_bits.h | 18 ++ 1 file changed, 18 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 52c21699774f..a179137bc1f

[Qemu-devel] [PULL 23/29] target/riscv: Allow setting mstatus virtulisation bits

From: Alistair Francis Signed-off-by: Alistair Francis Revieweb-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/csr.c | 17 - 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index f9d8d150e012..e6d68a99560

[Qemu-devel] [PULL 19/29] target/riscv: Mark privilege level 2 as reserved

From: Alistair Francis Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu_bits.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 7180fccf54f9..945aa8dbb851 1

[Qemu-devel] [PULL 08/29] target/riscv: Use pattern groups in insn16.decode

From: Richard Henderson This eliminates about half of the complicated decode bits within insn_trans/trans_rvc.inc.c. Signed-off-by: Richard Henderson Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn16.decode | 29 +--- target/riscv/insn_tra

[Qemu-devel] [PULL 24/29] target/riscv: Add Hypervisor CSR macros

From: Alistair Francis Add the 1.10.1 Hypervisor CSRs and remove the 1.9.1 spec versions. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu_bits.h | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/target/

[Qemu-devel] [PULL 26/29] target/riscv: Add the HGATP register masks

From: Alistair Francis Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/cpu_bits.h | 11 +++ 1 file changed, 11 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index a179137bc1f2..dc9d53d4becf 1006

[Qemu-devel] [PULL 18/29] riscv: spike: Add a generic spike machine

From: Alistair Francis Add a generic spike machine (not tied to a version) and deprecate the spike mahines that are tied to a specific version. As we can now specify the CPU via the command line we no londer need specific versions of the spike machines. Signed-off-by: Alistair Francis Acked-by:

[Qemu-devel] [PULL 28/29] target/riscv: More accurate handling of `sip` CSR

From: Jonathan Behrens According to the spec, "All bits besides SSIP, USIP, and UEIP in the sip register are read-only." Further, if an interrupt is not delegated to mode x, then "the corresponding bits in xip [...] should appear to be hardwired to zero. This patch implements both of those requir

[Qemu-devel] [PULL 27/29] target/riscv: Add checks for several RVC reserved operands

From: Richard Henderson C.ADDI16SP, C.LWSP, C.JR, C.ADDIW, C.LDSP all have reserved operands that were not diagnosed. Signed-off-by: Richard Henderson Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- target/riscv/insn16-64.decode | 10 -- target/riscv/insn16.decode|

[Qemu-devel] [PULL 29/29] target/riscv: Only flush TLB if SATP.ASID changes

From: Jonathan Behrens There is an analogous change for ARM here: https://patchwork.kernel.org/patch/10649857 Signed-off-by: Jonathan Behrens Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/csr.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --gi

Re: [Qemu-devel] [PATCH 07/19] aspeed: add support for multiple NICs

Drive by comment, since I spotted this in my inbox. When I tried to make this change (two years ago though), I additionally needed the following. Unfortunately, I don't quite remember exactly what the issue was, but I think qemu would crash trying to create more than one nic. --- hw/net/ftgmac100

Re: [Qemu-devel] [PATCH v7 00/10] hw/m68k: add Apple Machintosh Quadra 800 machine

Patchew URL: https://patchew.org/QEMU/20190525225013.13916-1-laur...@vivier.eu/ Hi, This series seems to have some coding style problems. See output below for more information: Message-id: 20190525225013.13916-1-laur...@vivier.eu Type: series Subject: [Qemu-devel] [PATCH v7 00/10] hw/m68k: add

[Qemu-devel] [PATCH v7 02/10] esp: add pseudo-DMA as used by Macintosh

There is no DMA in Quadra 800, so the CPU reads/writes the data from the PDMA register (offset 0x100, ESP_PDMA in hw/m68k/q800.c) and copies them to/from the memory. There is a nice assembly loop in the kernel to do that, see linux/drivers/scsi/mac_esp.c:MAC_ESP_PDMA_LOOP(). The start of the tran

[Qemu-devel] [PATCH v7 01/10] escc: introduce a selector for the register bit

On Sparc and PowerMac, the bit 0 of the address selects the register type (control or data) and bit 1 selects the channel (B or A). On m68k Macintosh, the bit 0 selects the channel and bit 1 the register type. This patch introduces a new parameter (bit_swap) to the device interface to indicate bi

[Qemu-devel] [PATCH v7 06/10] hw/m68k: add macfb video card

Co-developed-by: Mark Cave-Ayland Signed-off-by: Mark Cave-Ayland Signed-off-by: Laurent Vivier Reviewed-by: Hervé Poussineau Reviewed-by: Thomas Huth --- arch_init.c| 4 + hw/display/Kconfig | 3 + hw/display/Makefile.objs | 1 + hw/display/macfb.c | 4

[Qemu-devel] [PATCH v7 03/10] dp8393x: manage big endian bus

This is needed by Quadra 800, this card can run on little-endian or big-endian bus. Signed-off-by: Laurent Vivier Tested-by: Hervé Poussineau Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Hervé Poussineau --- hw/net/dp8393x.c | 88 +++- 1 file ch

[Qemu-devel] [PATCH v7 08/10] hw/m68k: add Nubus support for macfb video card

From: Mark Cave-Ayland Co-developed-by: Mark Cave-Ayland Signed-off-by: Mark Cave-Ayland Signed-off-by: Laurent Vivier Reviewed-by: Hervé Poussineau --- hw/display/Kconfig | 1 + hw/display/macfb.c | 56 ++ include/hw/display/macfb.h | 21

[Qemu-devel] [PATCH v7 05/10] hw/m68k: implement ADB bus support for via

Co-developed-by: Mark Cave-Ayland Signed-off-by: Mark Cave-Ayland Signed-off-by: Laurent Vivier Reviewed-by: Hervé Poussineau Reviewed-by: Thomas Huth --- hw/misc/mac_via.c | 190 ++ include/hw/misc/mac_via.h | 7 ++ 2 files changed, 197 insertion

[Qemu-devel] [PATCH v7 07/10] hw/m68k: add Nubus support

Co-developed-by: Mark Cave-Ayland Signed-off-by: Mark Cave-Ayland Signed-off-by: Laurent Vivier Reviewed-by: Thomas Huth --- hw/Kconfig | 1 + hw/Makefile.objs| 1 + hw/nubus/Kconfig| 2 + hw/nubus/Makefile.objs

[Qemu-devel] [PATCH v7 00/10] hw/m68k: add Apple Machintosh Quadra 800 machine

I'm rebasing some of these patches for seven years now, too many years... if you want to test the machine, I'm sorry, it doesn't boot a MacROM, but you can boot a linux kernel from the command line. You can install your own disk using debian-installer, with: ... -M q800 \ -serial non

[Qemu-devel] [PATCH v7 04/10] hw/m68k: add via support

Co-developed-by: Mark Cave-Ayland Signed-off-by: Mark Cave-Ayland Signed-off-by: Laurent Vivier Reviewed-by: Hervé Poussineau --- hw/misc/Kconfig | 4 + hw/misc/Makefile.objs | 1 + hw/misc/mac_via.c | 666 ++ include/hw/misc/mac_vi

[Qemu-devel] [PATCH v7 10/10] hw/m68k: define Macintosh Quadra 800

If you want to test the machine, it doesn't yet boot a MacROM, but you can boot a linux kernel from the command line. You can install your own disk using debian-installer with: ./qemu-system-m68k \ -M q800 \ -serial none -serial mon:stdio \ -m 1000M -drive file=m68k.qcow2,format=q

[Qemu-devel] [PATCH v7 09/10] hw/m68k: add a dummy SWIM floppy controller

Co-developed-by: Mark Cave-Ayland Signed-off-by: Mark Cave-Ayland Signed-off-by: Laurent Vivier Reviewed-by: Hervé Poussineau --- hw/block/Kconfig| 3 + hw/block/Makefile.objs | 1 + hw/block/swim.c | 415 include/hw/block/swim.h |

[Qemu-devel] [Bug 1829682] Re: QEMU PPC SYSTEM regression - 3.1.0 and GIT - Fail to boot AIX

Got gdb for ppc64 to work and connect to qemu... Here is what I am getting when doing a "info all-registers" r0 0x0 0 r1 0xf1000816b0036890 17365889056675948688 r2 0x32b5d2053173536 r3 0x33854001664 r4 0x2dc

[Qemu-devel] [PATCH 12/19] aspeed/timer: Ensure positive muldiv delta

From: Christian Svensson If the host decrements the counter register that results in a negative delta. This is then passed to muldiv64 which only handles unsigned numbers resulting in bogus results. This fix ensures the delta being operated on is positive. Test case: kexec a kernel using aspeed

[Qemu-devel] [PATCH 13/19] aspeed/smc: add a 'sdram_base' propertie

The DRAM address of a DMA transaction depends on the DRAM base address of the SoC. Inform the SMC controller model of this value. Signed-off-by: Cédric Le Goater --- include/hw/ssi/aspeed_smc.h | 3 +++ hw/arm/aspeed_soc.c | 6 ++ hw/ssi/aspeed_smc.c | 1 + 3 files changed, 1

[Qemu-devel] [PATCH 15/19] aspeed: add a RAM memory region container

The RAM memory region is defined after the SoC is realized when the SDMC controller has cheched that the defined RAM size for the machine is correct. This is problematic for controller models requiring a link on the RAM region, for DMA support in the SMC controller for instance. Introduce a contai

[Qemu-devel] [PATCH 14/19] aspeed: remove the "ram" link

It has never been used as far as I can tell from the git history. Signed-off-by: Cédric Le Goater --- hw/arm/aspeed.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 004b0c318951..228fdbcf65e2 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -193

[Qemu-devel] [PATCH 16/19] aspeed/smc: add support for DMAs

The FMC controller on the Aspeed SoCs support DMA to access the flash modules. It can operate in a normal mode, to copy to or from the flash module mapping window, or in a checksum calculation mode, to evaluate the best clock settings for reads. The model introduces two custom address spaces for D

[Qemu-devel] [PATCH 19/19] aspeed/smc: Calculate checksum on normal DMA

From: Christian Svensson This patch adds the missing checksum calculation on normal DMA transfer. According to the datasheet this is how the SMC should behave. Verified on AST1250 that the hardware matches the behaviour. Signed-off-by: Christian Svensson Signed-off-by: Cédric Le Goater --- h

[Qemu-devel] [PATCH 17/19] aspeed/smc: add DMA calibration settings

When doing calibration, the SPI clock rate in the CE0 Control Register and the read delay cycles in the Read Timing Compensation Register are set using bit[11:4] of the DMA Control Register. Signed-off-by: Cédric Le Goater --- hw/ssi/aspeed_smc.c | 64

[Qemu-devel] [PATCH 18/19] aspeed/smc: inject errors in DMA checksum

Emulate read errors in the DMA Checksum Register for high frequencies and optimistic settings of the Read Timing Compensation Register. This will help in tuning the SPI timing calibration algorithm. The values below are those to expect from the first flash device of the FMC controller of a palmett

[Qemu-devel] [PATCH 09/19] aspeed/timer: Status register contains reload for stopped timer

From: Andrew Jeffery >From the datasheet: This register stores the current status of counter #N. When timer enable bit TMC30[N * b] is disabled, the reload register will be loaded into this counter. When timer bit TMC30[N * b] is set, the counter will start to decrement. CPU can update t

[Qemu-devel] [PATCH 10/19] aspeed/timer: Fix match calculations

From: Andrew Jeffery If the match value exceeds reload then we don't want to include it in calculations for the next event. Signed-off-by: Andrew Jeffery Signed-off-by: Cédric Le Goater --- hw/timer/aspeed_timer.c | 13 ++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --gi

[Qemu-devel] [PATCH 07/19] aspeed: add support for multiple NICs

The Aspeed SoCs have two MACs. Extend the Aspeed model to support a second NIC. Signed-off-by: Cédric Le Goater --- include/hw/arm/aspeed_soc.h | 3 ++- hw/arm/aspeed_soc.c | 33 +++-- 2 files changed, 21 insertions(+), 15 deletions(-) diff --git a/include/h

[Qemu-devel] [PATCH 11/19] aspeed/timer: Provide back-pressure information for short periods

From: Andrew Jeffery First up: This is not the way the hardware behaves. However, it helps resolve real-world problems with short periods being used under Linux. Commit 4451d3f59f2a ("clocksource/drivers/fttmr010: Fix set_next_event handler") in Linux fixed the timer driver to correctly schedule

[Qemu-devel] [PATCH 06/19] aspeed: introduce a configurable number of CPU per machine

The current models of the Aspeed SoCs only have one CPU but future ones will support SMP. Introduce a way to configure the maximum number of CPU per machine. SMP support will be activated when models for such SoCs are implemented. Signed-off-by: Cédric Le Goater --- include/hw/arm/aspeed.h |

[Qemu-devel] [PATCH 05/19] hw/arm/aspeed: Add RTC to SoC

From: Joel Stanley All systems have an RTC. The IRQ is hooked up but the model does not use it at this stage. There is no guest code that uses it, so this limitation is acceptable. Signed-off-by: Joel Stanley Reviewed-by: Peter Maydell Signed-off-by: Cédric Le Goater --- include/hw/arm/aspe

[Qemu-devel] [PATCH 08/19] aspeed/timer: Fix behaviour running Linux

From: Joel Stanley The Linux kernel driver was updated in commit 4451d3f59f2a ("clocksource/drivers/fttmr010: Fix set_next_event handler) to fix an issue observed on hardware: > RELOAD register is loaded into COUNT register when the aspeed timer > is enabled, which means the next event may be

[Qemu-devel] [PATCH 04/19] hw: timer: Add ASPEED RTC device

From: Joel Stanley The RTC is modeled to provide time and date functionality. It is initialised at zero to match the hardware. There is no modelling of the alarm functionality, which includes the IRQ line. As there is no guest code to exercise this function that is acceptable for now. Signed-of

[Qemu-devel] [PATCH 03/19] aspeed: add a per SoC mapping for the memory space

This will simplify the definition of new SoCs, like the AST2600 which should use a slightly different address space and have a different set of controllers. Signed-off-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Joel Stanley --- include/hw/arm/aspeed_soc.h | 4 +- h

[Qemu-devel] [PATCH 02/19] aspeed: add a per SoC mapping for the interrupt space

This will simplify the definition of new SoCs, like the AST2600 which should use a different CPU and a different IRQ number layout. Signed-off-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Joel Stanley --- include/hw/arm/aspeed_soc.h | 36 +++ hw/arm

[Qemu-devel] [PATCH 01/19] hw/arm/aspeed: Use object_initialize_child for correct ref. counting

From: Philippe Mathieu-Daudé As explained in commit aff39be0ed97: Both functions, object_initialize() and object_property_add_child() increase the reference counter of the new object, so one of the references has to be dropped afterwards to get the reference counting right. Otherwise the

[Qemu-devel] [PATCH 00/19] aspeed: machine extensions and fixes

Hello, This series improves the current models of the Aspeed machines in QEMU and adds new ones. It also prepares ground for the future Aspeed SoC. You will find patches for : - per SoC mappings of the memory space and the interrupt number space - a RTC model from Joel - support for multiple

Re: [Qemu-devel] hw/s390x/ipl: Dubious use of qdev_reset_all_fn

On Fri, 24 May 2019 at 20:47, Christian Borntraeger wrote: > While this patch is certainly ok, I find it disturbing that qdev devices are > being resetted, > but qom devices not. It's not a qdev-vs-QOM thing. Anything which is a DeviceState has a reset method, but only devices which are somewher

Re: [Qemu-devel] [PATCH v9 0/9] Add vhost-user-gpu

Patchew URL: https://patchew.org/QEMU/20190524130946.31736-1-marcandre.lur...@redhat.com/ Hi, This series seems to have some coding style problems. See output below for more information: Message-id: 20190524130946.31736-1-marcandre.lur...@redhat.com Type: series Subject: [Qemu-devel] [PATCH v

Re: [Qemu-devel] [PATCH v4 00/20] monitor: add asynchronous command type

Hi On Thu, May 23, 2019 at 9:52 AM Markus Armbruster wrote: > I'm not sure how asynchronous commands could support reconnect and > resume. The same way as current commands, including job commands. > > >> I'm ignoring "etc" unless you expand it into something specific. > >> > >> I'm also not tak

Re: [Qemu-devel] [PATCH 1/3] iotests: add test 255 to check bitmap life after snapshot + commit

25.05.2019 2:15, John Snow wrote: > > > On 5/23/19 11:47 AM, Vladimir Sementsov-Ogievskiy wrote: >> Two testcases with persistent bitmaps are not added here, as there are >> bugs to be fixed soon. >> >> Signed-off-by: Vladimir Sementsov-Ogievskiy >> --- >> python/qemu/__init__.py| 4 +- >>

Re: [Qemu-devel] [Qemu-block] [PATCH] block/io_uring: use pkg-config for liburing

On Sat, May 25, 2019 at 10:07 AM Stefan Hajnoczi wrote: Based-on: <20190524140337.13415-1-mehta.aar...@gmail.com> "[RFC PATCH v2 0/9] Add support for io_uring" > diff --git a/block/Makefile.objs b/block/Makefile.objs > index 262d413c6d..eed8043740 100644 > --- a/block/Makefile.objs >

[Qemu-devel] [PATCH] block/io_uring: use pkg-config for liburing

Now that liburing has pkg-config support, use it instead of hardcoding compiler flags in QEMU's build scripts. This way distros can customize the location of liburing's headers and libraries without requiring changes to QEMU. Signed-off-by: Stefan Hajnoczi --- Hi Aarushi, This change is needed t

Re: [Qemu-devel] [PATCH] migration: fix a typo

Li Qiang writes: > 'postocpy' should be 'postcopy'. > > CC: qemu-triv...@nongnu.org > Signed-off-by: Li Qiang Reviewed-by: Alex Bennée > --- > migration/ram.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/migration/ram.c b/migration/ram.c > index 4c60869226..359d